ANALOG MODELING WITH VERILOG-A

USING CADENCE TOOLS

Eng. Sherief Fathi
 Hardware Description Language (HDL)
• Inelectronics, a hardware description language (HDL) is a
specialized computer language used to describe the structure
and behavior of electronic circuits.
• Two HDLs used today:
VHDL and Verilog
Both are industrial standards and are supported
by most software tools.

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Verilog-AMS
• Combines Verilog, ...
Discrete-event / discrete-value simulation
Digital Analog
• Verilog-A, …
 Continuous-time / continuous-value System System
simulation
 Signal flow modeling Gate Circuit
 Conservative modeling

• And some extras Verilog Verilog-A

 Discrete-event / continuous value
simulation Verilog-AMS
 Automatic interface element insertion
Mixed-Level Simulation (MLS)
10000
IBS 2001
9000
8000
7000
6000
5000
4000
Mixed-Signal
3000
2000 Digital
1000
0

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Verilog-A
• Able to model analog circuits and systems

- Signal-flow models
Model relates potentials only
Useful for abstract models
- Conservative models
Model relates potentials and flows
Device modeling and loading at interfaces

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Potentials and Flows Resistor
a module resistor (a, b);
+ electrical a, b;
Potential
Conservative

Flow
parameter r = 1;
V(a,b) I(a,b) Model
analog
(potential & flow)
– V(a,b) <+ r*I(a,b);
b endmodule
Amplifier
module amp (out, in);
output out; input in;
+ + Potential
Potential

voltage out, in; Signal-Flow

V(in) V(out) parameter a = 1; Model
– – analog (potential only)
V(out) <+ a*V(in);
endmodule
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Declaring Modules

module mymod(p,n);
.............
endmodule

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Ports
module modName(outPort1, outPort2, inPort, bidirectional);
output outPort1;
output [3:0] outPort2;
input inPort;
inout bidirectional;
electrical outPort1, [3:0] outport2, inPort, bidirectional;
……
endmodule

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Constants
• parameter real res = 5e3 from (0:inf);
• parameter real percentage = 0.7 from [0:1];
• parameter integer N = 4 from (0:inf);
• parameter real poles[0:3] = { 1.0, 3.198, 4.554, 2.00 };
• parameter string transistortype = "NPN" from { "NPN", "PNP" };

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Variables
• integer a[1:64]; // an array of 64 integer values

• real float; // a variable to store real value

• real gain_factor[1:30]; // array of 30 gain multipliers

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Signal Access on Nodes, Ports, Branches
• To get (probe) values: use access function in expression
• x gets voltage between a and ground: x = V(a)
• x gets voltage between a and b: x = V(a,b)
• x gets current between a and ground: x = I(a)
• x gets current between a and b: x = I(a,b)
• To set (source) values: use access function as target in contribution
• set voltage between a and ground to x: V(a) <+ x
• set voltage between a and b to x: V(a,b) <+ x
• set current between a and ground to x: I(a) <+ x
• set current between a and b to x: I(a,b) <+ x

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The Contribution Operator : ‘<+’
• Accumulates potentials or flows to nodes, ports, and branches
• Order of contribution is not significant
module rlc (a, b);
electrical a, b;
parameter R = 1 exclude 0;
parameter C = 1;
parameter L = 1 exclude 0;
analog begin
I(a,b) <+ V(a,b) / R;
I(a,b) <+ C*ddt(V(a,b));
I(a,b) <+ idt(V(a,b) / L;
end
endmodule

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 Assignment vs Contribution
• Example1:
module test(p,n) ;
inout p,n; electrical p,n;
parameter integer a = 2; real r;
analog begin
r=a; // Now r=2
r=2*a; // The value of r is updated to r=4
V(n) <+ a; // This equation contributes by a value a , V(n) =a=2;
V(n) <+ 2*a; // A new contribution is added to V(n) , V(n) = a+2a =6;
end endmodule

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Operators
Arithmetic Operators +, -, *,**, /, %
Relational Operators <, <=, >, >=
Equality Operators ==, !=, ===, !==
Logical Operators !, &&, ||
Bit-Wise Operators ~, &, |, ^, ~^
Unary Reduction &, ~&, |, ~|, ^, ~^
Shift Operators >>, <<
Conditional Operators ?:
Concatenations {}
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Analog Operators
• Differentiator: ddt()
Time derivative of its argument
• Integrator: idt()
Time integral of its argument
Optional initial condition
• Circular integrator: idtmod()
Time integral of its argument passed through modulus
operation
• Time delay: absdelay()
Delayed version of its argument

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Standard mathematical functions

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Trigonometric and hyperbolic functions

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If Statement (SWITCH)
Example 1 Example 2
if (x1 >= 2) begin if(analysis("ic")) begin
x2= 5*x1;
x2= init_cond;
end
else if (x1<5) begin end
x2= x1/2; else if(analysis("tran")) begin
end x2= x1/2;
else begin
end
x2 = x1;
end

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Example: Resistor and Conductor
• Resistor (potential source branch) module res (a, b);
electrical a, b;
parameter real r = 1;

+
–
analog
i v=ri V(a,b) <+ r*I(a,b);
endmodule
• Conductor (flow source branch)
module cond (a, b);
v electrical a, b;
+ parameter real g = 1;
–
analog
I(a,b) <+ g*V(a,b);
i=gv endmodule

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Example: Capacitor and inductor
• Capacitor module cap (a, b);
electrical a, b;
parameter c = 1;
analog
I(a,b) <+ C*ddt(V(a,b));
endmodule
• inductor
module ind (a, b);
electrical a, b;
parameter L = 1;
analog
V(a,b) <+ L*ddt(I(a,b));
endmodule

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Example: Multiplier

//VerilogA for a multiplier, output out;

`include "constants.vams" electrical in1,in2,out;

analog begin
`include "disciplines.vams“
V(out) <+ V(in1) * V(in2);
module multiplier(in1,in2,out);
end
input in1,in2;
endmodule

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 Inserting Verilog-A model into Cadence
• Open Cadence then change the editor: editor=“gedit”

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 Inserting Verilog-A model into Cadence
• From the library manager, create a “new cell view” with a type: “veriloga”

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Inserting Verilog-A model into Cadence
• Insert the VerilogA code:

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Inserting Verilog-A model into Cadence
• Choose highlight mode > verilog

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Inserting Verilog-A model into Cadence
• Insert the VerilogA code, save the file, and close.
1. If the model does not has a syntax error, you will be asked to create a
symbol.

2. If the model has a syntax error, open the error log to identify errors and
solve it.

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 Inserting Verilog-A model into Cadence
• Define the directions of the pins i.e. : left, right, top, or bottom

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 Inserting Verilog-A model into Cadence
• Modify the symbol “optional”, then Check & Save

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 Inserting Verilog-A model into Cadence
• Now you can test your model by creating a new cell view of type “Schematic”,
and make a simple test circuit:

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Inserting Verilog-A model into Cadence

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Inserting Verilog-A model into Cadence

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Example B: TEAM Memristor model

http://webee.technion.ac.il/people/skva/Memristor%20Models
/TCAS_memristor_model_paper_final.pdf
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 Example B: TEAM
Memristor model
Note: You can access the parameters’ values
from the schematic directly

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Some useful links
• Verilog-AMS Manual

• Verilog-A model library at

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Operators

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Verilog-AMS
• Combines Verilog, ...
• Discrete-event / discrete-value simulation

• Verilog-A, …
• Continuous-time / continuous-value simulation
• Signal flow modeling
• Conservative modeling

• And some extras

• Discrete-event / continuous value simulation
• Automatic interface element insertion

38 CADENCE DESIGN
SYSTEMS, INC.
Named Branches
• Named branches are explicitly declared
• Useful when defining distinct parallel potential branches

module rlc (a, b);

electrical a, b;
parameter R = 1, C = 1, L= 1;
branch (a, b) res, cap, ind;
analog begin
V(res) <+ R*I(res);
I(cap) <+ C*ddt(V(cap));
V(ind) <+ L*ddt(I(ind));
end
endmodule

39 CADENCE DESIGN
SYSTEMS, INC.
Example: Capacitor with Initial Condition
module cap (a, b);
electrical a, b;
parameter real c=0, ic=0;
analog begin
if (analysis("ic"))
V(a,b) <+ ic;
else
I(a,b) <+ ddt(c*V(a,b));
end
endmodule

40 CADENCE DESIGN
SYSTEMS, INC.
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 Accessing Net and Branch Signals
• Examples
Vin = V(in);
CurrentThruBranch = I( myBranch );

• Indirect branch assignment

An indirect branch assignment is useful when it is difficult to solve an equation. It has this
format,
V(n) : V(p) == 0;
which can be read as "find V(n) such that V(p) is equal to zero."

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Operator Precedence
[ ] bit-select or part-select >, >=, <, <= relational
( ) parentheses ==, != logical equality
!, ~ logical and bit-wise & bit-wise AND
negation
^, ^~, ~^ bit-wise XOR and XNOR
&, |, ~&, ~|, ^, ~^, ^~
reduction operators | bit-wise OR

+, - unary arithmetic && logical AND

{ } concatenation || logical OR

*, /, % arithmetic ?: conditional

+, - arithmetic
<<, >> shift
 Analog operators and equations
• Time derivative operator
• Time integral operator
• Circular integrator operator

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The Contribution Operator – ‘<+’
• Accumulates potentials or flows to nodes, ports, and branches
• Order of contribution is not significant
module rlc (a, b);
electrical a, b;
parameter R = 1 exclude 0;
parameter C = 1;
parameter L = 1 exclude 0;
analog begin
I(a,b) <+ V(a,b) / R;
I(a,b) <+ C*ddt(V(a,b));
I(a,b) <+ idt(V(a,b) / L;
end
endmodule
The Contribution Operator – ‘<+’
• Supports implicit equations
• Solves for x when x <+ f(x)

module diode (a, c);

electrical a, c; a c
parameter is = 1f from (0:inf);
parameter rs = 0 from [0:inf);
analog begin
I(a,c) <+ is * ($limexp((V(a,c) – rs * I(a,c) ) / $vt) – 1);
end
endmodule Limiting I(a,c) on both sides
Exponential makes eqn implicit
(helps convergence)
Example: Controlled Sources
module vcvs (p, n, ps, ns); module vccs (p, n, ps, ns);
electrical p, n, ps, ns; electrical p, n, ps, ns;
output p, n; input ps, ns; output p, n; input ps, ns;
parameter gain = 1; parameter gain = 1;
analog analog
V(p,n) <+ gain*V(ps,ns); I(p,n) <+ gain*V(ps,ns);
endmodule endmodule
module ccvs (p, n, ps, ns); module cccs (p, n, ps, ns);
electrical p, n, ps, ns; electrical p, n, ps, ns;
output p, n; input ps, ns; output p, n; input ps, ns;
parameter gain = 1; parameter gain = 1;
analog analog
V(p,n) <+ gain*I(ps,ns); I(p,n) <+ gain*I(ps,ns);
endmodule endmodule
Hysteretic Relay
module relay (pout, nout, pin, nin);
voltage pout, nout, pin, nin;
input pin, nin; output pout, nout;
parameter real thresh = 0, hyst = 0;
real offset;
analog begin
@(cross(V(pin,nin) – thresh – offset, +1))
offset = –hyst;
@(cross(V(pin,nin) – thresh – offset, –1))
offset = hyst;
if (V(pin,nin) – thresh – offset > 0)
V(pout, nout) <+ 0; Switch Branch
end
endmodule
Event-Driven Modeling
• @ blocks
• Blocks of code executed upon an event
• Event types

Name Generates events …

cross() At analog signal crossings
timer() Periodically or at specific times
initial_step At beginning of simulation
final_step At end of simulation
• Time of the Last Zero Crossing; last_crossing()
Example: Record Zero Crossing Times
module zero_crossings (in);
voltage in; input in;
parameter integer dir=1 from [-1:1] exclude 0;
integer fp; real last;
analog begin
@(initial_step)
fp = $fopen( “zero-crossings”);
last = $last_crossing(V(in), dir);
Record time
@(cross(V(in), dir))
$fstrobe( fp, “%0.10e”, last); of crossing
@(final_step)
$fclose(fp);
end
endmodule
Example: Noisy Diode
module diode (a, c);
electrical a, c;
branch (a, c) diode, cap;
parameter real is=1e–14, rs=0, tf=0, cjo=0, phi=0.7;
parameter real kf=0, af=1, ef=1;
analog begin
I(diode) <+ is*($limexp(V(diode)/$vt) – 1);
I(cap) <+ ddt(tf*I(diode) - 2*cjo*sqrt(phi * (phi * V(diode)));
I(diode) <+ white_noise( 2 * `P_Q * I(diode) );
I(diode) <+ flicker_noise( kf * pow(abs(I(diode)), af), ef);
end
endmodule
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Example: Resistive RF Source
module port (p, m); +–
voltage p, m;
parameter real r=50, dc=0, mag=0, ampl=0, freq=0, phase=0;
analog begin
V(p,m) <+ 2*dc – r*I(p,m);
V(p,m) <+ 2*ac_stim(mag);
V(p,m) <+ white_noise(4*`P_K*r*$temperature);
if (analysis(“tran”))
V(p,m) <+ 2*ampl*cos(2*`M_PI*freq*$abstime+phase);
bound_step(0.1 / freq);
end
endmodule