PD -95152A

IRFBA1405PPbF
Typical Applications
l Industrial Motor Drive HEXFET® Power MOSFET
D
Benefits VDSS = 55V
l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating RDS(on) = 5.0mΩ
G
l 175°C Operating Temperature
l Fast Switching ID = 174A†
l Repetitive Avalanche Allowed up to Tjmax S

Description
Stripe Planar design of HEXFET® Power MOSFETs utilizes the latest
processing techniques to achieve extremely low on-resistance per
silicon area. Additional features of this MOSFET are a 175oC junction
operating temperature, fast switching speed and improved ruggedness
in single and repetitive avalanche. The Super-220 TM is a package that
has been designed to have the same mechanical outline and pinout as
the industry standard TO-220 but can house a considerably larger
silicon die. The result is significantly increased current handling capability
over both the TO-220 and the much larger TO-247 package. The
combination of extremely low on-resistance silicon and the Super-220 Super-220™
TM
package makes it ideal to reduce the component count in multiparalled
TO-220 applications, reduce system power dissipation, upgrade
existing designs or have TO-247 performance in a TO-220 outline. This
package has been designed to meet automotive, Q101, qualification
standard.
These benefits make this design an extremely efficient and reliable
device for use in a wide variety of applications.

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 174†
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 123† A
IDM Pulsed Drain Current  680
PD @TC = 25°C Power Dissipation 330 W
Linear Derating Factor 2.2 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 560 mJ
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy‡ mJ
dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns
TJ Operating Junction and -40 to + 175
TSTG Storage Temperature Range -55 to + 175 °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Recommended clip force 20 N
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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250μA
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 4.3 5.0 mΩ VGS = 10V, ID = 101A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250μA
gfs Forward Transconductance 69 ––– ––– S VDS = 25V, ID = 110A
––– ––– 20 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current μA
––– ––– 250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 170 260 ID = 101A
Qgs Gate-to-Source Charge ––– 44 66 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– 62 93 VGS = 10V„
td(on) Turn-On Delay Time ––– 13 ––– VDD = 38V
tr Rise Time ––– 190 ––– ID = 110A
ns
td(off) Turn-Off Delay Time ––– 130 ––– RG = 1.1Ω
tf Fall Time ––– 110 ––– VGS = 10V „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact S

Ciss Input Capacitance ––– 5480 ––– VGS = 0V

Coss Output Capacitance ––– 1210 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 280 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 5210 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 900 ––– VGS = 0V, VDS = 44V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance … ––– 1500 ––– VGS = 0V, VDS = 0V to 44V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 174†

(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 680

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 101A, VGS = 0V „
trr Reverse Recovery Time ––– 88 130 ns TJ = 25°C, IF = 101A
Qrr Reverse RecoveryCharge ––– 250 380 nC di/dt = 100A/μs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.45 °C/W
RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––
RθJA Junction-to-Ambient ––– 58
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1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

I D , Drain-to-Source Current (A)

I D , Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
100

100

10

4.5V 4.5V

20μs PULSE WIDTH 20μs PULSE WIDTH

TJ = 25 °C TJ = 175 ° C
1 10
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0
TJ = 25 ° C ID = 169A
RDS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)

TJ = 175 ° C 2.5

100 2.0
(Normalized)

1.5

10 1.0

0.5

V DS = 25V
20μs PULSE WIDTH VGS = 10V
1 0.0
4 6 8 10 12 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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100000 20
VGS = 0V, f = 1 MHZ ID = 101A
Ciss = Cgs + Cgd, Cds SHORTED VDS = 44V
VDS = 27V

VGS , Gate-to-Source Voltage (V)

Crss = Cgd
16
Coss = Cds + Cgd
C, Capacitance(pF)

10000
Ciss 12

Coss
8
1000

Crss
4

FOR TEST CIRCUIT

100 SEE FIGURE 13
0
1 10 100 0 60 120 180 240 300
VDS, Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ISD , Reverse Drain Current (A)

TJ = 175 ° C
1000
I D , Drain Current (A)

100 10us

100 100us

TJ = 25 ° C
1ms
10
10 10ms

TC = 25 ° C
TJ = 175 ° C
V GS = 0 V Single Pulse
1 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 1 10 100
VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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200 RD
LIMITED BY PACKAGE VDS

VGS
160 D.U.T.
RG
ID , Drain Current (A)

+
-VDD
120
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
80

Fig 10a. Switching Time Test Circuit

40
VDS
90%
0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

1
Thermal Response (Z thJC )

D = 0.50

0.1 0.20

0.10
0.05
0.02 SINGLE PULSE
0.01 (THERMAL RESPONSE) PDM
0.01
t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.001
0.00001 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFBA1405PPbF

1200
15V ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 41A
1000 71A
L DRIVER BOTTOM 101A
VDS

800
RG D.U.T +
- VDD
IAS A
600
20V
tp 0.01Ω

400
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp 200

0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( °C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
QGS QGD 4.0

VG
3.5
VGS(th) , Variace ( V )

Charge 3.0 ID = 250μA

Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T. 2.5

50KΩ

12V .2μF 2.0

.3μF

+
V
D.U.T. - DS
1.5
VGS -75 -50 -25 0 25 50 75 100 125 150 175
3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs
Avalanche Current (A)

100 0.01 avalanche pulsewidth, tav

assuming Δ Tj = 25°C due to
avalanche losses
0.05

0.10
10

1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

600 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
500 ID = 101A
EAR , Avalanche Energy (mJ)

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for
400 every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
300 3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
200 avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
100 6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed
0
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25 50 75 100 125 150 175
D = Duty cycle in avalanche = t av ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
Vs. Temperature EAS (AR) = PD (ave)·tav
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Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T* • Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• ISD controlled by Duty Factor "D" VDD
-
• D.U.T. - Device Under Test
VGS

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.
Period D=
P.W. Period

[VGS=10V ] ***

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% [ISD ]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

Fig 17. For N-channel HEXFET® power MOSFETs

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Super-220™ ( TO-273AA ) Package Outline

9.00 [.
11.00 [.433] B 8.00 [.
A 10.00 [.394] 5.00 [.196]
4.00 [.158] 0.25

1.50 [.059]
0.50 [.020]
4 13.50 [
15.00 [.590] 12.50 [
14.00 [.552]

1 2 3

4.00 [.157] 14.50 [.570]

3.50 [.138] 13.00 [.512]

1.00 [.039]
4X
1.30 [.051] 0.70 [.028]
3X
0.90 [.036]
2.55 [.100] 3.00 [.118]
0.25 [.010] B A 2.50 [.099]
2X

MOSFET IGBT

Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/auto
2. For the most current drawing please refer to IR website at http://www.irf.com/package/

Notes:
 Repetitive rating; pulse width limited by … Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11). as Coss while VDS is rising from 0 to 80% VDSS .Refer to AN-1001
‚ Starting TJ = 25°C, L = 0.11mH † Calculated continuous current based on maximum allowable
RG = 25Ω, IAS = 101A. (See Figure 12). junction temperature. Package limitation current is 95A.
ƒ ISD ≤ 101A, di/dt ≤ 210A/μs, VDD ≤ V(BR)DSS,
‡ Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
TJ ≤ 175°C
avalanche performance.
„ Pulse width ≤ 400μs; duty cycle ≤ 2%.

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Super-220 (TO-273AA) Part Marking Information

EXAMPLE: THIS IS AN IRFBA22N50A WITH

ASSEMBLY LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"

PART NUMBER
INTERNATIONAL RECTIFIER
IRFBA22N50A
LOGO 719C
17 89
DATE CODE
ASSEMBLY LOT CODE YEAR 7 = 1997
WEEK 19
LINE C

Note: "P" in assembly line position TOP

indicates "Lead-Free"
Super-220™ not recommended for surface mount application

Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/auto
2. For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 101N. Sepulvedablvd, El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/2011
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