THE NATIONAL INSTITUTE OF ENGINEERING

MYSURU-570008
An Autonomous Institute Affiliated to VTU, Belagavi

Seminar report
on

Study of structure and performance of stacked nanosheets

Gate-all-around transistor
Submitted in partial fulfilment for the award of degree of Bachelor of Engineering in
Electronics and Communication Engineering
Submitted by

NAME: VISHWAS L
USN:4NI19EC117

Under the guidance of

Dr. YAJUNATH KALIYATH
Assisatant professor, Dept. of ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

2022-23
 THE NATIONAL INSTITUTE OF ENGINEERING
MYSURU-570008
An Autonomous Institute Affiliated to VTU, Belagavi

CERTIFICATE

This is to certify that Mr.Vishwas L bearing USN 4NI19EC117 has given a

seminar presentation on the topic "Study of structure and performance of stacked
nanosheets Gate-all-around transistor" in partial fulfillment of curriculum prescribed
for the VII semester of B.E course in Electronics and Communication Engineering during
the year 2022-23.

Signature of Examiner 1 Signature of Examiner 2

 ACKNOWLEDGEMENT

The Satisfaction and Euphoria that accompanies successful completion of any task would
be incomplete without the mention of people who made it possible. I would like to express my deep
sense gratitude and indebtedness to the following.

I would like to thank the principal of NIE Dr.Rohini Nagapadma and HOD of ECE Dept.
Dr. Parameshwara S, for encouraging me to carry out my seminar in the college.

I specially thank to my guide Dr. Yajunath kaliyath, Assistant professor, Dept. of ECE
for his precious inputs and suggestions from time to time.

I would also like to thank my parents, friends and my college faculty who helped me a lot
in finalizing this within the limited time frame.

Vishwas L Signature

4NI19EC117
 ABSTRACT

An Integrated Circuit (IC) is a set of electronic circuits on one small flat piece (or "chip") of
semiconductor material (normally silicon). The integration of large numbers of tiny MOS (MetalOx-
ide Semiconductor) transistors into a small chip resulted in circuits that are orders of magnitude
smaller, faster, and less expensive than those constructed of discrete electronic components. The
semiconductor industry has been struggling to maintain the rate of chip performance. As a result of
technological growth requirement for high processing, fast switching transistor increased, this lead
to the development of new architectural structures for transistors.

Many semiconductor company developed their own formula for different architecture they
all come under the same concept. we will study the different structures, performence improvement,
fabrication process of GAAFET’s, Advanatages and Disadvantages of GAAFET’s.
 TABLE OF CONTENTS

1 INTRODUCTION ii

2 EVOLUTION OF TRANSISTOR STRUCTURE iii

2.1 Planar FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

2.1.1 Drawbacks of Planar transistor strucure . . . . . . . . . . . . . . . . . . . . . iv

2.2 FinFET Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

3 GATE-ALL-AROUND TRANSISTOR vii

3.1 Types of GAAFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

3.1.1 Nanosheet GAAFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

3.1.2 Nanowire GAAFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

3.2 Fabrication of GAAFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

3.3 Advantages and Disadvantages of GAAFET . . . . . . . . . . . . . . . . . . . . . . . xi

4 INDUSTRIAL EVOLUTION xi

4.1 Intel Ribbon FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

4.2 Samsung MBCFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

5 CONCLUSIONS xiv

REFERENCES xv
Gate-all-around transistor: Strucure and Performance

1 INTRODUCTION

Transistor technologies evolved over the period of time to improve channel capacity, better
switching performance, working in low voltage, improve current flow etc., we can see three major
type of transistor technology in terms of VLSI chip design which include planar transistors, FinFET
transistors and one of the advanced transistor technology that is Gate-All-Around transistors.

In this seminar we mainly focus on construction and characteristic of stacked Nano sheets
Gate-All-Around transistors by keeping the knowledge of basics of semiconductors, planar transistors
and FinFET transistors.

1. Planar transistors: The classical transistor which include the concept of gate, which
modulate the conductivity of the channel through which current flows in the channel.

2. FinFET transistors: to have more control over the flow of currnt in the channel
FinFET technology was discovered where the gate can be raised above the plane of silicon, like
Fin over water. The gate wraps around the channel on three sides of a silicon fin. This creates an
inversion layer with a much larger surface area, which allows the gate to better control the flow of
current through the transistor. This means that more current can flow through with less leakage,
and a lower gate voltage is needed to operate the transistor. In addition, the vertical geometry of
FinFETs made it possible for engineers to pack more transistors in a chip.

3. Gate-All-Around transistor (GAAFET): To further improve the control of the

transistor channel, engineers found a way to replace the vertical fin with a stack of horizontal
sheets, creating a new concept called gate-all-around field-effect transistors, which are shortened
to GAA transistors, or GAAFETs. Gate-all-around transistors use stacked nanosheets. These
separate horizontal sheets are vertically stacked so that the gate surrounds the channel on all four
sides, further reducing leakage and increasing drive current. This means superior electrical signals
pass through and between the transistors, improving chip performance.

4. Multi-Bridge Channel FET (MBCFET): MBCFET uses nanosheets stacked on

top of each other and allows for more current flow through the stack. MBCFET is compatible
with the existing FinFET design flows and manufacturing processes and thus provides enhanced
performance without an increase in area.

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2 EVOLUTION OF TRANSISTOR STRUCTURE

Through out the path of evolution transistor had different architecture and each have thier own
advantages and disadvantages. Infact engineers develop the new structure because of need in the
modern days for high speed processors, low power consumption, compatible devices.

2.1 Planar FET

As we know in 1959, Dawon Kahng and Martin M. (John) Atalla at Bell Labs invented the
metal–oxide–semiconductor field-effect transistor (MOSFET) as an offshoot to the patented FET
design. it was the simple and basic transistor structure in which the it contain diffusion layer in
which the channel will be formed and current will folw from one ed to other end called ad source
and drain terminals. the flow of current through the channel is controlled by the onother terminal
kown as gate, a layer of dielectric material is developed above the diffusion layer in which the gate
metal contact will be formed.

At the beginning these form of transistor helped in many technological growth in the semi-
conductor industry. but as the requirement for fast computing devices, high speed processor, we
need to look for new transistor architecture which can overcome the limitation and perform with
high efficiency and high speed.

the planar structure of transistor limit the performance in many aspects, which all lead
to the new transistor architecture such as FinFET, Gate-all-around FET. limitaion o the sizing of
transistor, high power consumption, poor channel control etc., reduces the transistor performance.

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Gate-all-around transistor: Strucure and Performance

2.1.1 Drawbacks of Planar transistor strucure

The question arises "Why do we need new transistor architecture".

1. Leakage current:

When Vgs<Vth, current flowing through the transistor is not zero. Known as sub threshold
condition

Id = Io.exp(V gs/βV th)

where β is non ideality factor

2. Short channel:

The channel length is comparable to the depletion layer widths of the source and drain
junctions. These effects include, in particular, drain-induced barrier lowering, velocity saturation,
quantum confinement and hot carrier degradation.

3. Low current capacity:

Due to very low channel length the current it can carry has limitations.

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2.2 FinFET Structure

We can achieve more control over the flow of current in the channel by rising the gate above the
plane of silicon, like fin above water. The gate wraps around the channel in three sides, which
creates an inversion area, which allows the gate to better control flow of current through transistor.

Why Use FinFET Devices in Place of MOSFETs?

Choosing FinFET devices instead of traditional MOSFETs happens for a variety of reasons.
Increasing computational power implies increasing computational density. More transistors are
required to achieve this, which leads to larger chips. However, for practical reasons, it is crucial to
keep the area about the same.

As previously stated, one way of achieving more computational power is by shrinking the
transistor’s size. But as the transistor’s dimensions decrease, the proximity between the drain and
the source lessens the gate electrode’s ability to control the flow of current in the channel region.
Because of this, planar MOSFETs display objectionable short-channel effects.

Another way to increase computational power is by changing the materials used for manu-
facturing the chips, but it may not be suitable from an economic standpoint.

In short, FinFET devices display superior short-channel behavior, have considerably lower
switching times, and higher current density than conventional MOSFET technology.

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Why do we need to move from FinFET

1. Limit in how high fins can go: In order get more current drive the height of the Fin
has to be increased but there is an limitation on the height of the fin.

2. Footprint Area and Speed: In finFETs, additional fins are required to increase
device speed. The process of adding parallel fins increases the footprint area, and this limits the
need for speed in finFETs with downsizing. The stacking of nanosheets is replacing traditional fins
in GAAFETs. Nanosheets are usually stacked vertically, which eliminates the need for more area.
In GAAFETs, higher speed is achieved within smaller transistors overall size when compared to
finFETs.

3. High Drive Currents: Nanosheet-based GAAFETs provide a larger drive current for
the given footprint compared to fin technology. The stacking of nanosheets creates larger effective
channel width and increases the device drive current capability compared to finFETs.

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3 GATE-ALL-AROUND TRANSISTOR

The first GAAFET was showcased in 1988 by Toshiba which was a vertical nanowire GAAFET,
and was called a Surrounding Gate Transistor (SGT). A Gate-All-Around Field Effect Transistor
(GAAFET) technology is similar in function to a FinFET transistor but the gate material surrounds
the channel from all sides. Generally, based on design, GAAFETs can have two or four gates.
Gate-All-Around Field Effect Transistor (GAAFET) technology is believed to be the successor to
FinFETs, as it provides better device performance at smaller sizes such as below 7 nm. Nanowire and
nanosheet structures are used for the fabrication of GAA transistors. The alignment of the GAAFET
structures can be parallel or perpendicular to the substrate depending on the implementation.

3.1 Types of GAAFET

3.1.1 Nanosheet GAAFET

Horizontally stacked nanosheets are emerging as an industry consensus for 5nm, according to IBM.
These devices start with alternating layers of silicon and silicon germanium (SiGe), patterned into
pillars.

Creating the initial Si/SiGe heterostructure is straightforward, and pillar patterning is

similar to fin fabrication. The next several steps are unique to nanosheet transistors, though. An
indentation in the SiGe layers makes room for an inner spacer between the source/drain, which will
eventually be deposited next to the pillar and the space where the gate will be. This spacer defines
the gate width. Then, once the inner spacers are in place, a channel release etch removes the SiGe.
ALD deposits the gate dielectric and metal into the spaces between the silicon nanosheets.

To minimize lattice distortion and other defects, the germanium content of the SiGe layers
should be as low as possible. Etch selectivity increases with Ge content, though, and erosion of
the silicon layers during either the inner spacer indentation or the channel release etch will affect
channel thickness and therefore threshold voltage.

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3.1.2 Nanowire GAAFET

In the lab, several entities are working on nanowire gate-all-around FET. For example, IBM recently
described a gate-all-around silicon nanowire FET, which achieved a nanowire pitch of 30nm and a
scaled gate pitch of 60nm. The device had an effective nanowire dimension of 12.8nm.

In IBM’s gate-all-around fabrication process, two landing pads are formed on a substrate.
The nanowires are formed and suspended horizontally on the landing pads. Then, vertical gates
are patterned over the suspended nanowires. In doing so, multiple gates are formed over a common
suspended region.

A spacer is formed. Then, the silicon nanowires are cut outside the gate region, according
to IBM. In-situ doped silicon epitaxy is then grown from the exposed cross sections of the silicon
nanowires at the edge of the spacer, according to IBM. Conventional self-aligned, nickel-based silicide
contacts and copper interconnects were used to complete the device.

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3.2 Fabrication of GAAFET

Though GAAFET semiconductor devices exhibit better performance than the prior FET designs,
the manufacturing of these devices comes with increased complexity.

The process of a nanowire GAAFET fabrication starts by growing a superlattice of alter-

nating Si and SiGe epitaxial layers. These layers form the basis for the nanowires and nanosheets.

An inner dielectric spacer layer is deposited to conserve the drain and source regions and
maintain superior administration over the gate width. The empty spaces between the nanosheets
are filled with the gate dielectric material and gate metal.

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Gate-all-around transistor: Strucure and Performance

Fabrication flow of stacked gate-all-around Si nanosheet metal-oxide-semiconductor field

effect transistors (GAA Si NS MOSFET):

(a) 200 mm p-type (100) silicon wafers after ground-plane (GP) doping,

(b) epitaxy of multi-layer GeSi/Si stacks,

(c) the pattern of fin arrays formed by a spacer image transfer (SIT),

(d) fin etch,

(e) shallow trench isolation (STI) formation, (f) dummy gate formation,

(g) Si3N4 spacers formation,

(h) epitaxy of source drain (SD),

(i) ILD0 deposition,

(j) dummy gate removal,

(k) Si NS channels release,

(l) high-k dielectric/metal gate (HK/MG) formation,

(m) chemical mechanical planarization (CMP),

(n) ILD deposition, and

(o) contact and metal.

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3.3 Advantages and Disadvantages of GAAFET

Advantages:

1. Better gate controllability as gate is all around the channel.

2. Leakage current is almost negligible (leakage current also based on the shape of channel).

3. Effect of Short channel is very less.

4. High drain current.

5. Low Subthreshold slope.

6. Corner effect is very less (negligible if channel shape is cylindrical).

Disadvantages:

1. Difficulty in fabrication as the gate is all around the channel so more chances of forming
a ruptured channel during fabrication.

2. Heating Problem.

4 INDUSTRIAL EVOLUTION

Many semiconductor industries implemented their own technique while developing the new archi-
tecture for the upgraded transistor structure. some of them are given beleow,

4.1 Intel Ribbon FET

Intel’s process name referring to Angstroms rather than nanometers. At this juncture, as mentioned
above, Intel will be transitioning from its FinFET design over to a new type of transistor, known
as a Gate-All-Around transistor, or GAAFET. In Intel’s case, the marketing name they are giving
their version is RibbonFET.

It has been widely expected that once the standard FinFET runs out of steam that the

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semiconductor manufacturing industry will pivot to GAAFET designs. Each of the leading edge
vendors call their implementation something different (RibbonFET, MBCFET), but it is all using
the same basic principle – a flexible width transistor with a number of layers helping drive transistor
current. Where FinFETs relies on multiple quantized fins for source/drain and a cell height of
multiple tracks of fins, GAAFETs enable a single fin of variable length, allowing the current for
each individual cell device to be optimized in power, performance, or area.

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Intel has been discussing GAAFETs in technical semiconductor conferences for a number of
years, at the International VLSI conference in June 2020, then CTO Dr. Mike Mayberry showcased
a diagram with the enhanced electrostatics of moving to a GAA design. At the time we asked about
Intel’s timescale for implementing GAA in volume, and were told to expect them ‘within 5 years’.
At present Intel’s RibbonFET is due to come with the 20A process, likely to be productized by the
end of 2024 based on the roadmaps outlined above.

4.2 Samsung MBCFET

Samsung has broken through the barriers to continual scaling, as it has recently announced that
it has begun production of its 3 nm process. According to Samsung, the key technology that has
allowed it to reach this point is its newest MOSFET architecture, the MBCFET.

An MBCFET can be classified as a GAA technology; however, it deviates from the industry
standard of using nanowires and instead uses a sheet-type structure with a greater width than a
wire. By utilizing a nanosheet instead of a nanowire, MBCFETs can offer several key advantages,
such as continuous channel width adjustment by controlling sheet width.

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Gate-all-around transistor: Strucure and Performance

Along with this, the MBCFET could offer a structural change enabling all four sides of the
device to act as a channel.

5 CONCLUSIONS

At the beginning planar transistors were enaugh because of the less requirements, as a result of
exponential growth in technology new constrains, high speed electronic devices, high computing
power new architecture for the transistor had to be developed. many semiconductor industries have
ongoing research on upgraded transistor structure to improve the performance of the electronic
circuit and to produce more transistor on a single semiconductor wafer.

GAA transistors are poised to become part of the most advanced chip designs in the coming
years. Because these transistors can be manufactured at a desirable cost for chipmakers, they will
help keep the mass production of advanced chips affordable, while driving up the performance of
new electronics, 5G connectivity, gaming, graphics, AI solutions, medical technology, automotive
technology and more. Additionally, GAA transistors have better performance, less leakage and
lower energy consumption, making them a more sustainable, environmentally friendly alternative
to older designs.

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REFERENCES

[1] “Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With

Twin 20-nm Gates”, Tung-Yu Liu, Fu-Ming Pan, And Jeng-Tzong Sheu, 2015.

[2] “A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate”,

Ke Han , Yannan Zhang , And Zhongliang Deng, 2020.

[3] “Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors”,

Yu-Ru Lin, Yi-Yun Yang, Yu-Hsien Lin, Erry Dwi Kurniawan, Mu-Shih Yeh, Lun-Chun Chen, And
Yung-Chun Wu, 2019.

[4] “Comprehensive Study of Stacked Nanosheet-Type Channel Based on Junctionless Gate-

All-Around ThinFilm Transistors”, Yu-Ru Lin, Yu-Hsien Lin, Yi-Yun Yang, And Yung-Chun Wu,
2018.

[5] "5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets", Anil
Kumar Gundu Department of Electronic and Computer Engineering (ECE), The Hong Kong Uni-
versity of Science and Technology, Hong Kong, Volkan Kursun Department of Electronic Systems,
Norwegian University of Science and Technology, Trondheim, Norway, 02 February 2022.

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