Improving Chip Design Performance and Productivity Using
Machine Learning Narender Hanchate Sr Machine Learning Architect, Digital and Signoff Group, Cadence Today’s Chip Design Market Landscape The semiconductor industry is experiencing a renaissance o Strong growth in 5G, autonomous driving, hyperscale compute, and industrial IoT o Underlying each of these trends is the application of Next-generation chips must be artificial intelligence (AI) and machine learning (ML) produced faster and smarter o Engineers are overloaded and need support to keep up with demand New applications and technological interdependencies are generating demand for even more compute, more functionality, faster data transmission speeds o Today’s electronics have more chips in them with no end to this trend in sight
Cadence Cerebrus - ML for Better PPA & Full Flow Productivity ML flow optimization improves designer efficiency CPU Cadence Cerebrus Manual Flow Development Process 5nm
implementation • Cadence® Cerebrus™ ran 50 flow experiments o Used Innovus™ mixed placer to improve floorplan o Other flow changes delivered better performance
To efficiently maximize the performance of new As Samsung Foundry continues to deploy up-to-date products that use emerging process nodes, digital process nodes, the efficiency of our Design Technology Co- implementation flows used by our engineering team Optimization (DTCO) program is very important, and we are need to be continuously updated. Automated design always looking for innovative ways to exceed PPA in chip flow optimization is critical for realizing product implementation. As part of our long-term partnership with development at a much higher throughput. Cadence Cadence, Samsung Foundry has used Cadence Cerebrus Cerebrus, with its innovative ML capabilities, and the and the Cadence digital implementation flow on multiple Cadence RTL-to-signoff tools have provided applications. We’ve observed more than an 8% power automated flow optimization and floorplan reduction on some of our most critical blocks in just a few exploration, improving design performance by more days versus many months of manual effort. In addition, we than 10%. Following this success, the new approach are using Cerebrus for automated floorplan power will be adopted in the development of our latest distribution network sizing, which has resulted in more than design projects. 50% better final design timing. Due to Cadence Cerebrus and the digital implementation flow delivering better PPA and significant productivity improvements, the solution has become a valuable addition to our DTCO program. Satoshi Shibatani, Director, Digital Design Technology Department, Sangyun Kim, Shared R&D EDA Division, Renesas Vice President, Design Technology, Samsung Foundry
Cadence Cerebrus: Productivity and PPA Revolution The Future of Intelligent • Unique reinforcement ML Chip Design • Delivers up to 10X better productivity and 20% PPA improvements
Automated RTL to GDS
Full-Flow Optimization • Delivers better PPA more quickly • Improves engineering team productivity
