HV257

32-Channel High Voltage

Sample and Hold Amplifier Array
Features General Description
► 32 independent high voltage amplifiers The Supertex HV257 is a 32 channel high voltage sample and
► 300V operating voltage hold amplifier array integrated circuit. It operates on a single
high voltage supply, up to 300V, and two low voltage supplies,
► 295V output voltage
VDD and VNN.
► 2.2V/µs typical output slew rate
► Adjustable output current source limit All 32 sample and hold circuits share a common analog input,
► Adjustable output current sink limit VSIG. The individual sample and hold circuits are selected by
► Internal closed loop gain of 72V/V a 5 to 32 logic decoder. The sampled voltage on the holding
► 12MΩ feedback impedance capacitor is buffered by a low voltage amplifier and amplified
by a high voltage amplifier with a closed loop gain of 72V/V.
► Layout ideal for die applications
The internal closed loop gain is set for an input voltage range
of 0V to 4.096V. The input voltage can be up to 5.0V but
Applications the output will saturate. The maximum output voltage swing is
5V below the VPP high voltage supply. The outputs can drive
► MEMS (microelectromechanical systems) driver capacitive loads of up to 3000pF.
► Piezoelectric transducer driver
The maximum output source and sink current can be adjusted
► Optical crosspoint switches (using MEMS technology)
by using two external resistors. An external RSOURCE resistor
controls the maximum sourcing current, and an external RSINK
resistor controls the maximum sinking current. The current
limit is approximated 12.5V divided by the external resistor
value. The setting is common for all 32 outputs. A low voltage
silicon junction diode is made available to help monitor the die
temperature.

Typical Application Circuit

High Voltage
Supertex HV257 Power Supply
HVOUT0
VSIG
DAC HVOUT1
y
Low Voltage
HVOUT2 x x
Power Supply
A0 HVOUT3 y
Micro
Processor A1 32 High Voltage
Low Voltage OpAmp Array MEMS
A2 Channel Array
A3 Select
Sample HVOUT30
RSOURCE

A4
and Hold
RSINK

EN HVOUT31

DGND AGND

VNN
 HV257

Absolute Maximum Ratings Package Options

Device
VPP, High voltage supply 310V 100 Lead MQFP
AVDD, Analog low voltage positive supply 8.0V HV257FG
DVDD, Digital low voltage positive supply 8.0V HV257
HV257FG-G
AVNN, Analog low voltage negative supply -7.0V -G indicates package is RoHS compliant (‘Green’)
DVNN, Digital low voltage negative supply -7.0V
Logic input voltage -0.5V to DVDD
VSIG, Analog input signal 0V to 6.0V
SRVPP, VPP ramp up/down TBDV/usec
Storage temperature range -65°C to 150°C
Maximum junction temperature 150°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device at the
absolute rating level may affect device reliability. All voltages are referenced to device ground.

Operating Conditions
Symbol Parameter Min Typ Max Units Conditions
VPP High voltage positive supply 125 - 300 V ---
VDD Low voltage positive supply 6.0 - 7.5 V ---
VNN Low voltage negative supply -4.5 - -6.5 V ---
IPP VPP supply current - - 0.8 mA VPP = 300V, All HVOUT = 0V No load
IDD VDD supply current - - 5.0 mA VDD = 6.0V to 7.5V
INN VNN supply current -6.0 - - mA VNN = -4.5V to -6.5V
TJ Operating temperature range -10 - 85 °C ---

Electrical Characteristics (over operating conditions, unless otherwise specified)

High Voltage Amplifier
Symbol Parameter Min Typ Max Units Conditions
HVOUT HVOUT voltage swing 0 - VPP-5 V ---
VINOS Input offset - - ±50 mV Input referred
HVOUT slew rate rise - 2.2 - V/µs No Load
SR
HVOUT slew rate fall - 2.0 - V/µs No Load
BW HVOUT -3dB channel bandwidth - 4.0 - KHz VPP = 300V
AO Open loop gain 70 100 - dB ---
AV Closed loop gain 68.4 72 75.6 V/V ---
Feedback resistance from HVOUT to
RFB 9.6 12 - MΩ ---
ground
CLOAD HVOUTt capacitive load 0 - 3000 pF ---
ISOURCE HVOUT sourcing current limiting range 50 - 500 µA ISOURCE = 12.5V/RSOURCE
ISINK HVOUT sinking current limiting range 50 - 500 µA ISINK = 12.5V/RSINK
External resistance range for setting
RSOURCE 25 - 250 KΩ ---
maximum current source
External resistance range for setting
RSINK 25 - 250 KΩ ---
maximum current sink
CTDC DC channel to channel crosstalk -80 - - dB ---
Power supply rejection ratio for VPP,
PSRR -40 - - dB ---
VDD, VNN

2
 HV257
Electrical Characteristics (over operating conditions, unless otherwise specified)
Sample and Hold
Symbol Parameter Min Typ Max Units Conditions

tAQ Acquisition time - 4.0 - µs ---

VPED Pedestal voltage - 1.0 - mV input referred

RSW Sample and Hold Switch resistance - 5.0 - kΩ ---

CH Sample and Hold capacitor - 10 12 pF ---

Voltage droop rate during hold time

VDROOP - 6.0 - V/s output referred
relative to input

VSIG Input signal voltage range 0 - 5.0 V ---

CSIG VSIG input capacitance - 33 - pF ---

Logic Decoder
Symbol Parameter Min Typ Max Units Conditions

tSU Set-up time-address to enable 75 - - ns ---

tH Hold time-address to enable bar 75 - - ns ---

VIH Input logic high voltage 2.4 - VDD V ---

VIL Input logic low voltage 0 - 1.2 V ---

IIH Input logic high current - - 1.0 µA VIL = VDD

IIL Input logic low current -1.0 - - µA VIL = 0V

CIN Logic input capacitance - - 15 pF ---

Decoder Truth Table Sample and Hold Timing

Selected tSU tH
A4 A3 A2 A1 A0 EN
S/H
A0-A4
L L L L L H 0
L L L L H H 1 EN Hold Sample Hold

L L L H L H 2 tR/F

L L L H H H 3 Hold Step
(Vpedestal )
HVOpamp
H H H H L H 30
Acquisition Window
H H H H H H 31

X X X X X L All Open

Temperature Diode
Symbol Parameter Min Typ Max Units Conditions
PIV Peak inverse voltage - - 5.0 V cathode to anode

VF Forward diode drop - 0.6 - V IF = 100µA, anode to cathode at TA = 25°C

IF Forward diode current - - 100 µA anode to cathode

TC VF temperature coefficient - -2.2 - mV/°C anode to cathode

3
 HV257
Block Diagram
BYP-VPP BYP-AVDD BYP-AVNN Anode Cathode

VPP To internal VPP bus

AVDD Bias Circuit To internal analog VDD bus
AVNN To internal analog VNN bus
DVDD To internal digital VDD bus
DVNN To internal digital VNN bus
AVDD
VSIG + VPP
DVDD +
CH -
- HVOUT0
Q0
AVNN
Q1 AVNN
A0 S/H -0
71R
A1
R
A2 5 to 32
A3 Decoder AVDD
A4 + VPP
+
CH -
- HVOUT1
EN AVNN
Q31 AVNN
S/H -1
DGND 71R
R
AGND

AVDD
+ VPP
HVOUT +
Current To all HVOUT CH -
RSOURCE amplifiers HVOUT31
Source -
Limiting AVNN
AVNN
HVOUT S/H - 31
Current To all HVOUT 71R
RSINK amplifiers R
Sink
Limiting

4
 HV257
Power Up/Down Issues
External Diode Protection External Diode Protection Connection
The device can be damaged due to improper power up / down
sequence. To prevent damage, please follow the acceptable power
up / down sequences, and add two external diodes as shown in VDD VPP
the diagram on the right. The first diode is a high voltage diode 1N4004 or similar
across VPP and VDD , where the anode of the diode is connected
to VDD and the cathode of the diode is connected to VPP. Any low VNN DGND
current, high voltage diode, such as a 1N4004, will be adequate.
1N5817 or similar
The second diode is a Schottky diode across VNN and DGND , where
the anode of the Schottky diode is connected to VNN , and the
cathode is connected to DGND. Any low current Schottky diode such
as a 1N5817 will be adequate. Suggested Power Up/Down Sequence
The HV257 needs all power supplies to be fully up and all channels
refreshed with VSIG = 0V to force all high voltage outputs to 0V.
Acceptable Power Up Sequences Before that time, the high voltage outputs may have temporary
The HV257 can be powered up with any of the following sequences voltage excursions above or below Gnd level depending on selected
listed below. power up sequence. To minimize the excursions:
1) VPP 2) VNN 3) VDD 4) Inputs and Anode
1) VNN 2) VDD 3) VPP 4) Inputs and Anode 1. The VDD and VNN power supplies should be applied at the same
1) VDD & VNN 2) Inputs 3) VPP 4) Anode time (or within a few nanoseconds).

Acceptable Power Down Sequences 2. All channels should be continuously refreshed with
The HV257 can be powered down with any of the following VSIG = 0V, just before, and while the VPP is ramping up.
sequences listed below. Suggested VPP ramp up speed should be 10msec or longer and
1) Inputs and Anode 2) VDD 3) VNN 4) VPP ramp down to be 1msec or longer.
1) Inputs and Anode 2) VPP 3) VDD 4) VNN
1) Anode 2) VPP 3) Inputs 4) VNN & VDD

Recommended Power Up/Down Timing

A0 - A4 0 1 2 31 0 0 1 2

EN
300V

VPP 0V

6.5V
VDD 0V

VNN 0V
-5.5V

VSIG 0V
Gnd +/- V offset X 72
HVOUT 0V

HVOUT Level at Power UP

Power Up Sequence
VNN Before VDD VDD Before VNN
VPP VPP 0V
0V

VDD 6.5V VDD 6.5V

0V 0V

VNN 0V VNN 0V
-5.5V -5.5V

HVOUT HVOUT 6.5V

0V 0V
-5.5V

5
 HV257
RSINK / RSOURCE
The VDD_BYP ,VDD_BYP ,and VNN_BYP pins are internal. high impedance nodes to follow fluctuation of power lines. The expected voltages
current. mirror gate nodes, brought out to mantain stable opamp at the VDD_BYP, and VNN_BYP pins are typically 1.5 volts from their
biasing currents in noisy power supply environments. 0.1uF/25V respectful power supply. The expected voltage at VPP_BYP is typically
bypass capacitors, added from VPP_BYP pin to VPP , from VDD_BYP pin 3V below VPP.
to VDD , and from VNN_BYP to VNN,will force the high impedance gate

VPP

BYP _VPP Cap Current limit

0.1uF / 25V

BYP _VPP
Set by RSOURCE

BYP _VDD HVOUT31

To internal biasing HVOUT0
HVOpamp HVOpamp
BYP _VDD Cap
0.1uF / 25V
VDD
Set by RSINK
BYP _VNN
Current limit
BYP _VNN Cap
0.1uF / 25V

VNN

Ground Isolation (AGND/DGND Isolation)

It is important that the AGND pin is connected to a clean ground. a gain of 72). The analog and digital ground traces on the PCB
The hold capacitors are internally connected to the AGND, and any should be physically separated to reduce digital switching noise
ground noise will directly couple to the high voltage outputs (with degrading the signal to noise performance.

DGND EN, A0 -A4

External bypass caps:
C3 C1 = 0.1µF / 500V
C2
C2, C3, C4, C5 = 0.1µF / 25V
DVNN
DVDD

DAC HVOUT
VSIG Sample LVOpamp HVOpamp
switch

C_hold 1R
10pF C_comp C_comp
AVNN AVDD VPP
C1
71R
C4 C5 C6

AGND1 (pins 89, 43)

Single star GND AGND2 (pin 39)

6
 HV257
Typical Characteristics
ISINK vs RSINK ISOURCE vs RSOURCE
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
600 600

500 500

400 400

ISOURCE (µA)
ISINK (µA)

300 300

200 200

max
max
100 100
min
min
0 0
25k 150k 250k 25k 150k 250k

RSINK (KΩ) RSOURCE (KΩ)

Acquisition Window Temperature Diode vs Temperature

(”one RC” response to one volt input step) (VPP = 300V, VDD = 6.5V, VNN = 5.5V)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
120
700 -10OC

100
+85OC
max
+25OC min 25OC
600
-10OC
80
One RC (nsec)

max
Vf (mV)

min
60 500 85OC

max
40 min
400

20

300
0 1μA 20μA 40μA 60μA 80μA 100μA
1 2 4
VSIG Level (V) Diode Biasing Current (µA)

HVOUT Charge Injection vs VSIG HVOUT Droop

(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) (VPP = 300V, VDD = 6.5V, VNN = 5.5V)
3

40

2
20
HVOUT (mV)

HVOUT (V/sec)

1
0

-20
0

25OC
-40 -1 85OC
0v 1v 2v 3v 4v -10OC
VSIG Level (V)
-2
0 150 280
HVOUT Level (V)

7
 HV257

Typical Characteristics (cont.)

VPP PSSR vs Frequency Input Offset vs VIN and Temperature
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
-50 3.5

-40 3.0
VPP PSSR (dB)

2.5
-30
2.0
-20

HVOUT (mV)
Offset at -10OC
1.5
Offset at 25OC
-10
Offset at 85OC
-2.0
0
10 100 1k 10k 100k 1M
-2.5
Frequency (Hz)
-3.0

VDD PSSR vs Frequency -3.5

(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25 C)

O

-4.0
-50
-4.5
-40 1 2 3
VIN (Volts)
VDD PSSR (dB)

-30

Gain vs VIN
-20
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC )
73.97
-10 73.96
73.95
0
10 100 1k 10 100 1M 73.94
HVOUT (V)

73.93
Frequency (Hz)
72.74
72.73
VNN PSSR vs Frequency 72.72
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 72.71
-50
72.70
72.69
-40 1 2 3
VIN (Volts)
VNN PSSR (dB)

-30

-20 HVOUT Drift

HV257DFG-5037047 Q3 Dev # 3, Channel 16
(VPP = 300V, VDD = 6.5V, VNN = -5V, VSIG=1V, TA = 25OC)
-10 73.03

73.028
0
10 100 1k 10k 100k 1M 73.026
Frequency
HVOUT (V)

73.024

73.022

73.02

73.018

73.016

73.014
0 8
Time (hours)

8
 HV257

Pad Configuration (not drawn to scale)

Byp-AVDD

Byp-AVNN
Do Not Bond.

AGND

DGND
DVNN
DVDD
For testing only

AVNN

AVDD
VSIG
Anode

Cathode
A4

RSINK A3

RSOURCE A2
BYP-VPP A1
VPP
HVOUT31 A0
EN
HVOUT30

HVOUT29

HVOUT28

HVOUT27

HVOUT26

HVOUT25

HVOUT24

HVOUT23

HVOUT22

HVOUT21

HVOUT20

HVOUT19

HVOUT18

HVOUT17
Do Not Bond.
HVOUT16
Leave Floating.
HVOUT15

HVOUT14

HVOUT13

HVOUT12

HVOUT11

HVOUT10

HVOUT9

HVOUT8

HVOUT7

HVOUT6

HVOUT5

HVOUT4

HVOUT3

HVOUT2

HVOUT1

HVOUT0

VPP
AVNN

AVDD

AGND

DVNN
DVDD
AGND

9
 HV257
Pad Coordinates
Chip size: 17160μm x 5830μm
Center of die is (0,0)

10
 HV257
Pin Description
Pin # Function Description
33,100 VPP High voltage positive supply. There are two pads.
99 BYP-VPP For additional VPP decoupling capacitor.
Analog low voltage positive supply. This should be at the same potential as DVDD. There are two
42,91 AVDD
pads.
93 BYP-AVDD For additional AVDD decoupling capacitor.
Analog low voltage negative supply. This should be at the same potential as DVNN. There are two
40,94 AVNN
pads.
92 BYP-AVNN For additional AVNN decoupling capacitor.
Digital low voltage positive supply. This should be at the same potential as AVDD. There are two
45, 87 DVDD
pads.
Digital low voltage negative supply. This should be at the same potential as AVNN. There are two
44, 88 DVNN
pads.
86 DGND Digital ground.
39, 43, 89 AGND Analog Ground. There are three pads. They need to be externally connected together.
Decoder logic input. Addressed channel will close the sample and hold switch. Sample and hold
81-85 A0 to A4
switches for unaddressed channels are kept open.
80 EN Active logic high input. Logic low will keep sample and hold switches open.
90 VSIG Common input signal for all 32 sample and hold circuits.
External resistor from RSOURCE to VNN sets output current sourcing limit. Current limit is approximately
98 RSOURCE
12.5V divided by RSOURCE resistor value.
External resistor from RSINK to VNN sets output current sinking limit. Current limit is approximately
97 RSINK
12.5V divided by RSINK resistor value.
95 Anode Anode side of a low voltage silicon diode that can be used to monitor die temperature.
96 Cathode Cathode side of a low voltage silicon diode that can be used to monitor die temperature.
1-32 HVOUT0 to VOUT31 Amplifier outputs.
34-38, 41,
NC No Connect
46-79

11
 HV257
Pin Layout
100 81

1 80

100 Lead MQFP

(top view)

30 51

31 50

Pin Configuration
Pin Function Pin Function Pin Function Pin Function
1 HVOUT31 26 HVOUT6 51 NC 76 NC
2 HVOUT30 27 HVOUT5 52 NC 77 NC
3 HVOUT29 28 HVOUT4 53 NC 78 NC
4 HVOUT28 29 HVOUT3 54 NC 79 NC
5 HVOUT27 30 HVOUT2 55 NC 80 EN
6 HVOUT26 31 HVOUT1 56 NC 81 A0
7 HVOUT25 32 HVOUT0 57 NC 82 A1
8 HVOUT24 33 VPP 58 NC 83 A2
9 HVOUT23 34 NC 59 NC 84 A3
10 HVOUT22 35 NC 60 NC 85 A4
11 HVOUT21 36 NC 61 NC 86 DGND
12 HVOUT20 37 NC 62 NC 87 DVDD
13 HVOUT19 38 NC 63 NC 88 DVNN
14 HVOUT18 39 AGND 64 NC 89 AGND
15 HVOUT17 40 AVNN 65 NC 90 VSIG
16 HVOUT16 41 NC 66 NC 91 AVDD
17 HVOUT15 42 AVDD 67 NC 92 BYP-AVNN
18 HVOUT14 43 AGND 68 NC 93 BYP-AVDD
19 HVOUT13 44 DVNN 69 NC 94 AVNN
20 HVOUT12 45 DVDD 70 NC 95 Anode
21 HVOUT11 46 NC 71 NC 96 Cathode
22 HVOUT10 47 NC 72 NC 97 RSINK
23 HVOUT9 48 NC 73 NC 98 RSOURCE
24 HVOUT8 49 NC 74 NC 99 BYP-VPP
25 HVOUT7 50 NC 75 NC 100 VPP
Note: NC = No Connect

12
 HV257

100-Lead MQFP Package Outline (FG)

20x14mm body, 3.15mm height (max.), 0.65mm pitch, 3.2mm footprint

D
D1

θ1
E
E1
Note 1
(Index Area
E1/4 x D1/4)

L2 Gauge
Plane

100 L Seating
θ Plane
L1
1
e b
Top View View B

View B
A A2 Seating
Plane

A1
Side View

Note 1:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.

Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ θ1
O
MIN 2.50 0.00 2.50 0.22 22.95 19.80 16.95 13.90 0.73 0 5O
Dimension 0.65 1.60 0.25
NOM - - 2.70 - 23.20 20.00 17.20 14.00 0.88 - -
(mm) BSC REF BSC
MAX 3.15 0.25 2.90 0.40 23.45 20.20 17.45 14.20 1.03 7O 16O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
Drawings not to scale.

Doc.# DSFP-HV257
B121106
13