Counters

What are Counters?

Counters are one of the most useful parts of a digital system. A counter is
a sequential circuit that holds the ability to count the number of clock pulses provided at
its input.
The output of the counter shows a particular sequence of states. This is so
because in the applied clock input the intervals of the pulses are known and fixed. Thus
can be used to determine the time and hence the frequency of the occurrence.
An arrangement of a group of flip-flops in a predetermined manner forms a binary
counter. The applied clock pulses are counted by the counter.
We know that a flip-flop has two possible states, therefore for n flip-flops there will
be 2n number of states and permits counting from 0 to 2n – 1.
Counter are of two types – Asynchronous and Synchronous Counters.

Asynchronous counters:
Asynchronous counters are those counters which do not operate on
simultaneous clocking. In asynchronous counter, only the first flip-flop is externally
clocked using clock pulse while the clock input for the successive flip-flops will be the
output from a previous flip-flop.
This means that only a single clock pulse is not driving all the flip-flops in the
arrangement of the counter.
Asynchronous counters are also known as ripple counters and are formed by the
successive combination of trailing edge-triggered flip-flops. It is called so because the
data ripples between the output of one flip-flop to the input of the next.
Before knowing about asynchronous counter one must know what are counters? So let
us first understand the basic idea of counters.
Circuit and Operation of Asynchronous Counter
The figure given below shows the circuit diagram of a 3-bit asynchronous counter:

Here as we can clearly see that 3 negative edge-triggered flip-flops are sequentially
connected where the output of one flip-flop is provided as the input to the next. The
input clock pulse is applied at the least significant or the first most flip-flop in the
arrangement.
Also, logic high signal i.e., 1 is provided at the J and K input terminals of the flip-flops.
Therefore, the toggling will be achieved at the negative transition of the applied clock
input.
 Let us now have a look at the timing diagram of the 3-bit asynchronous counter:

Initially when the clock input is applied at the LSB flip-flop i.e., A then the output
QA will change from 0 to 1 at the falling edge of the clock pulse. As we can see that at
the first count of a clock pulse at the falling edge, QA toggles from 0 to 1.
Further QA holds its state 1 and toggles from 1 to 0 only when another falling edge of
the clock input is received. Again QA toggles from 0 to 1 at the next falling edge of the
input clock pulse.
As we have already discussed that only the first flip-flop is triggered with an
external clock signal. So, now the output of flip-flop A will act as the clock input for
flip-flop B and the external clock signal will not be going to affect QB.
Therefore, the further toggling of the QB will depend on the falling edge of QA signal.
So, as we can see clearly in the timing diagram that QB undergoes toggling only at the
falling edge of the QA signal. And the clock input signal is not affecting the output of
flip-flop B.
Further for flip-flop C, the clock input will now be the output of flip-flop B i.e., QB.
So, the output QC will be according to the transition of QB.
As we can see in the diagram that first time QC toggles from 0 to 1 only at the first
falling edge of QB signal. And maintains the state till it reaches the next falling edge of
QB.
So, in this way, we can say that we are not simultaneously providing a clock input
to all the flip-flops in asynchronous counters.
Now the question arises by this how the counter counts the number of states?
Basically, the number of states depends on the number of flip-flops employed in the
circuit.
A 3 flip-flop arrangement counter can count the states up to 23 – 1 i.e., 8-1 = 7. Let’s
understand this by the help of the truth table given below:
 As we can see that initially, the outputs of all the 3 flip-flop is 0. But as we move
further then we see that at the first falling edge of the clock input, QA is 1 while QB and
QC are 0, thereby providing decimal equivalent as 0. Again for the second falling edge
of the clock input QB is 1 whereas QA and QC are 0, giving a decimal count 1.
Similarly, for the 3rd falling edge, QA and QB are 1 and QC is still 0. In the case of
4th falling edge, only QC is 1 while both QA and QB are 0 and so on.
In this way, we can draw the truth table by observing the timing diagram of the counters.
And the truth table provides the count of the applied input clock pulse.
Thus, we can say an asynchronous counter counts the binary value according to
the clock input applied at the least signal bit flip-flop of the arrangement.
A 3-bit counter is also known as mod 8 counter due to the presence of 8 states.
Applications of Asynchronous Counter
These are used in applications where low power consumption is required. And
are also used in frequency divider circuits, ring and Johnson counters.

Synchronous Counter:
The synchronous counter is a type of counter in which the clock signal is
simultaneously provided to each flip-flop present in the counter circuit. More specifically,
we can say that each flip-flop is triggered in synchronism with the clock input.
Unlike asynchronous counter where separate clock pulses are used to trigger the
flip-flop, all the flip-flops in synchronous counters are triggered using a single clock
pulse.
We know designing an asynchronous counter is easy then what is the reason
behind designing the synchronous counter. The answer to this question is that the
asynchronous counter has a limitation towards maximum operating frequency.
Therefore, in order to overcome this limitation, synchronous counters are designed in
which simultaneous clocking is provided. Due to simultaneous clocking, the output
varies in synchronization with the clock input.
Synchronization leads to variation in each output bit at the same time with a common
clock signal. Thereby eliminating the ripple effects and so the propagation delay.
Circuit and Operation of Synchronous Counter
Here the figure below shows a 3-bit synchronous counter:
 The circuit is composed of 3 J-K flip-flops and 2 AND gates. And the clock signal
to trigger the flip-flop is provided at the same time.
It is noteworthy here that only the input terminal of flip-flop A is provided with active high
signal and therefore it toggles at the falling edge of each clock input.
Furthermore, the input to flip-flop B will be provided through an AND gate whose
output will depend on the input and output of previous flip-flop i.e., B in this case. And
the gate turns on and causes flip-flop B to toggle only when the output of flip-flop A will
be high.
In a similar way, the input to flip-flop C will be the output of 2nd AND gate. Therefore,
flip-flop C toggles only when gate A2 will be on. And A2 will be on only in case when the
output of A1, as well as flip-flop B, will be high.
Let us now understand the operation performed by the synchronous counter by
considering a 3-bit synchronous counter:
In the beginning, the flip-flops are set at 0, thus the outputs of all the three
flip-flops i.e., QCQBQA will be 000. However, at the falling edge of the first clock pulse,
the output of flip-flop A toggles from 0 to 1. But no change will occur at the output of
flip-flop B and C because the input terminals of these two flip-flops are 0 until the next
clock pulse arrives.
Therefore, on applying the first clock pulse, the output of the flip-flops i.e., QCQBQA will
be 001.
Now further before the commencement of the 2nd clock pulse, inputs of both the
flip-flops i.e., A and B will be 1. This is so because the output of gate A1 is high. So, at
the falling edge of the 2nd clock pulse, the output of flip-flop A and B will again toggle.
Therefore, this will lead to a change in the output of flip-flip A, from 1 to 0 and flip-flop B
from 0 to 1.
Hence now the output will be 010. Thus this causes the turning off both gate
A1 and A2.
Again when 3rd clock pulse is applied, the at its falling edge, again the output of flip-flop
A toggles. This causes the turning on of gate A1. And due to this gate A2 will also turn
on and therefore the output will be 011.
On moving further when 4th clock pulse is applied, the inputs to all the 3 flip-flops in the
circuits are high. Therefore, the falling edge of the 4th flip flop will toggle the outputs of
all the flip-flop, thereby changing QA and QB to 0 and QC to 1. Hence the overall output
for this particular clock pulse will be 100.
This will cause the turning off of gates A1 and A2. So, when the next clock pulse
arrives, then at the falling edge of the 5th clock pulse, the output of flip-flop A will again
toggles from 0 to 1. So, now QCQBQA will be 101. However, this will also cause the
turning on of A1 and A2.
So, when 6th clock pulse is applied then at its falling edge flip-flop A toggles from 1 to 0.
And also the input to flip-flop B is high therefore, its output toggles from 0 to 1. Thus, in
this case, QCQBQA will be 110.
 The process further continues in this way and at the falling edge of 8th clock
pulse, the output of all the flip-flops QCQBQA will reset to 000.
It is noteworthy in case of synchronous counters that the resetting of all the flip-flops in
the circuit occurs at the same time. Thus the settling time of the counter is equivalent to
the propagation delay time of each flip-flop in the circuit.
Thus the synchronous counter can be operated with a clock signal of high frequency.
Timing Diagram of 3-bit Synchronous Counter
So, from the above explanation the truth table for the 3-bit synchronous counter is given
as:

Also, the figure here shows the timing diagram of the synchronous counter:

TAJ4360