Verilog Vs SV

The document compares Verilog and SystemVerilog, which are hardware description languages. Verilog is based on modules and supports wire and reg datatypes, while SystemVerilog is based on classes and supports more complex datatypes. SystemVerilog was originally intended as an extension to Verilog and adds object oriented capabilities.

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Verilog Vs SV

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jagadeesh

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S.No.

VERILOG SYSTEMVERILOG
SystemVerilog is a combination of both
Verilog is a Hardware Hardware Description Language (HDL)
Description Language and Hardware Verification Language
01. (HDL). (HVL).

Verilog language is used SystemVerilog language is used to

to structure and model model, design, simulate, test and
02. electronic systems. implement electronic system.

It supports structured It supports structured and object

03. paradigm. oriented paradigm.

Verilog is based on SystemVerilog is based on class level

04. module level testbench. testbench.

It is standardized as IEEE
05. 1364. It is standardized as IEEE 1800-2012.

Verilog is influenced by C
language and Fortran SystemVerilog is based on Verilog,
06. programming language. VHDL and c++ programming language.

It has file extension .v

07. or .vh It has file extension .sv or .svh

It supports Wire and Reg It supports various datatypes like enum,

08. datatype. union, struct, string, class.

It is based on hierarchy of
09. modules. It is based on classes.

It was began in 1983 as

proprietary language for It was originally intended as an
10. hardware modelling. extension to Verilog in the year 2005.

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