Verilog for

Digital Design
Chapter 1:
Introduction

Verilog for Digital Design

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Frank Vahid and Roman Lysecky
 Digital Systems

Verilog for Digital Design

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Frank Vahid and Roman Lysecky
 Digital Systems
• Digital systems surround us
– Electronic system operating on 0s and 1s
– Typically implemented on an Integrated Circuit (IC) –
"chip"
• Desktop/laptop computers ("PCs") are the most
popular examples
• Other increasingly common examples
– Consumer electronics: Cell phones, portable music
players, cameras, video game consoles, electronic
music instruments, ...
– Medical equipment: Hearing aids, pacemakers, life
support systems, ...
– Automotive electronics: Engine control, brakes, ...
– Military equipment
– Networking components: Routers, switches, ...
– Many, many more...
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 Hardware Description Languages (HDLs)
• You have already taken one course on digital design. The name of that particular course is digital
logic design. In that course you have learned the basics of Boolean algebra and two types of digital
circuits: (1) combinational circuits and (2) Sequential circuits.
• In digital logic design course, you just studies the basic principles of digital circuits and did not
study any language that you can use for the designing of digital systems.
• Although, u know some programming languages like Java and C++. Java and C++ can be used for
deigning digital systems ?? The answer is NO. Why ?? The answer is that we use these languages
ONLY for software and Not for hardware.
• For hardware (digital systems), we use hardware description languages for designing. These are
not the programming languages like C or Java. Therefore, if you want to design hardware, u must
need hardware description languages (HDL).
• Examples of hardware languages are Verilog and VHDL.
• In this course, u will learn Verilog ONLY.

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 An important question
• Why HDL is used for designing digital systems
????
• For u, this question is important….. Because u are going to learn an
HDL (Verilog) for designing digital systems.
• You will find the reasons in the next slide…………………………..

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 Transistors per IC (millions)
100,000

Digital Systems and HDLs 10,000

1,000

100
• Typical digital components per IC
– 1960s/1970s: 10-1,000 transistors 10
– 1980s: 1,000-100,000 transistors

1997

2000

2003

2006

2009

2012

2015

2018
– 1990s: Millions transistors
– 2000s: Billions transistors.
Inputs: b; Outputs: x
– Why more transistors per IC?? x=0
– When we are able to put more transistors per IC, it
diagrams Off b’
will increase the processing speed of the IC
b
• 1970s x=1 x=1 x=1
On1 On2 On3
– IC behavior documented using schematics
natural
combination of schematics, language Combinational Logic
diagrams, and natural language b x

outputs
inputs
(e.g., English)

FSM

FSM
b x
"The system has four states. Combinational n1

• 1980s When in state Off, the logic

n0
n1
system outputs 0 and stays s1 s0
– Simulating circuits becoming more in state Off until the input clk State register
important (programming in HDL) becomes 1. In that case, the n0

• Schematics commonplace system enters state On1,

• Simulating schematic helped followed by On2, and then s1 s0
ensure circuit was correct before On3, in which the system clk State register
costly implementation outputs 1. The system then
returns to state Off."
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 HDLs for Simulation
• Simulations are used to verify the
functional correctness of the
program.
• Just like, u write the program in C
and Java and then run it using a
// CombLogic
compiler for the language. always @(State, B) begin
case (State)
• Similarly, HDL program is also run S_Off: begin
X <= 0;
using a compiler for functional if (B == 0)
StateNext <= S_Off;
verification/testing. else
Clk_s

StateNext <= S_On1;

• Hardware description languages end
Rst_s

S_On1: begin
(HDLs) are Machine-readable X <= 1; Simulation B_s
textual languages for describing end
StateNext <= S_On2; X_s

hardware S_On2: begin 10 20 30 40 50 60 70 80 90 100110

X <= 1;
• Text language could be more end
StateNext <= S_On3;

efficient means of circuit entry than S_On3: begin

X <= 1;
graphical language StateNext <= S_Off;
end
endcase
Verilog for Digital Design end
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 module DoorOpener(C,H,P,F);
input C, H, P;
output F;
Verilog reg F;

always @(C,H,P)
begin
• Verilog F <= (~C) & (H | P);
end
– Defined in 1985 at Gateway Design Automation Inc., endmodule
which was then acquired by Cadence Design
Systems ENTITY DoorOpener IS
– C-like syntax PORT (c, h, p: IN std_logic;
f: OUT std_logic);
– Initially a proprietary language, but became open END DoorOpener;
standard in early 1990s, then IEEE standard
("1364") in 1995, revised in 2002, and again in 2005. ARCHITECTURE Beh OF DoorOpener IS
BEGIN
• Other HDLs PROCESS(c, h, p)
– VHDL BEGIN
f <= NOT(c) AND (h OR p);
• VHSIC Hardware Description Language / defined in END PROCESS;
1980s / U.S. Dept. of Defense project / Ada-like syntax / END Beh;
IEEE standard ("1076") in 1987
• VHDL & Verilog very similar in capabilities, differ mostly #include "systemc.h"
SC_MODULE(DoorOpener)
in syntax {
– SystemC sc_in<sc_logic> c, h, p;
sc_out<sc_logic> f;
• Defined in 2000s by several companies / C++ libraries
and macro routines / IEEE standard ("1666") in 2005 SC_CTOR(DoorOpener)
{
• Excels for system-level; cumbersome for logic level SC_METHOD(comblogic);
sensitive << c << h << p;
– SystemVerilog }
• System-level modeling extensions to Verilog / IEEE
Standard ("1800") in 2005 void comblogic()
{
f.write((~c.read()) & (h.read() | p.read()));
}
};
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 4 types of VHDL
• Verilog and VHDL are very much similar.
• Verilog is generally used in European countries while the VHDL is
commonly practiced in USA.
• You can learn from the previous slide that both languages were initially
introduced in 1980……….
• However……………………………………….
• SystemC and SystemVerilog are HDL but different from Verilog and
VHDL …. The question is what is the difference ?????
• Remember that it is not the difference of syntax only as we know that
Verilog and VHDL have also different syntax but still we say that they
are very much similar.
• The purpose of SystemC and SystemVerilog is to combine the
designing of hardware and software in a single language. It means
people should not use two different languages for designing software
andVerilog
hardware.
for Digital Design
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 HDLs for Design and Synthesis

What is design ??????

What is synthesis ????

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 HDLs for Design and Synthesis
HDL
• HDLs became increasingly used for
designing ICs using top-down design
process
– Design: Converting a higher-level FSM outputs
description into a lower-level one HDL
Clk_s
– Describe circuit in HDL, simulate Rst_s

• Physical design tools automatically HDL behavior (Engineer) b_s

convert to low-level IC design
x_s
– Describe behavior in HDL, simulate
10 20 30 40 50 60 70 80 90100110
• e.g., Describe addition as A = B + C, Synthesis (tools)
rather than as circuit of hundreds of logic Clk_s
gates Rst_s
– Compact description, designers get HDL circuit
b_s
function right first
• Design circuit x_s

– Manually, or Physical design (tools) 10 20 30 40 50 60 70 80 90100110

– Using synthesis tools, which
automatically convert HDL behavior to
HDL circuit
– Simulate circuit, should match
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 HDLs for Synthesis
• Use of HDLs for synthesis is growing
– Circuits are more complex
– Synthesis tools are maturing
• But HDLs originally defined for Clk_s

simulation Simulate Rst_s

HDL behavior (Engineer)
– General language b_s

x_s
– Many constructs not suitable for
10 20 30 40 50 60 70 80 90100110
synthesis Synthesis Tools
• e.g., delays
– Behavior description may simulate, but HDL circuit
not synthesize, or may synthesize to
incorrect or inefficient circuit
• Not necessarily synthesis tool's fault!

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 HDLs for Synthesis
• Consider the English language
– General and complex; many uses
– But use for cooking recipes is greatly restricted
• Chef understands: stir, blend, eggs, bowl, ...
• Chef may not understand: bludgeon, harmonic,
forthright, castigate, ..., even if English grammar Clk_s
is correct Simulate Rst_s
– If the meal turns out bad, don't blame the chef!
HDL behavior b_s
• Likewise, consider HDL language x_s
– General and complex; many uses
10 20 30 40 50 60 70 80 90100110
– But use for synthesizing circuits is greatly Synthesis
restricted
• Synthesis tool understands: sensitivity lists, if
statements, ... HDL circuit
• Synthesis tool may not understand: wait
statements, while loops, ..., even if the HDL
simulates correctly
– If the circuit is bad, don't blame the synthesis tool!
– This book emphasizes use of VHDL for design
and synthesis

Verilog for Digital Design

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 Verilog for Digital Design
• This book introduces use of Verilog for design and synthesis
– In contrast to books that introduce the general language first, and then (maybe)
describe synthesis subset
– No need to learn entire French language if your goal is just to write recipes in
French
• Shows use of Verilog for increasingly complex digital systems
– Combinational logic design
– Sequential logic design
– Datapath components
– Register transfer level (RTL) design
– Emphasizes a very disciplined use of the language for specific purposes
• Book can be used as supplement to digital design textbook
– Specifically follows structure and examples of "Digital Design" by Frank Vahid,
John Wiley and Sons, 2007
• But can be used with other books too
– Can also be used as standalone introduction to Verilog

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