M25P64

64 Mbit, Low Voltage, Serial Flash Memory

With 50MHz SPI Bus Interface
PRELIMINARY DATA

FEATURES SUMMARY
■ 64Mbit of Flash Memory Figure 1. Packages
■ Page Program (up to 256 Bytes) in 1.4ms
(typical)
■ Sector Erase (512Kbit)
■ Bulk Erase (64Mbit)
■ 2.7 to 3.6V Single Supply Voltage
■ SPI Bus Compatible Serial Interface
■ 50MHz Clock Rate (maximum)
■ Electronic Signatures
– JEDEC Standard Two-Byte Signature VDFPN8 (ME)
(2017h) 8x6mm (MLP8)
– RES Instruction, One-Byte, Signature
(16h), for backward compatibility
■ More than 100000 Erase/Program Cycles per
Sector
■ More than 20-Year Data Retention

SO16 (MF)
300 mils width

February 2005 1/38

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M25P64

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. VDFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Hold Condition Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/38
 M25P64

Figure 10.Write Disable (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Read Identification (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . 16
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 17
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13.Write Status Register (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 20
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15.Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence 21
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16.Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17.Sector Erase (SE) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18.Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19.Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence . . . . . 25

POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 20.Power-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 21.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 13. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 22.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23.Write Protect Setup and Hold Timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . 32
Figure 24.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3/38
M25P64

Figure 25.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . . 34
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27.SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35
Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4/38
 M25P64

SUMMARY DESCRIPTION Figure 3. VDFPN Connections

The M25P64 is a 64Mbit (8M x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
M25P64
The memory is organized as 128 sectors, each
containing 256 pages. Each page is 256 bytes S 1 8 VCC
wide. Thus, the whole memory can be viewed as
Q 2 7 HOLD
consisting of 32768 pages, or 8388608 bytes.
W 3 6 C
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the VSS 4 5 D
Sector Erase instruction. AI08595

Figure 2. Logic Diagram

VCC

Note: 1. There is an exposed die paddle on the underside of the

MLP8 package. This is pulled, internally, to VSS, and
D Q must not be allowed to be connected to any other voltage
or signal line on the PCB.
C 2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
S M25P64
Figure 4. SO Connections
W
M25P64
HOLD
HOLD 1 16 C
VCC 2 15 D
DU 3 14 DU
VSS
AI07485 DU 4 13 DU
DU 5 12 DU
DU 6 11 DU
S 7 10 VSS
Table 1. Signal Names Q 8 9 W
AI07486b
C Serial Clock

D Serial Data Input

Note: 1. DU = Don’t Use
Q Serial Data Output 2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
S Chip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

5/38
M25P64

SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is progress, the device will be in the Standby Power
used to transfer data serially out of the device. mode. Driving Chip Select (S) Low selects the de-
Data is shifted out on the falling edge of Serial vice, placing it in the Active Power mode.
Clock (C). After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in- Hold (HOLD). The Hold (HOLD) signal is used to
structions, addresses, and the data to be pro- pause any serial communications with the device
grammed. Values are latched on the rising edge of without deselecting the device.
Serial Clock (C).
During the Hold condition, the Serial Data Output
Serial Clock (C). This input signal provides the (Q) is high impedance, and Serial Data Input (D)
timing of the serial interface. Instructions, address- and Serial Clock (C) are Don’t Care.
es, or data present at Serial Data Input (D) are To start the Hold condition, the device must be se-
latched on the rising edge of Serial Clock (C). Data lected, with Chip Select (S) driven Low.
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C). Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
Chip Select (S). When this input signal is High, ory that is protected against program or erase
the device is deselected and Serial Data Output instructions (as specified by the values in the BP2,
(Q) is at high impedance. Unless an internal Pro- BP1 and BP0 bits of the Status Register).
gram, Erase or Write Status Register cycle is in

6/38
 M25P64

SPI MODES
These devices can be driven by a microcontroller is available from the falling edge of Serial Clock
with its SPI peripheral running in either of the two (C).
following modes: The difference between the two modes, as shown
– CPOL=0, CPHA=0 in Figure 6., is the clock polarity when the bus
– CPOL=1, CPHA=1 master is in Stand-by mode and not transferring
data:
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data – C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus Master and Memory Devices on the SPI Bus

SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

C Q D C Q D C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory SPI Memory SPI Memory
Device Device Device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI03746D

Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 6. SPI Modes Supported

CPOL CPHA

0 0 C

1 1 C

D MSB

Q MSB

AI01438B

7/38
M25P64

OPERATING FEATURES
Page Programming Active Power and Standby Power Modes
To program one data byte, two instructions are re- When Chip Select (S) is Low, the device is select-
quired: Write Enable (WREN), which is one byte, ed, and in the Active Power mode.
and a Page Program (PP) sequence, which con- When Chip Select (S) is High, the device is dese-
sists of four bytes plus data. This is followed by the lected, but could remain in the Active Power mode
internal Program cycle (of duration tPP). until all internal cycles have completed (Program,
To spread this overhead, the Page Program (PP) Erase, Write Status Register). The device then
instruction allows up to 256 bytes to be pro- goes in to the Standby Power mode. The device
grammed at a time (changing bits from 1 to 0), pro- consumption drops to ICC1.
vided that they lie in consecutive addresses on the
same page of memory. Status Register

Sector Erase and Bulk Erase The Status Register contains a number of status
and control bits that can be read or set (as appro-
The Page Program (PP) instruction allows bits to priate) by specific instructions.
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all WIP bit. The Write In Progress (WIP) bit indicates
1s (FFh). This can be achieved either a sector at a whether the memory is busy with a Write Status
time, using the Sector Erase (SE) instruction, or Register, Program or Erase cycle.
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal WEL bit. The Write Enable Latch (WEL) bit indi-
Erase cycle (of duration tSE or tBE). cates the status of the internal Write Enable Latch.
The Erase instruction must be preceded by a Write
Enable (WREN) instruction. BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the
size of the area to be software protected against
Polling During a Write, Program or Erase Cycle Program and Erase instructions.
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or SRWD bit. The Status Register Write Disable
BE) can be achieved by not waiting for the worst (SRWD) bit is operated in conjunction with the
case delay (tW, tPP, tSE, or tBE). The Write In Write Protect (W) signal. The Status Register
Progress (WIP) bit is provided in the Status Regis- Write Disable (SRWD) bit and Write Protect (W)
ter so that the application program can monitor its signal allow the device to be put in the Hardware
value, polling it to establish when the previous Protected mode. In this mode, the non-volatile bits
Write cycle, Program cycle or Erase cycle is com- of the Status Register (SRWD, BP2, BP1, BP0)
plete. become read-only bits.

8/38
 M25P64

Protection Modes – Power-up

The environments where non-volatile memory de- – Write Disable (WRDI) instruction
vices are used can be very noisy. No SPI device completion
can operate correctly in the presence of excessive – Write Status Register (WRSR) instruction
noise. To help combat this, the M25P64 features completion
the following data protection mechanisms: – Page Program (PP) instruction completion
■ Power On Reset and an internal timer (tPUW) – Sector Erase (SE) instruction completion
can provide protection against inadvertant
– Bulk Erase (BE) instruction completion
changes while the power supply is outside the
operating specification. ■ The Block Protect (BP2, BP1, BP0) bits allow
part of the memory to be configured as read-
■ Program, Erase and Write Status Register
only. This is the Software Protected Mode
instructions are checked that they consist of a
(SPM).
number of clock pulses that is a multiple of
eight, before they are accepted for execution. ■ The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status
■ All instructions that modify data must be
Register Write Disable (SRWD) bit to be
preceded by a Write Enable (WREN)
protected. This is the Hardware Protected
instruction to set the Write Enable Latch
Mode (HPM).
(WEL) bit. This bit is returned to its reset state
by the following events:

Table 2. Protected Area Sizes

Status Register
Memory Content
Content
BP2 BP1 BP0
Protected Area Unprotected Area
Bit Bit Bit

0 0 0 none All sectors1 (128 sectors: 0 to 127)

0 0 1 Upper 64th (2 sectors: 126 and 127) Lower 63/64ths (126 sectors: 0 to 125)
0 1 0 Upper 32nd (4 sectors: 124 to 127) Lower 31/32nds (124 sectors: 0 to 123)
0 1 1 Upper sixteenth (8 sectors: 120 to 127) Lower 15/16ths (120 sectors: 0 to 119)
1 0 0 Upper eighth (16 sectors: 112 to 127) Lower seven-eighths (112 sectors: 0 to 111)
1 0 1 Upper quarter (32 sectors: 96 to 127) Lower three-quarters (96 sectors: 0 to 95)
1 1 0 Upper half (64 sectors: 64 to 127) Lower half (64 sectors: 0 to 63)
1 1 1 All sectors (128 sectors: 0 to 127) none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

9/38
M25P64

Hold Condition rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
The Hold (HOLD) signal is used to pause any se- Clock (C) next goes Low. (This is shown in Figure
rial communications with the device without reset- 7.).
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status During the Hold condition, the Serial Data Output
Register, Program or Erase cycle that is currently (Q) is high impedance, and Serial Data Input (D)
in progress. and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be Normally, the device is kept selected, with Chip
selected, with Chip Select (S) Low. Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
The Hold condition starts on the falling edge of the the internal logic remains unchanged from the mo-
Hold (HOLD) signal, provided that this coincides ment of entering the Hold condition.
with Serial Clock (C) being Low (as shown in Fig-
ure 7.). If Chip Select (S) goes High while the device is in
the Hold condition, this has the effect of resetting
The Hold condition ends on the rising edge of the the internal logic of the device. To restart commu-
Hold (HOLD) signal, provided that this coincides nication with the device, it is necessary to drive
with Serial Clock (C) being Low. Hold (HOLD) High, and then to drive Chip Select
If the falling edge does not coincide with Serial (S) Low. This prevents the device from going back
Clock (C) being Low, the Hold condition starts af- to the Hold condition.
ter Serial Clock (C) next goes Low. Similarly, if the

Figure 7. Hold Condition Activation

HOLD

Hold Hold
Condition Condition
(standard use) (non-standard use)
AI02029D

10/38
 M25P64

MEMORY ORGANIZATION
The memory is organized as: Each page can be individually programmed (bits
■ 8388608 bytes (8 bits each) are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
■ 128 sectors (512Kbits, 65536 bytes each) not Page Erasable.
■ 32768 pages (256 bytes each).

Figure 8. Block Diagram

HOLD
High Voltage
W Control Logic Generator
S

D
I/O Shift Register
Q

Address Register 256 Byte Status

and Counter Data Buffer Register

7FFFFFh

Size of the
Y Decoder

read-only
memory area

00000h 000FFh
256 Bytes (Page Size)

X Decoder

AI08520

11/38
M25P64

Table 3. Memory Organization Sector Address Range

Sector Address Range
92 5C0000h 5CFFFFh
127 7F0000h 7FFFFFh
91 5B0000h 5BFFFFh
126 7E0000h 7EFFFFh
90 5A0000h 5AFFFFh
125 7D0000h 7DFFFFh
89 590000h 59FFFFh
124 7C0000h 7CFFFFh
88 580000h 58FFFFh
123 7B0000h 7BFFFFh
87 570000h 57FFFFh
122 7A0000h 7AFFFFh
86 560000h 56FFFFh
121 790000h 79FFFFh
85 550000h 55FFFFh
120 780000h 78FFFFh
84 540000h 54FFFFh
119 770000h 77FFFFh
83 530000h 53FFFFh
118 760000h 76FFFFh
82 520000h 52FFFFh
117 750000h 75FFFFh
81 510000h 51FFFFh
116 740000h 74FFFFh
80 500000h 50FFFFh
115 730000h 73FFFFh
79 4F0000h 4FFFFFh
114 720000h 72FFFFh
78 4E0000h 4EFFFFh
113 710000h 71FFFFh
77 4D0000h 4DFFFFh
112 700000h 70FFFFh
76 4C0000h 4CFFFFh
111 6F0000h 6FFFFFh
75 4B0000h 4BFFFFh
110 6E0000h 6EFFFFh
74 4A0000h 4AFFFFh
109 6D0000h 6DFFFFh
73 490000h 49FFFFh
108 6C0000h 6CFFFFh
72 480000h 48FFFFh
107 6B0000h 6BFFFFh
71 470000h 47FFFFh
106 6A0000h 6AFFFFh
70 460000h 46FFFFh
105 690000h 69FFFFh
69 450000h 45FFFFh
104 680000h 68FFFFh
68 440000h 44FFFFh
103 670000h 67FFFFh
67 430000h 43FFFFh
102 660000h 66FFFFh
66 420000h 42FFFFh
101 650000h 65FFFFh
65 410000h 41FFFFh
100 640000h 64FFFFh
64 400000h 40FFFFh
99 630000h 63FFFFh
63 3F0000h 3FFFFFh
98 620000h 62FFFFh
62 3E0000h 3EFFFFh
97 610000h 61FFFFh
61 3D0000h 3DFFFFh
96 600000h 60FFFFh
60 3C0000h 3CFFFFh
95 5F0000h 5FFFFFh
59 3B0000h 3BFFFFh
94 5E0000h 5EFFFFh
58 3A0000h 3AFFFFh
93 5D0000h 5DFFFFh
57 390000h 39FFFFh

12/38
 M25P64

Sector Address Range Sector Address Range

56 380000h 38FFFFh 20 140000h 14FFFFh
55 370000h 37FFFFh 19 130000h 13FFFFh
54 360000h 36FFFFh 18 120000h 12FFFFh
53 350000h 35FFFFh 17 110000h 11FFFFh
52 340000h 34FFFFh 16 100000h 10FFFFh
51 330000h 33FFFFh 15 0F0000h 0FFFFFh
50 320000h 32FFFFh 14 0E0000h 0EFFFFh
49 310000h 31FFFFh 13 0D0000h 0DFFFFh
48 300000h 30FFFFh 12 0C0000h 0CFFFFh
47 2F0000h 2FFFFFh 11 0B0000h 0BFFFFh
46 2E0000h 2EFFFFh 10 0A0000h 0AFFFFh
45 2D0000h 2DFFFFh 9 090000h 09FFFFh
44 2C0000h 2CFFFFh 8 080000h 08FFFFh
43 2B0000h 2BFFFFh 7 070000h 07FFFFh
42 2A0000h 2AFFFFh 6 060000h 06FFFFh
41 290000h 29FFFFh 5 050000h 05FFFFh
40 280000h 28FFFFh 4 040000h 04FFFFh
39 270000h 27FFFFh 3 030000h 03FFFFh
38 260000h 26FFFFh 2 020000h 02FFFFh
37 250000h 25FFFFh 1 010000h 01FFFFh
36 240000h 24FFFFh 0 000000h 00FFFFh
35 230000h 23FFFFh
34 220000h 22FFFFh
33 210000h 21FFFFh
32 200000h 20FFFFh
31 1F0000h 1FFFFFh
30 1E0000h 1EFFFFh
29 1D0000h 1DFFFFh
28 1C0000h 1CFFFFh
27 1B0000h 1BFFFFh
26 1A0000h 1AFFFFh
25 190000h 19FFFFh
24 180000h 18FFFFh
23 170000h 17FFFFh
22 160000h 16FFFFh
21 150000h 15FFFFh

13/38
M25P64

INSTRUCTIONS
All instructions, addresses and data are shifted in lowed by a data-out sequence. Chip Select (S) can
and out of the device, most significant bit first. be driven High after any bit of the data-out se-
Serial Data Input (D) is sampled on the first rising quence is being shifted out.
edge of Serial Clock (C) after Chip Select (S) is In the case of a Page Program (PP), Sector Erase
driven Low. Then, the one-byte instruction code (SE), Bulk Erase (BE), Write Status Register
must be shifted in to the device, most significant bit (WRSR), Write Enable (WREN) or Write Disable
first, on Serial Data Input (D), each bit being (WRDI), Chip Select (S) must be driven High ex-
latched on the rising edges of Serial Clock (C). actly at a byte boundary, otherwise the instruction
The instruction set is listed in Table 4.. is rejected, and is not executed. That is, Chip Se-
lect (S) must driven High when the number of
Every instruction sequence starts with a one-byte clock pulses after Chip Select (S) being driven
instruction code. Depending on the instruction, Low is an exact multiple of eight.
this might be followed by address bytes, or by data
bytes, or by both or none. All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
In the case of a Read Data Bytes (READ), Read Erase cycle are ignored, and the internal Write
Data Bytes at Higher Speed (Fast_Read), Read
Status Register cycle, Program cycle or Erase cy-
Status Register (RDSR), Read Identification cle continues unaffected.
(RDID) or Read Electronic Signature (RES) in-
struction, the shifted-in instruction sequence is fol-

Table 4. Instruction Set

Address Dummy Data
Instruction Description One-byte Instruction Code
Bytes Bytes Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
RES Read Electronic Signature 1010 1011 ABh 0 3 1 to ∞

14/38
 M25P64

Write Enable (WREN) (SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction (Figure 9.)
sets the Write Enable Latch (WEL) bit. The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
The Write Enable Latch (WEL) bit must be set pri- struction code, and then driving Chip Select (S)
or to every Page Program (PP), Sector Erase High.

Figure 9. Write Enable (WREN) Instruction Sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI02281E

Write Disable (WRDI) – Power-up

The Write Disable (WRDI) instruction (Figure 10.) – Write Disable (WRDI) instruction completion
resets the Write Enable Latch (WEL) bit. – Write Status Register (WRSR) instruction
The Write Disable (WRDI) instruction is entered by completion
driving Chip Select (S) Low, sending the instruc- – Page Program (PP) instruction completion
tion code, and then driving Chip Select (S) High. – Sector Erase (SE) instruction completion
The Write Enable Latch (WEL) bit is reset under – Bulk Erase (BE) instruction completion
the following conditions:

Figure 10. Write Disable (WRDI) Instruction Sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI03750D

15/38
M25P64

Read Identification (RDID) The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the in-
The Read Identification (RDID) instruction allows struction is shifted in. This is followed by the 24-bit
the 8-bit manufacturer identification to be read, fol- device identification, stored in the memory, being
lowed by two bytes of device identification. The shifted out on Serial Data Output (Q), each bit be-
manufacturer identification is assigned by JEDEC, ing shifted out during the falling edge of Serial
and has the value 20h for STMicroelectronics. The Clock (C).
device identification is assigned by the device
manufacturer, and indicates the memory type in The instruction sequence is shown in Figure 11..
the first byte (20h), and the memory capacity of the The Read Identification (RDID) instruction is termi-
device in the second byte (17h). nated by driving Chip Select (S) High at any time
Any Read Identification (RDID) instruction while during data output.
an Erase or Program cycle is in progress, is not When Chip Select (S) is driven High, the device is
decoded, and has no effect on the cycle that is in put in the Standby Power mode. Once in the
progress. Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.

Table 5. Read Identification (RDID) Data-Out Sequence

Device Identification
Manufacturer Identification
Memory Type Memory Capacity

20h 20h 17h

Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31

Instruction

Manufacturer Identification Device Identification

High Impedance
Q 15 14 13 3 2 1 0

MSB MSB
AI06809b

16/38
 M25P64

Read Status Register (RDSR) WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
The Read Status Register (RDSR) instruction al- When set to 1 the internal Write Enable Latch is
lows the Status Register to be read. The Status set, when set to 0 the internal Write Enable Latch
Register may be read at any time, even while a is reset and no Write Status Register, Program or
Program, Erase or Write Status Register cycle is in Erase instruction is accepted.
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress BP2, BP1, BP0 bits. The Block Protect (BP2,
(WIP) bit before sending a new instruction to the BP1, BP0) bits are non-volatile. They define the
device. It is also possible to read the Status Reg- size of the area to be software protected against
ister continuously, as shown in Figure 12.. Program and Erase instructions. These bits are
written with the Write Status Register (WRSR) in-
Table 6. Status Register Format struction. When one or more of the Block Protect
(BP2, BP1, BP0) bits is set to 1, the relevant mem-
b7 b0
ory area (as defined in Table 2.) becomes protect-
SRWD 0 0 BP2 BP1 BP0 WEL WIP ed against Page Program (PP) and Sector Erase
(SE) instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hard-
Status Register ware Protected mode has not been set. The Bulk
Write Protect Erase (BE) instruction is executed if, and only if, all
Block Protect (BP2, BP1, BP0) bits are 0.
Block Protect Bits
Write Enable Latch Bit
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write In Progress Bit Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
The status and control bits of the Status Register signal allow the device to be put in the Hardware
are as follows: Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
WIP bit. The Write In Progress (WIP) bit indicates
(W) is driven Low). In this mode, the non-volatile
whether the memory is busy with a Write Status
bits of the Status Register (SRWD, BP2, BP1,
Register, Program or Erase cycle. When set to 1,
BP0) become read-only bits and the Write Status
such a cycle is in progress, when reset to 0 no
Register (WRSR) instruction is no longer accepted
such cycle is in progress.
for execution.

Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Status Register Out Status Register Out

High Impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

AI02031E

17/38
M25P64

Write Status Register (WRSR) (whose duration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status
The Write Status Register (WRSR) instruction al- Register may still be read to check the value of the
lows new values to be written to the Status Regis- Write In Progress (WIP) bit. The Write In Progress
ter. Before it can be accepted, a Write Enable (WIP) bit is 1 during the self-timed Write Status
(WREN) instruction must previously have been ex- Register cycle, and is 0 when it is completed.
ecuted. After the Write Enable (WREN) instruction When the cycle is completed, the Write Enable
has been decoded and executed, the device sets Latch (WEL) is reset.
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction al-
The Write Status Register (WRSR) instruction is lows the user to change the values of the Block
entered by driving Chip Select (S) Low, followed Protect (BP2, BP1, BP0) bits, to define the size of
by the instruction code and the data byte on Serial the area that is to be treated as read-only, as de-
Data Input (D). fined in Table 2.. The Write Status Register
The instruction sequence is shown in Figure 13.. (WRSR) instruction also allows the user to set or
The Write Status Register (WRSR) instruction has reset the Status Register Write Disable (SRWD)
no effect on b6, b5, b1 and b0 of the Status Reg- bit in accordance with the Write Protect (W) signal.
ister. b6 and b5 are always read as 0. The Status Register Write Disable (SRWD) bit and
Chip Select (S) must be driven High after the Write Protect (W) signal allow the device to be put
eighth bit of the data byte has been latched in. If in the Hardware Protected Mode (HPM). The Write
not, the Write Status Register (WRSR) instruction Status Register (WRSR) instruction is not execut-
is not executed. As soon as Chip Select (S) is driv- ed once the Hardware Protected Mode (HPM) is
en High, the self-timed Write Status Register cycle entered.

Table 7. Protection Modes

Memory Content
W SRWD Write Protection of the
Mode
Signal Bit Status Register
Protected Area1 Unprotected Area1
1 0 Status Register is Writable
(if the WREN instruction
0 0 Software Protected against Page Ready to accept Page
has set the WEL bit)
Protected Program, Sector Erase Program and Sector Erase
The values in the SRWD,
(SPM) and Bulk Erase instructions
1 1 BP2, BP1 and BP0 bits
can be changed
Status Register is
Hardware Hardware write protected Protected against Page Ready to accept Page
0 1 Protected The values in the SRWD, Program, Sector Erase Program and Sector Erase
(HPM) BP2, BP1 and BP0 bits and Bulk Erase instructions
cannot be changed
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2..

The protection features of the device are summa- has previously been set by a Write Enable
rized in Table 7. (WREN) instruction.
When the Status Register Write Disable (SRWD) – If Write Protect (W) is driven Low, it is not
bit of the Status Register is 0 (its initial delivery possible to write to the Status Register even if
state), it is possible to write to the Status Register the Write Enable Latch (WEL) bit has
provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
previously been set by a Write Enable (WREN) in- (WREN) instruction. (Attempts to write to the
struction, regardless of the whether Write Protect Status Register are rejected, and are not
(W) is driven High or Low. accepted for execution). As a consequence,
When the Status Register Write Disable (SRWD) all the data bytes in the memory area that are
bit of the Status Register is set to 1, two cases software protected (SPM) by the Block Protect
need to be considered, depending on the state of (BP2, BP1, BP0) bits of the Status Register,
Write Protect (W): are also hardware protected against data
modification.
– If Write Protect (W) is driven High, it is
possible to write to the Status Register Regardless of the order of the two events, the
provided that the Write Enable Latch (WEL) bit Hardware Protected Mode (HPM) can be entered:

18/38
 M25P64

– by setting the Status Register Write Disable The only way to exit the Hardware Protected Mode
(SRWD) bit after driving Write Protect (W) Low (HPM) once entered is to pull Write Protect (W)
– or by driving Write Protect (W) Low after High.
setting the Status Register Write Disable If Write Protect (W) is permanently tied High, the
(SRWD) bit. Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0)
bits of the Status Register, can be used.

Figure 13. Write Status Register (WRSR) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Status
Register In

D 7 6 5 4 3 2 1 0

High Impedance MSB

Q
AI02282D

19/38
M25P64

Read Data Bytes (READ) next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
The device is first selected by driving Chip Select with a single Read Data Bytes (READ) instruction.
(S) Low. The instruction code for the Read Data When the highest address is reached, the address
Bytes (READ) instruction is followed by a 3-byte counter rolls over to 000000h, allowing the read
address (A23-A0), each bit being latched-in during sequence to be continued indefinitely.
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se- The Read Data Bytes (READ) instruction is termi-
rial Data Output (Q), each bit being shifted out, at nated by driving Chip Select (S) High. Chip Select
a maximum frequency fR, during the falling edge of (S) can be driven High at any time during data out-
Serial Clock (C). put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
The instruction sequence is shown in Figure 14.. progress, is rejected without having any effects on
The first byte addressed can be at any location. the cycle that is in progress.
The address is automatically incremented to the

Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-Bit Address

D 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB

AI03748D

Note: 1. Address bit A23 is Don’t Care.

20/38
 M25P64

Read Data Bytes at Higher Speed next higher address after each byte of data is shift-
(FAST_READ) ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
The device is first selected by driving Chip Select (FAST_READ) instruction. When the highest ad-
(S) Low. The instruction code for the Read Data dress is reached, the address counter rolls over to
Bytes at Higher Speed (FAST_READ) instruction 000000h, allowing the read sequence to be contin-
is followed by a 3-byte address (A23-A0) and a ued indefinitely.
dummy byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory The Read Data Bytes at Higher Speed
contents, at that address, is shifted out on Serial (FAST_READ) instruction is terminated by driving
Data Output (Q), each bit being shifted out, at a Chip Select (S) High. Chip Select (S) can be driv-
maximum frequency fC, during the falling edge of en High at any time during data output. Any Read
Serial Clock (C). Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
The instruction sequence is shown in Figure 15.. is in progress, is rejected without having any ef-
The first byte addressed can be at any location. fects on the cycle that is in progress.
The address is automatically incremented to the

Figure 15. Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31

Instruction 24 BIT ADDRESS

D 23 22 21 3 2 1 0

High Impedance
Q

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Dummy Byte

D 7 6 5 4 3 2 1 0

DATA OUT 1 DATA OUT 2

Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB MSB

AI04006

Note: Address bit A23 is Don’t Care.

21/38
M25P64

Page Program (PP) rectly within the same page. If less than 256 Data
bytes are sent to device, they are correctly pro-
The Page Program (PP) instruction allows bytes to grammed at the requested addresses without hav-
be programmed in the memory (changing bits from ing any effects on the other bytes of the same
1 to 0). Before it can be accepted, a Write Enable page.
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction Chip Select (S) must be driven High after the
has been decoded, the device sets the Write En- eighth bit of the last data byte has been latched in,
able Latch (WEL). otherwise the Page Program (PP) instruction is not
executed.
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in- As soon as Chip Select (S) is driven High, the self-
struction code, three address bytes and at least timed Page Program cycle (whose duration is tPP)
one data byte on Serial Data Input (D). If the 8 is initiated. While the Page Program cycle is in
least significant address bits (A7-A0) are not all progress, the Status Register may be read to
zero, all transmitted data that goes beyond the end check the value of the Write In Progress (WIP) bit.
of the current page are programmed from the start The Write In Progress (WIP) bit is 1 during the self-
address of the same page (from the address timed Page Program cycle, and is 0 when it is
whose 8 least significant bits (A7-A0) are all zero). completed. At some unspecified time before the
Chip Select (S) must be driven Low for the entire cycle is completed, the Write Enable Latch (WEL)
duration of the sequence. bit is reset.
The instruction sequence is shown in Figure 16.. A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP2, BP1,
If more than 256 bytes are sent to the device, pre- BP0) bits (see Table 2. and Table 3.) is not execut-
viously latched data are discarded and the last 256 ed.
data bytes are guaranteed to be programmed cor-

Figure 16. Page Program (PP) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-Bit Address Data Byte 1

D 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB

S
2072
2073
2074
2075
2076
2077
2078
2079

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Data Byte 2 Data Byte 3 Data Byte 256

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB MSB

AI04082B

22/38
 M25P64

Sector Erase (SE) Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
The Sector Erase (SE) instruction sets to 1 (FFh) in, otherwise the Sector Erase (SE) instruction is
all bits inside the chosen sector. Before it can be not executed. As soon as Chip Select (S) is driven
accepted, a Write Enable (WREN) instruction High, the self-timed Sector Erase cycle (whose du-
must previously have been executed. After the ration is tSE) is initiated. While the Sector Erase cy-
Write Enable (WREN) instruction has been decod- cle is in progress, the Status Register may be read
ed, the device sets the Write Enable Latch (WEL). to check the value of the Write In Progress (WIP)
The Sector Erase (SE) instruction is entered by bit. The Write In Progress (WIP) bit is 1 during the
driving Chip Select (S) Low, followed by the in- self-timed Sector Erase cycle, and is 0 when it is
struction code, and three address bytes on Serial completed. At some unspecified time before the
Data Input (D). Any address inside the Sector (see cycle is completed, the Write Enable Latch (WEL)
Table 3.) is a valid address for the Sector Erase bit is reset.
(SE) instruction. Chip Select (S) must be driven A Sector Erase (SE) instruction applied to a page
Low for the entire duration of the sequence. which is protected by the Block Protect (BP2, BP1,
The instruction sequence is shown in Figure 17.. BP0) bits (see Table 2. and Table 3.) is not execut-
ed.

Figure 17. Sector Erase (SE) Instruction Sequence

0 1 2 3 4 5 6 7 8 9 29 30 31

Instruction 24 Bit Address

D 23 22 2 1 0
MSB

AI03751D

Note: Address bit A23 is Don’t Care.

23/38
M25P64

Bulk Erase (BE) in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
The Bulk Erase (BE) instruction sets all bits to 1 the self-timed Bulk Erase cycle (whose duration is
(FFh). Before it can be accepted, a Write Enable tBE) is initiated. While the Bulk Erase cycle is in
(WREN) instruction must previously have been ex- progress, the Status Register may be read to
ecuted. After the Write Enable (WREN) instruction check the value of the Write In Progress (WIP) bit.
has been decoded, the device sets the Write En- The Write In Progress (WIP) bit is 1 during the self-
able Latch (WEL). timed Bulk Erase cycle, and is 0 when it is com-
The Bulk Erase (BE) instruction is entered by driv- pleted. At some unspecified time before the cycle
ing Chip Select (S) Low, followed by the instruction is completed, the Write Enable Latch (WEL) bit is
code on Serial Data Input (D). Chip Select (S) reset.
must be driven Low for the entire duration of the The Bulk Erase (BE) instruction is executed only if
sequence. all Block Protect (BP2, BP1, BP0) bits are 0. The
The instruction sequence is shown in Figure 18.. Bulk Erase (BE) instruction is ignored if one, or
Chip Select (S) must be driven High after the more, sectors are protected.
eighth bit of the instruction code has been latched

Figure 18. Bulk Erase (BE) Instruction Sequence

0 1 2 3 4 5 6 7

Instruction

AI03752D

24/38
 M25P64

Read Electronic Signature (RES) The instruction sequence is shown in Figure 19.
The instruction is used to read, on Serial Data Out- The Read Electronic Signature (RES) instruction
put (Q), the old-style 8-bit Electronic Signature, is terminated by driving Chip Select (S) High after
whose value for the M25P64 is 16h. the Electronic Signature has been read at least
once. Sending additional clock cycles on Serial
Please note that this is not the same as, or even a Clock (C), while Chip Select (S) is driven Low,
subset of, the JEDEC 16-bit Electronic Signature cause the Electronic Signature to be output re-
that is read by the Read Identifier (RDID) instruc- peatedly.
tion. The old-style Electronic Signature is support-
ed for reasons of backward compatibility, only, and When Chip Select (S) is driven High, the device is
should not be used for new designs. New designs put in the Standby Power mode. Once in the
should, instead, make use of the JEDEC 16-bit Standby Power mode, the device waits to be se-
Electronic Signature, and the Read Identifier lected, so that it can receive, decode and execute
(RDID) instruction. instructions.
The device is first selected by driving Chip Select Driving Chip Select (S) High after the 8-bit instruc-
(S) Low. The instruction code is followed by 3 tion byte has been received by the device, but be-
dummy bytes, each bit being latched-in on Serial fore the whole of the 8-bit Electronic Signature has
Data Input (D) during the rising edge of Serial been transmitted for the first time, still ensures that
Clock (C). Then, the old-style 8-bit Electronic Sig- the device is put into Standby Power mode. Once
nature, stored in the memory, is shifted out on Se- in the Standby Power mode, the device waits to be
rial Data Output (Q), each bit being shifted out selected, so that it can receive, decode and exe-
during the falling edge of Serial Clock (C). cute instructions.

Figure 19. Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38

Instruction 3 Dummy Bytes

D 23 22 21 3 2 1 0

MSB
Electronic Signature Out
High Impedance
Q 7 6 5 4 3 2 1 0
MSB
AI04047C

Note: The value of the 8-bit Electronic Signature, for the M25P64, is 16h.

25/38
M25P64

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must – tPUW after VCC passed the VWI threshold
not be selected (that is Chip Select (S) must follow – tVSL after VCC passed the VCC(min) level
the voltage applied on VCC) until VCC reaches the
correct value: These values are specified in Table 8..
– VCC(min) at Power-up, and then for a further If the delay, tVSL, has elapsed, after VCC has risen
above VCC(min), the device can be selected for
delay of tVSL
READ instructions even if the tPUW delay is not yet
– VSS at Power-down fully elapsed.
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down. At Power-up, the device is in the following state:
To avoid data corruption and inadvertent write op- – The device is in the Standby Power mode
erations during Power-up, a Power On Reset – The Write Enable Latch (WEL) bit is reset.
(POR) circuit is included. The logic inside the de- Normal precautions must be taken for supply rail
vice is held reset while VCC is less than the Power decoupling, to stabilize the VCC supply. Each de-
On Reset (POR) threshold voltage, VWI – all oper- vice in a system should have the VCC rail decou-
ations are disabled, and the device does not re- pled by a suitable capacitor close to the package
spond to any instruction. pins. (Generally, this capacitor is of the order of
Moreover, the device ignores all Write Enable 0.1µF).
(WREN), Page Program (PP), Sector Erase (SE), At Power-down, when VCC drops from the operat-
Bulk Erase (BE) and Write Status Register ing voltage, to below the Power On Reset (POR)
(WRSR) instructions until a time delay of tPUW has threshold voltage, VWI, all operations are disabled
elapsed after the moment that VCC rises above the and the device does not respond to any instruc-
VWI threshold. However, the correct operation of tion. (The designer needs to be aware that if a
the device is not guaranteed if, by this time, VCC is Power-down occurs while a Write, Program or
still below VCC(min). No Write Status Register, Erase cycle is in progress, some data corruption
Program or Erase instructions should be sent until can result.)
the later of:

Figure 20. Power-up Timing

VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed

VCC(min)

Reset State tVSL Read Access allowed Device fully

of the accessible
Device
VWI

tPUW

time AI04009C

26/38
 M25P64

Table 8. Power-Up Timing and VWI Threshold

Symbol Parameter Min. Max. Unit

tVSL (1) VCC(min) to S low 30 µs

tPUW(1) Time delay to Write instruction 1 10 ms

VWI(1) Write Inhibit Voltage 1.5 2.5 V

Note: 1. These parameters are characterized only.

INITIAL DELIVERY STATE

The device is delivered with the memory array FFh). The Status Register contains 00h (all Status
erased: all bits are set to 1 (each byte contains Register bits are 0).

27/38
M25P64

MAXIMUM RATING
Stressing the device outside the ratings listed in this specification, is not implied. Exposure to Ab-
Table 9. may cause permanent damage to the de- solute Maximum Rating conditions for extended
vice. These are stress ratings only, and operation periods may affect device reliability. Refer also to
of the device at these, or any other conditions out- the STMicroelectronics SURE Program and other
side those indicated in the Operating sections of relevant quality documents.

Table 9. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note (1) °C

VIO Input and Output Voltage (with respect to Ground) –0.5 4.0 V
VCC Supply Voltage –0.2 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 –2000 2000 V

Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

28/38
 M25P64

DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions summarized in the relevant
surement conditions, and the DC and AC charac- tables. Designers should check that the operating
teristics of the device. The parameters in the DC conditions in their circuit match the measurement
and AC Characteristic tables that follow are de- conditions when relying on the quoted parame-
rived from tests performed under the Measure- ters.

Table 10. Operating Conditions

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TA Ambient Operating Temperature –40 85 °C

Table 11. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CL Load Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

Note: Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC Measurement I/O Waveform

Input Levels Input and Output

Timing Reference Levels
0.8VCC
0.7VCC
0.5VCC
0.3VCC
0.2VCC
AI07455

Table 12. Capacitance

Symbol Parameter Test Condition Min. Max. Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.

29/38
M25P64

Table 13. DC Characteristics

Test Condition
Symbol Parameter Min. Max. Unit
(in addition to those in Table 10.)
ILI Input Leakage Current ±2 µA
ILO Output Leakage Current ±2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA
C = 0.1VCC / 0.9.VCC at 50MHz,
8 mA
Q = open
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20MHz,
4 mA
Q = open
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 20 mA
ICC6 Operating Current (SE) S = VCC 20 mA
ICC7 Operating Current (BE) S = VCC 20 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.2 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = –100µA VCC–0.2 V

30/38
 M25P64

Table 14. AC Characteristics

Test conditions specified in Table 10. and Table 11.
Symbol Alt. Parameter Min. Typ. Max. Unit
Clock Frequency for the following instructions: FAST_READ,
fC fC D.C. 50 MHz
PP, SE, BE, RES, WREN, WRDI, RDID, RDSR, WRSR
fR Clock Frequency for READ instructions D.C. 20 MHz

tCH (1) tCLH Clock High Time 9 ns

tCL (1) tCLL Clock Low Time 9 ns

tCLCH (2) Clock Rise Time3 (peak to peak) 0.1 V/ns

tCHCL (2) Clock Fall Time3 (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 100 ns

tSHQZ (2) tDIS Output Disable Time 8 ns

tCLQV tV Clock Low to Output Valid 8 ns

tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX (2) tLZ HOLD to Output Low-Z 8 ns

tHLQZ (2) tHZ HOLD to Output High-Z 8 ns

tWHSL (4) Write Protect Setup Time 20 ns

tSHWL (4) Write Protect Hold Time 100 ns

tW Write Status Register Cycle Time 5 15 ms

tPP Page Program Cycle Time 1.4 5 ms
tSE Sector Erase Cycle Time 1 3 s
tBE Bulk Erase Cycle Time 68 160 s
Note: 1. tCH + tCL must be greater than or equal to 1/ fC(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

31/38
M25P64

Figure 22. Serial Input Timing

tSHSL

tCHSL tSLCH tCHSH tSHCH

tDVCH tCHCL

tCHDX tCLCH

D MSB IN LSB IN

High Impedance
Q

AI01447C

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1

W
tSHWL
tWHSL

High Impedance
Q

AI07439

32/38
 M25P64

Figure 24. Hold Timing

tHLCH

tCHHL tHHCH

tCHHH

tHLQZ tHHQX

HOLD

AI02032

Figure 25. Output Timing

tCH

tCLQV tCLQV tCL tSHQZ

tCLQX tCLQX

Q LSB OUT

tQLQH
tQHQL

D ADDR.LSB IN

AI01449e

33/38
M25P64

PACKAGE MECHANICAL

Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline

E E2 e

A D2

L L1
ddd
A1
VDFPN-02

Note: Drawing is not to scale.

Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data
millimeters inches
Symbol
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 8.00 0.3150
D2 6.40 0.2520
ddd 0.05 0.0020
E 6.00 0.2362
E2 4.80 0.1890
e 1.27 – – 0.0500 – –
K 0.20 0.0079
L 0.50 0.45 0.60 0.0197 0.0177 0.0236
L1 0.15 0.0059
N 8 8

34/38
 M25P64

Figure 27. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width

D h x 45˚
16 9

E H

1 8
θ

A2 A A1 L

ddd
B e
SO-H

Note: Drawing is not to scale.

Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e 1.27 – – 0.050 – –
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
θ 0° 8° 0° 8°
ddd 0.10 0.004

35/38
M25P64

PART NUMBERING

Table 17. Ordering Information Scheme

Example: M25P64 – V MF 6 T P

Device Type
M25P = Serial Flash Memory for Code Storage

Device Function
64 = 64Mbit (8M x 8)

Operating Voltage
V = VCC = 2.7 to 3.6V

Package
MF = SO16 (300 mil width)
ME = VDFPN8 8x6mm (MLP8)

Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option
blank = Standard Packing
T = Tape and Reel Packing

Plating Technology
blank = Standard SnPb plating
P or G = RoHS compliant

For a list of available options (speed, package, device, please contact your nearest ST Sales Of-
etc.) or for further information on any aspect of this fice.

36/38
 M25P64

REVISION HISTORY

Table 18. Document Revision History

Date Rev. Description of Revision
28-Apr-2003 0.1 Target Specification Document written in brief form
15-May-2003 0.2 Target Specification Document written in full
20-Jun-2003 0.3 8x6 MLP8 and SO16(300 mil) packages added
18-Jul-2003 0.4 tPP, tSE and tBE revised

02-Sep-2003 0.5 Voltage supply range changed

19-Sep-2003 0.6 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added

17-Dec-2003 0.7 Value of tVSL(min) VWI, tPP(typ) and tBE(typ) changed. MLP8 package removed.

Document status promoted from Target Specification to Preliminary Data. 8x6 MLP8 package
15-Nov-2004 1.0
added. Minor wording changes.
Deep Power-Down mode removed from datasheet (Figure 19., Read Electronic Signature
(RES) Instruction Sequence and Data-Out Sequence modified and tRES1 and tRES2
24-Feb-2005 2.0 removed from Table 14., AC Characteristics). SO16 Wide package specifications updated.
End timing line of tSHQZ modified in Figure 25., Output Timing. Figures moved below the
corresponding instructions in the INSTRUCTIONS section.

37/38
M25P64

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners

© 2005 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com

38/38