Introduction to CMOS RF Integrated Circuits Design

V. Voltage Controlled Oscillators

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-1
Outline

Phase Noise and Spurs

Ring VCO
LC VCO
Frequency Tuning (Varactor, SCA)
Phase Noise Estimation
Quadrature Phase Generator

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-2
VCO Phase Noise

Sblock
SNR
fRF
Sdesired fIF
IF 
fLO
RF

L{

LO 

Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou V-3
Phase Noise Requirement

SNR  Sdesired  Snoise

 Sdesired [Sblock  L{}10log( f ch )]
L{} Sdesired  Sblock  SNRmin 10log( f ch )
Ex: GSM
Sdesired 102dB; Sblock 23dB @600KHz
SNRmin 9dB; f ch 200KHz
L{} 102 23910log(200K )
141dBc / Hz @600KHz

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-4
Spurious-Tone Performance

Sblock
SNR
fRF fIF
Sdesired

 fLO IF
RF

Sspur

LO 

Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou V-5
Spurious-Tone Requirement

SNR  Sdesired  Snoise

 Sdesired (Sblock  S spur )
S spur  Sdesired  Sblock  SNRmin
Ex: GSM
Sdesired  102dB; Sblock 23dB @ 600KHz
SNRmin 9dB;
S spur  102 239  88 dBc

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-6
Typical Figure of Merits for VCO

Frequency ~ 1 – 5 GHz
Tuning Range ~ 10 – 20 %
Phase Noise - 105 dBc/Hz @ 100 KHz
Supply Voltage ~ 1.5 V
Current < 10 mA

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-7
Oscillation Theory

Y(s) H(s)

X(s) 1  H(s)G(s)
For steady oscillation, Barkhausen’s criteria must be simultaneously met:
H (s )G (s )  1
H ( s )   G ( s )  2 n

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-8
Negative Resistance Model

Z a s  Z r s  Equivalent Circuit

GL  GM

During Oscillation:

Re Z a s   Re Z r s   0

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-9
Negative Resistance Model

G m Z in
A
1  G o Z in
A V2
1  1 
V1 Go Y   G o  G mβ    G o  1  A β 
Gm Z in  Z in 
Determine the oscillation frequency

Im Y   0
Zin

β V2 Im 1  Aβ   0
Oscillation:
 1  
Aβ  1  Re    G o  1  A β   0
  Z in  
Negative Conductance

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-10
Negative Resistance Model

Z(jω)

1
fo 
2 L C
Z(j)

f0

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-11
Ring vs LC Oscillators

Parameters Ring VCO LC VCO

Phase Noise Poor Good

Tuning Range Large Small

Power Consumption High Low

Chip Area Small Large

Output Waveform Square Sinusoidal

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-12
Ring VCO

 A Cascade of Delay Cells Connected in Feedback to Meet

Oscillation Criteria ( Barkhausen)
 Loop Gain @ wosc > 1
 Total Phase Shift @ wosc = 2nπ
 For Single-Ended Design, Needs An Odd Number of
Delay Cells to provide 2nπ phase shift
1
f osc 
2N d

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-13
Implementation of Ring Oscillator

 GmR0
in H ( j 0 )  ( )N
out 1  j0 R0C0
1
f osc 
2 N d

 Gm  Gm  Gm

C0 R0 C0 R0 C0 R0

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-14
Ring VCO

 Delay Cells Can Simply Be Digital or Analog Inverters

 Delay and Frequency Can Be Tuned By Bias Current,
Device Transconductance, or Loading Resistance or
Capacitance
 Can Provide Rail-To-Rail Output Waveform and Wide
Tuning Range
 All Components Contribute Phase Noise

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-15
Delay Cells

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-16
Ring VCO – Differential Design

 Signal is Increased by 6 dB while Noise is Increased by 3

dB => Phase Noise is Improved by 3 dB
 Common-Mode Rejection (Supply, Even-Order
Harmonics, Common-Mode, Substrate Noise)
 Double Power, Double Chip Area

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-17
LC VCO – Single-Ended Design

 Use Feedback Principle for Oscillation:

 Loop Gain @ wosc > 1
 Total Phase Shift @ wosc = 2nπ
 Critical to Include Impedance Transform:
 Not to Degrade Tank Q
 Improve Gain for Oscillation
 Either Capacitive or Inductive Divider Can Be Used for
Impedance Transformation

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-18
LC VCO – Single-Ended Design

Feedback can be
from drain to source
or gate to source

Impedance Transform

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-19
LC VCO – Single-Ended Design

1
f 
o

L1 2 (L1  L2 )C

RL L2 L2 2
RL  Rs (1 )
L1

Hartley Oscillator
Rs

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-20
LC VCO - Single-Ended Design

1
f 
o
C1C2
2 L( )
C1 C2
RL
C2 2
C1 RL  Rs (1 )
C1

Rs C2 Colpitts Oscillator

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-21
LC VCO – Negative Resistance Design

 Make Use of LC Resonant Tank

 Use Negative-Gm Compensation Technique to Achieve
Infinite Q for Oscillation

C C
LP LP

YL GP -Gm Yeq Geq= 0

Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou V-22
Negative Resistance

-Gm
M1 M2

IB

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-23
Negative Resistance
ix Vx

id2
M1 M2

IB

ix  id 2  id 1 v x  Vgs 2  v gs1

gm
ix  Gm v x   vx
2
At high-frequency the device capacitance and input resistance
should be included in the analysis.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-24
Differential VCO

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-25
Differential VCOs

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-26
LC VCO – Frequency Tuning

1
f 
2 LC
osc

 Frequency Tuning Can Be Achieved By Tuning

Capacitance Using a Varactor or a Switchable
Capacitor Array (SCA)
 Or Effective Inductance

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-27
PN-Junction Varactor

C
n+ p+ C A
T
jo

V
n-well 1 B

 F

1
Q 
R C
C

RS CT S T

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-28
PN-Junction Varactor

1.5
Capacitance=img(Y11)/w (pF)

1.4

1.3

1.2

1.1

1.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Control Voltage (V)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-29
PN-Junction Varactor

 Make Use of Depletion Capacitance of p-n Diode Junction

 n+ Contacts Are Used to Minimize Contact Resistance and
thus to Maximize Q
 Reducing Size of p+ Would Minimize p+ Series Resistance

 Increasing Size of p+ Would Increase Number of Contacts

and Reduce Contact Resistance
 Measurements Indicate Contact Resistance Dominates =>
Larger Size of p+ Diffusion is Desired for Higher Q

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-30
Accumulation-Mode Varactor

1 1 1
n+ n- n- n+  
C C C
T ox dep

n-well

1
Q 
R C
C

S T

RS CT

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-31
Accumulation-Mode Varactor

1.4
Capacitance=img(Y11)/w (pF)

1.2

1.0

0.8
-2 -1 0 1 2

Control Voltage (V)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-32
Accumulation-Mode Varactor

 Similar to NMOS with N-Well Instead of P-Substrate

 n+ Are Used to Minimize Parasitic p-n Junction
Capacitance to Maximize Tuning
 For Gate Voltage Larger Than Flat-Band Voltage VFB =>
Accumulate => CT = Cox
 For Smaller Gate Voltage, Depletion Capacitance Cdep
Exists Between Oxide and N-Well => 1/CT = 1/Cox + 1/Cdep
 Compared to p-n Junction Capacitance, Advantages of
Accumulation-Mode Capacitance Include [Soorapanth]:
 Better Average Q
 Larger Tuning Capacitance

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-33
Switchable-Capacitance Array

CU CU CU

M1
CGD RON RON
CGD

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-34
Larger Tuning Range

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-35
Switchable-Capacitance Array

Coff Con-Coff Con C

u
CU
CC
C 
off
u gd

M1
C C u gd

1
Q 
R C
C

on on

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-36
Switchable-Capacitance Array

 Wide Tuning Range Can Be Achieved By Increasing

Number of Bits in the Array
 Large Switch => Small Turn-On Resistance => High Q
 Large Switch => Large Parasitic Capacitance => Small
Tuning Range and Limited Operating Frequency

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-37
Phase Noise Estimation

Phase Noise
Power

dBc
f –3 (flicker FM)
f –2 (random walk phase or white FM)
f -1 (flicker phase)
 f 0 (white phase)
1Hz Frequency
0 Freq

 Psideband0  ,1Hz
Ltotal  10  log 
 P carrier 

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-38
Phase Noise Estimation-Leeson’s Model

  
L( )  S  ( ) 1  ( 0 ) 2 
 2 Q  
α 2 FkΤ
S  ( )  
Δω Ρs
S   (  ) L() 1 /( ) 3

1 /( ) 1 /( )
Noise floor
1 /( ) 2

 Δω

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-39
Phase Noise – Hajimiri’s Theory

ν(t) ν(t)

t t

i(t) i(t)

τ t τ t
(a) (b)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-40
Phase Noise – Hajimiri’s Theory

f(x)
1 1
' '
f rise f fall
1

f ' rise  f ' fall

2 x

(x)
1 2
'
f rise f ' fall

2 x
2 1
f ' rise f ' fall

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-41
Phase Noise – Hajimiri’s Theory

 Use Impulse Sensitivity Function (ISF) G(x) which is a

Periodic Function of Phase Shift for A Unit Impulse
Applied at Time t = x
 Phase Noise is Maximum when Noise Current Impulses are
Injected at Zero-Crossing Point
 Phase Noise is Minimum when Noise Current Impulses are
Injected at Output Peaks

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-42
Phase Noise – Hajimiri’s Theory

rms
2
i 2n / f
L()  2 
q max 2() 2

c i / f 1 / f
2 2
L( )  2  
0 n
q max 8( ) 
2

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-43
Phase Noise in the VCO

We see that all noise a distance ω around all the harmonics,

including DC, contributes to the phase noise. DC 1/f noise
contributes to the 1/f3 region.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-44
Optimization of Phase Noise in the LC VCO
•Evaluate the optimization gate length of the active device
•Calculate minimize spectral density of each oscillator noise
source by using the optimization gate length of the active
device.
•Derive the impulse sensitivity function of each oscillator
source after the transient simulation is done when a current
noise is injected at the node of the oscillator circuit
(Cadence SpectreRF).
•Combine
.
above results to obtain for each oscillator noise
source.
•Calculate Fourier Series Coefficient for each ISF
•Calculate the overall output phase noise using the results
from above step.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-45
Quadrature Phase Generator

•Divide-by-2
•Quadrature VCO
•Poly phase shifter (RC-CR network)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou V-46