ARM LEGv8 and MIPS: Comparative Study
An “Introduction to Computer Architecture (ECEN 432)” Project Report by
Nayera Hisham Elsaady 18100036
Nourhan Salim 18101619
Ahmed Ayman Abo Elmagd 18100767
Mohamed Ibrahim Seada 18102078
Submitted in partial fulfilment for the requirements of the ECEN 432 project to
Dr. Eman Gewish
Fall 2021
2
ARM LEGv8 and MIPS: Comparative Study
Ahmed Abo Almagd, Mohamed Seada, Nayera Elsaady & Nourhan Salim
School of Engineering and Applied Sciences, Nile University, Cairo, Egypt
Abstract— Since out studies focus on Reduced Instruction Set MIPS and ARM both use the RISC architecture, which is a
Chip RISC architecture like MIPS and ARM, the target in areas load-store architecture, and since they use the same ISA, both
of research and design is to perform comparative studies that later models are quite similar. In comparison to ARM, MIPS has
on help in the optimization of such architectures based on the field more general-purpose registers. Although a few of these
and its usage. ARM, unlike the MIPS, has 16 registers only. It also registers have unique purposes, this effectively restricts the
has a higher throughput, and efficiency as they support 64-bit data
buses. The project will focus on the implementation of ARM
number of registers that the programmer has access to on a
LEGv8, a more down to earth subset implementation of the regular basis. MIPS also needs to employ additional instruction
ARMv8 – one of the top ARM architectures. The choice of ARM fields to define register operands, which reduces the flexibility
LEGv8 is based on its usage and definition in “Computer of the MIPS instructions. ARM, on the other hand, addresses
Organization and Design Book”. this problem by giving more bits to encode more alternatives,
resulting in more flexible addressing modes.
Keywords— ISA, architecture, MIPS, ARM, LEGv8, waveform.
ARM’s code is more efficient and denser since all of its
I. INTRODUCTION instructions may be conditionally executed, whereas MIPS only
allows conditional branches. Both MIPS and ARM
ISA is the inly way the user can interact with the hardware,
architectures implement conditional execution, but in slightly
and with it comes various different types of architectures that
different ways. MIPS evaluates conditional branches using the
compete to provide the best performance when it comes to
contents of the registers, whereas ARM employs the condition
processors and embedded systems.
field in addition to the four conational flags contained in the
CISC stands for Complex Instruction Set Computer. It was
CPSR. Furthermore, both MIPS and ARM employ a stack
invented by computer developers to create the job of the
pointer to manage the stack, therefore their stack
compiler simpler. Typically, this architecture implements over
implementations are identical. However, the MIPS architecture
a hundred instructions of variable byte count and complexity.
typically only has one stack, whereas the ARM architecture has
Because some of these instructions can modify data directly
several stacks, each of which must be started during system
from memory, they must be encoded with a big memory
startup and the list of differences and similarities can go on and
address. RISC stands for Reduced Instruction Set Computer;
on [3,4].
this architecture was created to address the weaknesses of the
With the impressive developments in the embedded
CICS architecture. RISC processors, unlike CISC cousins, use
microprocessors industry and especially in mobile
fixed-size instructions, making instruction decoding easier
development, the ARM architecture tops the field. ARM, or
[1,2].
"Advanced RISC Machine" was developed by Arm Ltd based
RISC as mentioned before is a microprocessor architecture
on an optimized RISC architecture. Smartphones, tablets,
that contain a small, highly optimized set of instructions instead
laptops, video game consoles, and desktop computers, as well
of the specialized set of instructions seen in other architectures.
as an increasing number of other smart devices, are all using
Compared to CISC, it is widely regarded as the most efficient
processors based on this architecture [5].
CPU architectural technology available today. A central
With a high performance, moderate price, low power
processing unit (CPU) that uses RISC can perform more with
consumption, and small size, it deserves its wide-spread
less time, which results in an improved performance. The
application and the 50 billion distributed and used licenses. The
ability to extend the register set and internal parallelism by
newer versions of the ARM architecture have a 64-bit addresses
raising the number of parallel threads performed by the CPU
and 32 registers [6-8]. One of the most famous and efficient
and improving the speed of the CPU's executing instructions is
ARM versions is the ARMv8. The ARM ISA in general is way
a fundamental RISC feature. Most RISC processors have the
much bigger than the MIPS and so instead of implementing the
following architectural features:
ARMv8 ISA, a famous subset of the ARMv8-A version is used,
• One-cycle execution time: RISC processors have a one-
developed by ARM as an educational testing kit, commonly
cycle CPI (clock per instruction). This is because to the
referred to as LEGv8, which is closer to the MIPS in size and
CPU's optimization of each instruction and a method
simplicity. [9,10].
known as Pipelining is a technique for more effectively
The details of both the MIPS and LEGv8 structure will be
processing instructions by allowing segments, or stages, of
further discussed in detail. The paper’s target is to provide a
instructions to be executed at the same time.
comparative study between the MIPS and the LEGv8
• High number of registers: The RISC design philosophy architectures. The implementations done are a simulation for
supports many registers to avoid significant amounts of the single-cycle processors for both the MIPS and the LEGv8
memory interactions.
3
on Xilinx’s Verilog and test benches are used to compare both
architectures.
II. SYSTEM DESIGN
MIPS contains 32 general purpose 32-bit registers that are
numbered 0-31. A 32-bit single cycle MIPS processor is
divided into two components: a 32-bit data path and a control
unit. LEGv8 – just like the ARMv8 – has 32 registers, 31
general ones and a zero register. It has a 64-bit data address size,
and a 32-bit instruction address size. The general difference
between both is the number of registers, the address sizes, and
Figure 2 Data Memory
other points in the ISA itself.
Both the MIPS and LEGv8 single-cycled processors perform
basic arithmetic, control, and data operations. Both processors
consist of basic constant blocks which are Program Counter D. Register File
(PC), control unit, instruction memory, data memory, register
file and Arithmetic Logic Unit (ALU), all that will be further
discussed in detail. Other blocks are necessary for the validation
of the CPU’s functionality like adders, multiplexers, sign
extend units and others.
A. Program Counter (PC)
PC Function is to increments by 4 with every clock cycle ( Its
initial value should be the address of the first instruction to be
executed) Figure 3 Register file
E. Arithmetic Logic Unit (ALU)
simple ALU with 5 operations (And, Or, Add, Subtract).
B. Instruction Memory
Figure 4 ALU
F. Control Unit
responsible for taking the instruction and generating the
appropriate signals for the Datapath elements.
Figure 1Instruction Memory Figure 5 Control Unit
C. Data Memory G. Full MIPS single Cycle processor Implementation
implements the functionality for reading and writing data
to/from memory
4
Figure 6 Full MIPS single Cycle processor Implementation
Holds the program instructions that are to be executed in 4 Figure 8 Program Counter in ARM
locations each (8-bit in each location, 32-bit total for each
instruction) 1- Register with 32-bit
• INSTRUCTION MEMORY
III. METHODOLOGY o MIPS
A. Program Counter
A. MIPS
Figure 9 Instruction Memory in MIPS
1- A: 32-bit input
2- RD: 32-bit output
o ARM
Figure 7 Program Counter in MIPS
1- PCNext: 32-bit that comes from multiplexer
2- Reset
3- CLK
4- PCcurrent: output 32-bit that enters instruction
memory
o ARM
Figure 10 Instruction Memory in ARM
1- PC: 64-bit input
2- Output CPU_Instruction is 32-bits333
• DATA MEMORY
o MIPS
5
Figure 13 Register file in MIPS
Figure 11 Data Memory in MIPS 1- RA1: 5-bit input to determine our first source register
2- RA2: 5-bit input to determine our second source
register
1- CLK 3- WA3: 5-bit input to determine our destination
2- We: we enable signal (1 when using store instruction, register
0 otherwise) 4- WD3: 32-bit data required to be stored
3- Wd: 32-bit input data which is required to be stored. 5- WE3: control signal to determine whether we will
4- A: 32-bit signal to determine the address in the write the wd input in the register determined by the
memory to either read its data or write the WD in it. wa3 input
5- RD: 32-bit output of the data 6- CLK
7- RD1: 32 -bit output of the value stored in the register
o ARM determined by the ra1 input signal
8- RD2: 32-bit output of the value stored in the register
determined by the ra1 input signal
o ARM
Figure 12 Data Memory in ARM
1- InputAddress is 64-bits that comes from ALU
2- InputData is 64-bits that comes from read2 from the
registers
3- CONTROL_MemRead and CONTROL_MemWrite Figure 14 Register file in ARM
comes from Control Units
• REGISTER FILE 1- COTROL_REGWRITE comes from Control Unit
o MIPS 2- Read1 and read2 takes 6-bits from instruction
3- WriteReg takes 5-bits
4- WriteData takes 64-bits that comes from results
• ALU
o MIPS
6
o Add Funct: 6'b100000
o Sub Funct: 6'b100010
o And Funct: 6'b100100
o Or Funct: 6'b100101
o ARM
Figure 15 ALU in MIPS
1- ALU is used to make ADD, SUB, and OR
o ARM
Figure 18 Control unit in ARM
1- Is done by connecting all components together
without making its own module
Figure 16 ALU in ARM
IV. RESULTS AND ANALYSIS
1- Used to make ADD, SUB, logical ADD, logical OR Waveforms
2- Also used to make ADD for adderNextPC and o MIPS
adderShiftPC.
• CONTROL UNIT
o MIPS
Figure 19 Result Waveform of MIPS
o ARM
Figure 17 Control unit in MIPS
• 6 bits opcode ([31:26] bits of the output instruction)
o R-type opcodes are: 6’b000000
o LW opcode: 6'b100011
o SW opcode: 6'b101011
o Addi opcode: 6'b001000
o J opcode: 6'b000010
• 6 bits func ([5:0] bits of the instruction)
o Only used to decode R-Type instructions
7
[1] S. Chevtchenko and Vale, “A Comparison of RISC and CISC
Architectures.” [Online].
[2] N. Hussain, Amanulllah, F. Ahmad, and S. Khan, “Comparative
Study of RISC AND CISC Architectures,” International Journal
of Computer Applications Technology and Research, vol. 5, no.
7, pp. 500–503, 2016, [Online].
[3] “Stanford Computer Science,” Stanford.edu, 2021.
https://cs.stanford.edu/ (accessed Jan. 03, 2022).
[4] M. Mahmoud, “An Architecture Comparison between MIPS and
ARM,” ResearchGate, May 15, 2020.
[5] Arm Ltd, “Artificial Intelligence Enhanced Computing,” Arm |
The Architecture for the Digital World, 2015.
Figure 20 Result Waveform in ARM [6] M. A. Laurenzano et al., “Characterization and bottleneck
analysis of a 64-bit ARMv8 platform,” 2016 IEEE International
Symposium on Performance Analysis of Systems and Software
(ISPASS), Apr. 2016, doi: 10.1109/ispass.2016.7482072.
[7] S. Kady, M. Khater, and M. Alhafnawi, “MIPS, ARM and
SPARC-an Architecture Comparison.” [Online].
[8] M. N. Asghar, “A Review of ARM Processor Architecture
History, Progress and Applications,” Journal of Applied and
Emerging Sciences, vol. 10, no. 2, p. 171, Dec. 2020, doi:
10.36785/jaes.102446.
[9] D. A. Patterson and J. L. Hennessy, Computer organization and
design: the hardware/software interface. Cambridge, Ma, United
States: Morgan Kaufmann Publishers, 2018.
[10] Arm Ltd, “Graphical Micro-Architecture Simulator | LEGv8,”
Arm | The Architecture for the Digital World, 2015.
Figure 21 Result Waveform in ARM
Differences
1. PC module is not constructed in ARM
2. Sign extended depends on format of instruction
Ex: Branch, Condition Branch, D Type: R Type in
MIPS
3. ALU instruction is 11-bits in ARM and 6-bits in
MIPS
4. ALU out is 4-bits while MIPS is called ALUControl
and have 3-bits
5. ALU input in ARM is 64-bits while MIPS is 32-bits
6. In ARM code ALU is used to compute Adder
PCNext and Adder ShiftPC
7. ARM has input of 64-bits while MIPS is 32-bits
In conclusion ARM saves several CLK cycles when fetching
compared to MIPS and Data bus output in ARM it outputs
more data.
V. CONCLUSION
In conclusion, The ARM LEGv8 was designed and
implemented with a basic ISA and compared to a MIPS single
cycle. It was found that the differences weren’t as big in delays
as it didn’t differ as much from a MIPS’s architecture and basic
ISA when it comes to the core alone. It was also found that the
changes start to appear when taken into account the peripherals
that come with ARM such as NVIC, SYSTick and DMA that
are interfaced with the core and aren’t affected by its ISA.
Therefore, on a basic core level the MIPs and LEGv8 didn’t
differ a lot.
REFERENCES
