MLX81115 Dual LIN RGB Controller

Datasheet

1. Features
Configurations
 MLX81115: 12 pin device in DFN12 4x4 package, 32kB Flash memory + 16kB ROM

Application Controller
 Internal RC-Oscillator (24 MHz default clock)
 16-bit MULAN MCU with
o max. 32kByte Flash
o 16kB ROM with MLX4 LIN firmware, MLX16 LIN boot-loader and MLX16 Application User
Library
o 2048 Byte RAM
o 512 Byte NVRAM with ECC (256 Byte for customer purpose)
 Math Co-processor for 32 bit MUL/DIV Operations
 LIN Protocol Controller according to LIN 2.x and SAE J2602
 Baudrate up to 19.2 kBaud
 Frame processing
 Low interrupt load to the application

LIN Transceiver according to LIN 2.x and SAE J2602

 Support for Autoconfig according bus shunt method

IO configuration
 MLX81115
o 2 x 3 high voltage I/Os with free configurable current sources (up to 48mA) for RGB
 Diagnostic capability for connected LED
 6x 16-bit PWM outputs
 Interrupt capability for all inputs
 Configurable wake up sources (LIN and IOs)
 10 bit ADC with DMA, conversion time <6us, multiple channels and 3 different reference voltages

Voltage Regulator
 Low standby current consumption of max. 38µA in sleep mode
 Integrated battery monitor including over- and under-voltage detection

Other Features
 Automotive Temperature Range of -40°C to 125°C
 28V jump start
 Integrated temperature sensor

Applications
 Any kind of LIN switch applications in automotive
 LIN slaves for LED lighting applications including RGB control
 LIN IO-Extension

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Ordering Information

Part No. Temp. Code Package Code Option Code Packing Form Code

MLX81115 K LW AAD-123 RE

Legend:
Temperature Code: K = -40 to 125°C
Package Code: LW = QFN/DFN with wettable flanks
Option Code: ABC = A – Major Hardware Design Revision, BC – ROM Code Revision
123 = Melexis Reserved
Packing Form: RE = Reel
Ordering example: MLX81115KLW-AAD-100-RE

For the correct order code please contact our sales team. The contact details can be found in chapter Contact
Information.

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2. Contents
1. Features .......................................................................................................................................................................................................... 1
2. Contents .......................................................................................................................................................................................................... 3
2.1. List of Figures .......................................................................................................................................................................................... 6
2.2. List of Tables............................................................................................................................................................................................ 7
2.3. Abbreviations .......................................................................................................................................................................................... 9
3. References .................................................................................................................................................................................................... 10
4. Technical description .................................................................................................................................................................................... 11
4.1. Package data DFN12 4x4 ....................................................................................................................................................................... 11
4.2. IC Marking ............................................................................................................................................................................................. 12
4.3. Pin out description ................................................................................................................................................................................ 13
4.4. Electrical characteristics ........................................................................................................................................................................ 14
4.4.1. Absolute maximum ratings............................................................................................................................................................ 14
4.4.2. Operating conditions ..................................................................................................................................................................... 15
4.4.3. Electrical parameter specification ................................................................................................................................................. 16
5. Typical application examples ........................................................................................................................................................................ 24
5.1. Application Example MLX81115 ............................................................................................................................................................ 25
6. Block diagram................................................................................................................................................................................................ 26
7. System behavior description ......................................................................................................................................................................... 27
7.1. The supply system ................................................................................................................................................................................. 27
7.2. Power On .............................................................................................................................................................................................. 28
7.3. Power Off .............................................................................................................................................................................................. 29
7.4. System initialization and Trimming ....................................................................................................................................................... 30
7.5. Entering SLEEP MODE (GO TO SLEEP MODE = GTSM) ........................................................................................................................... 30
7.6. WAKE UP from SLEEP MODE ................................................................................................................................................................. 31
7.7. System behavior in case of different under voltage conditions ............................................................................................................ 32
7.8. Supply voltage VS over and under voltage detection ............................................................................................................................ 33
7.9. Enter the Low Power Mode................................................................................................................................................................... 34
8. CPU core MULAN3 – MULtiple CPU with Analogue and Network support .................................................................................................... 35
8.1. MULAN3 compared to MULAN2 ........................................................................................................................................................... 35
8.2. MULAN3 CPU Performance ................................................................................................................................................................... 35
8.3. Math Co-Processor ................................................................................................................................................................................ 35
8.4. CPU Architecture ................................................................................................................................................................................... 36
8.5. CPU Address space ................................................................................................................................................................................ 36
8.6. Memory mapping .................................................................................................................................................................................. 37
9. IO Registers ................................................................................................................................................................................................... 39
9.1. General.................................................................................................................................................................................................. 39
9.2. System Protected ports ......................................................................................................................................................................... 39
9.3. Standard ports....................................................................................................................................................................................... 41
10. Memories .................................................................................................................................................................................................... 45
10.1. RAM sharing ........................................................................................................................................................................................ 45
10.2. Flash sharing........................................................................................................................................................................................ 45
10.3. Flash memory ...................................................................................................................................................................................... 45
10.3.1. Flash Trimming ............................................................................................................................................................................ 46
10.3.2. Flash ports ................................................................................................................................................................................... 47
10.4. NVRAM................................................................................................................................................................................................ 47
10.4.1. NVRAM organization ................................................................................................................................................................... 49
10.4.2. NVRAM ports............................................................................................................................................................................... 50
11. Interrupts .................................................................................................................................................................................................... 51
11.1. Introduction ........................................................................................................................................................................................ 51
11.2. Interrupt sources ................................................................................................................................................................................. 51
11.2.1. High level system interrupts ........................................................................................................................................................ 51
11.2.1.1. Reset interrupt and watchdog ............................................................................................................................................. 51
11.2.1.2. Stack error ........................................................................................................................................................................... 51
11.2.1.3. Exception error .................................................................................................................................................................... 52
11.2.1.4. Protection error ................................................................................................................................................................... 52
11.2.1.5. Invalid address..................................................................................................................................................................... 52
11.2.1.6. Program error ...................................................................................................................................................................... 52
11.2.2. User block interrupts ................................................................................................................................................................... 52
11.3. Interrupt management........................................................................................................................................................................ 52
11.3.1. Interrupt enabling and masking .................................................................................................................................................. 52
11.3.2. Pending interrupts....................................................................................................................................................................... 53
11.3.3. Call and jump interrupts .............................................................................................................................................................. 53
11.4. Interrupt priorities .............................................................................................................................................................................. 53
11.4.1. User priority ................................................................................................................................................................................ 54
11.5. Mlx16 interrupt table .......................................................................................................................................................................... 55
11.5.1. Interrupt vectors ......................................................................................................................................................................... 56
11.6. External Interrupts .............................................................................................................................................................................. 57
12. PWM ........................................................................................................................................................................................................... 60
12.1. General introduction and features ...................................................................................................................................................... 60

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12.2. Block diagram and description ............................................................................................................................................................ 60

12.3. PWM frequency control ...................................................................................................................................................................... 61
12.4. PWM frequency parameter selection ................................................................................................................................................. 62
12.5. Synchronization of the PWM modules ................................................................................................................................................ 63
12.6. Independent mode.............................................................................................................................................................................. 63
12.7. Mirror mode ........................................................................................................................................................................................ 64
12.8. PWM control and command ports ...................................................................................................................................................... 65
12.9. Interrupt connections.......................................................................................................................................................................... 67
12.10. Routing of PWM outputs to external pins ......................................................................................................................................... 67
13. Timers ......................................................................................................................................................................................................... 68
13.1. Simple 15bit Timer .............................................................................................................................................................................. 68
13.2. Universal 16bit Timer .......................................................................................................................................................................... 68
13.2.1. Introduction and Features ........................................................................................................................................................... 68
13.2.2. Block diagram and description .................................................................................................................................................... 70
13.2.3. Timer mode ................................................................................................................................................................................. 70
13.2.4. Dual Timer Compare mode ......................................................................................................................................................... 72
13.2.5. Dual Timer Capture mode ........................................................................................................................................................... 73
13.2.5.1. Functional block diagram .................................................................................................................................................... 73
13.2.5.2. Output signals...................................................................................................................................................................... 74
13.2.5.3. Usage and example ............................................................................................................................................................. 74
13.2.6. Timer Capture/Compare mode ................................................................................................................................................... 75
13.2.6.1. Functional block diagram .................................................................................................................................................... 75
13.2.6.2. Output signals...................................................................................................................................................................... 76
13.2.7. Pulse accumulator mode ............................................................................................................................................................. 77
13.2.7.1. Functional block diagram .................................................................................................................................................... 77
13.2.7.2. Output signals...................................................................................................................................................................... 77
13.2.7.3. Usage and example ............................................................................................................................................................. 77
13.2.8. Debouncer mode......................................................................................................................................................................... 78
13.2.8.1. Functional block diagram .................................................................................................................................................... 78
13.2.8.2. Output signals...................................................................................................................................................................... 78
13.2.8.3. Usage and example ............................................................................................................................................................. 79
13.2.9. Timers IO ports ............................................................................................................................................................................ 79
13.2.10. Interrupt connections ................................................................................................................................................................ 83
14. RC-Oscillator................................................................................................................................................................................................ 84
15. Temperature Detection ............................................................................................................................................................................... 85
16. AD converter system ................................................................................................................................................................................... 86
16.1. ADC Block diagram .............................................................................................................................................................................. 86
16.2. ADC control and command ports ........................................................................................................................................................ 87
16.3. ADC Channel selection Guide .............................................................................................................................................................. 89
16.4. ADC Reference Voltage and Hardware Trigger Selection .................................................................................................................... 90
16.5. Hardware SC filter triggered RGB channels ......................................................................................................................................... 90
16.6. ADC result list format .......................................................................................................................................................................... 90
16.6.1. Calculation Instruction for the measured Input Voltage ............................................................................................................. 91
16.6.2. Accuracy of the HVIODIFFx Input Channel .................................................................................................................................. 91
16.7. Trimming of ADC reference voltage .................................................................................................................................................... 91
16.8. ADC conversion time ........................................................................................................................................................................... 91
16.9. Stopping the ADC conversion .............................................................................................................................................................. 91
16.10. Disabling the ADC .............................................................................................................................................................................. 92
16.11. Measuring the chip temperature ...................................................................................................................................................... 92
17. Digital Watchdog ......................................................................................................................................................................................... 94
17.1. Introduction and features ................................................................................................................................................................... 94
17.2. Applications......................................................................................................................................................................................... 94
17.3. Block diagram and description ............................................................................................................................................................ 94
17.4. Timer mode ......................................................................................................................................................................................... 95
17.5. Window mode ..................................................................................................................................................................................... 95
17.6. Intelligent mode .................................................................................................................................................................................. 95
17.7. Watchdog Control and Command ports .............................................................................................................................................. 96
17.8. Interrupts connections ........................................................................................................................................................................ 97
17.9. Reset state .......................................................................................................................................................................................... 97
18. Analogue Watchdog (AWD) ........................................................................................................................................................................ 98
18.1. AWD Ports ........................................................................................................................................................................................... 98
18.2. Interrupt connections.......................................................................................................................................................................... 99
19. LIN Interface .............................................................................................................................................................................................. 100
19.1. Introduction ...................................................................................................................................................................................... 100
19.2. LIN Physical Layer .............................................................................................................................................................................. 101
19.3. Application Recommendations for the pins LIN_IN and LIN_OUT ..................................................................................................... 101
19.4. LIN Slave Node Position Detection (Auto-configuration)................................................................................................................... 101
20. Multi purpose high voltage IOs (HVIOs) .................................................................................................................................................... 102
20.1. HV IOs Connection matrix ................................................................................................................................................................. 103
20.2. RGB control ....................................................................................................................................................................................... 103
20.3. RGB monitoring ................................................................................................................................................................................. 105
20.4. Shunt Current Measurement ............................................................................................................................................................ 105

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20.5. HVIO configuration ports .................................................................................................................................................................. 107

21. The safety concept .................................................................................................................................................................................... 111
21.1. IC Behavior in the fault case .............................................................................................................................................................. 112
21.1.1. Loss of battery ........................................................................................................................................................................... 112
21.1.2. Loss of Ground .......................................................................................................................................................................... 112
21.1.3. Short circuit to battery .............................................................................................................................................................. 112
21.1.4. Short circuit to ground .............................................................................................................................................................. 112
21.1.5. Thermal overload ...................................................................................................................................................................... 112
21.1.6. Under-voltage VS....................................................................................................................................................................... 112
22. ESD and EMC ............................................................................................................................................................................................. 113
22.1. Automotive Qualification Test Pulses according to ISO7637-2/3 and ISO16750-2 ............................................................................ 113
22.1.1. Test Pulses on supply Lines (directly connected to Car Battery) ............................................................................................... 113
22.1.2. Test pulses on LIN_IN and LIN_OUT Lines ................................................................................................................................. 114
22.1.3. Test pulses on signal lines, incl. LIN_IN, LIN_OUT...................................................................................................................... 114
22.1.4. EMV Test pulse definition.......................................................................................................................................................... 115
22.1.5. Circuitry recommendations for improved ESD and EMC behavior ............................................................................................ 116
22.1.5.1. External Circuitry on Supply Lines ..................................................................................................................................... 116
22.1.5.2. External Circuitry on LIN Lines ........................................................................................................................................... 117
22.1.5.3. External Circuitry on Signal Lines ....................................................................................................................................... 117
22.2. ESD Robustness according to IEC61000-4-2 ...................................................................................................................................... 117
23. Debugging Facilities .................................................................................................................................................................................. 119
23.1. Debug Interface................................................................................................................................................................................. 119
23.2. Melexis Mini E-Mlx emulator ............................................................................................................................................................ 121
24. End of Line Programming .......................................................................................................................................................................... 122
25. Standard information regarding manufacturability of Melexis products with different soldering processes ........................................... 122
26. Disclaimer ................................................................................................................................................................................................. 124
27. Contact Information .................................................................................................................................................................................. 124
28. History record ........................................................................................................................................................................................... 125
28.1. Change list for ROM code .................................................................................................................................................................. 125

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2.1. List of Figures

Figure 1 - DFN12 4x4 Package ................................................................................................................................ 11
Figure 2 – LIN timing diagram: Relation between propagation delay and duty cycle............................................ 23
Figure 3 – Application schematic sample ............................................................................................................... 25
Figure 4 – Block Diagram ........................................................................................................................................ 26
Figure 5 – Supply and Under voltage concept ....................................................................................................... 28
Figure 6 – Signal behavior during Power On .......................................................................................................... 29
Figure 7 – Signal behavior to and from SLEEP MODE............................................................................................. 32
Figure 8 – block diagram over- and under-voltage detection ................................................................................ 33
Figure 9 – CPU architecture ................................................................................................................................... 36
Figure 10 – Memory mapping ................................................................................................................................ 37
Figure 11 – MLX4 and MLX16 RAM sharing principle ............................................................................................ 45
Figure 12 – Flash organization (8Kx32) .................................................................................................................. 46
Figure 13 – Interrupt vectors ................................................................................................................................. 56
Figure 14 – Functional diagram of one PWM module. .......................................................................................... 60
Figure 15 – Relation between PWM resolution and frequency (M=0) .................................................................. 62
Figure 16 – Internal daisy chain connection of the PWM modules. ...................................................................... 63
Figure 17 – sample configurations with multiple master and slave modules. ....................................................... 63
Figure 18 – PWM output signal in independent mode. ......................................................................................... 64
Figure 19 – PWM output signal in mirror mode. ................................................................................................... 65
Figure 20 – Simple Timer ........................................................................................................................................ 68
Figure 21 – Functional diagram of Timer module. ................................................................................................. 70
Figure 22 – Timer mode block diagram. ................................................................................................................. 71
Figure 23 – Dual timer compare block diagram. .................................................................................................... 72
Figure 24 – Dual timer capture block diagram. ...................................................................................................... 73
Figure 25 – Timer compare/capture block diagram. .............................................................................................. 75
Figure 26 – 16-bits pulse accumulator block diagram. .......................................................................................... 77
Figure 27 – Debouncer block diagram. .................................................................................................................. 78
Figure 28 – AD converter overview illustrating control including DMA and channel multiplexing ....................... 86
Figure 29 – ADC Reference voltage selection ........................................................................................................ 90
Figure 30 – Functional diagram of the Watchdog block. ....................................................................................... 94
Figure 31 – LIN OSI-Reference model .................................................................................................................. 100
Figure 32 – Principle architecture of a LIN-network supporting auto-configuration measurements .................. 101
Figure 33 – HVIO functional diagram ................................................................................................................... 102
Figure 34 – Block diagram for RGB control at the HVs ......................................................................................... 104
Figure 35 – Principle Inline current measurement ............................................................................................... 105
Figure 36 – Function Block of shunt measurement unit ...................................................................................... 106
Figure 37 – Used application circuitry for the IEC 61000-4-2 test ....................................................................... 118
Figure 38 – RGB-controller debug interface with the Melexis Mini E-Mlx emulator ........................................... 120

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2.2. List of Tables

Table 1 – Absolute maximum ratings ..................................................................................................................... 14
Table 2 – Operating conditions .............................................................................................................................. 15
Table 3 – Electrical parameter specification .......................................................................................................... 19
Table 4 – Electrical information parameters specification ..................................................................................... 20
Table 5 – LIN related parameters ........................................................................................................................... 22
Table 6 – RGB monitoring parameters ................................................................................................................... 23
Table 7 – Wakeup Source ....................................................................................................................................... 31
Table 8 – System behavior in different UV conditions ........................................................................................... 32
Table 9 – RC-Control port ....................................................................................................................................... 34
Table 10 – CPU performance ................................................................................................................................. 35
Table 11 – Mlx16 pre-defined pages ...................................................................................................................... 38
Table 12 – System Protected Ports Overview ........................................................................................................ 40
Table 13 – Standard Ports Overview ...................................................................................................................... 44
Table 14 – Flash Cycles and data retention ............................................................................................................ 46
Table 15 – Flash control port ................................................................................................................................. 47
Table 16 – NVRAM Cycles and data retention ....................................................................................................... 48
Table 17 – NVRAM organization ............................................................................................................................ 49
Table 18 – NVRAM control port ............................................................................................................................. 50
Table 19 – NVRAM status port ............................................................................................................................... 50
Table 20 – CONTROL port....................................................................................................................................... 51
Table 21 – Interrupt inputs .................................................................................................................................... 55
Table 22 – PWM ports – Low Threshold (no Reset) ............................................................................................... 65
Table 23 – PWM ports – High Threshold (no Reset) .............................................................................................. 66
Table 24 – PWM bits – Compare Threshold (no Reset) ......................................................................................... 66
Table 25 – PWM bits – Period value (no Reset) ..................................................................................................... 66
Table 26 – PWM ports – control bits (Reset=00h) ................................................................................................. 67
Table 27 – PWM ports – Prescaler value (no Reset) .............................................................................................. 67
Table 28 – Timer port ............................................................................................................................................. 68
Table 29 – Timer capture output signals. ............................................................................................................... 74
Table 30 – Timer Compare/Capture output signals. .............................................................................................. 76
Table 31 – Control bit for edge selector. ................................................................................................................ 77
Table 32 – Debounce method selection. ................................................................................................................ 79
Table 33 – Timer ports – data port for channel A. ................................................................................................. 80
Table 34 – Timer ports – data port for channel B. ................................................................................................. 80
Table 35 – Timer ports – control port. ................................................................................................................... 81
Table 36 – Timer ports – counter value. ................................................................................................................ 82
Table 37 – Interrupts functions .............................................................................................................................. 83
Table 38 – Memory map of temperature reference values ................................................................................... 85
Table 39 – ADC Interface – ADC Mux, Reference and Trigger source selection .................................................... 87
Table 40 – ADC Interface – Base addresses for results .......................................................................................... 87
Table 41 – ADC interface ports – Control register. ................................................................................................ 88
Table 42 – ADC configuration Register ANA_OUTE................................................................................................ 88
Table 43 – ADC configuration Register ANA_OUTD ............................................................................................... 88
Table 44 – ADC channels selection......................................................................................................................... 89
Table 45 – ADC Hardware trigger selection ........................................................................................................... 90
Table 46 – ADC result format ................................................................................................................................. 90
Table 47 – Accuracy of the HVIODIFFx Input Channel ........................................................................................... 91
Table 48 – ADC conversion time ............................................................................................................................ 91
Table 49 – NVRAM Position of the calibration data for temperature measurement ............................................ 92
Table 50 – Example of WD_DIV and WD_TO setting with Fck=250kHz. ................................................................ 95
Table 51 – Watchdog ports – Tag value. ................................................................................................................ 96
Table 52 – Watchdog ports – Status and Control port. .......................................................................................... 96
Table 53 – Watchdog ports – Time Out value. ....................................................................................................... 96
Table 54 – AWD IO ports ........................................................................................................................................ 98

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Table 55 – HV[x:0] functions overview ................................................................................................................ 103

Table 56 – Port ANA_OUTO ................................................................................................................................. 106
Table 57 – HV Configuration Port 1 - Interrupt config ......................................................................................... 107
Table 58 – HV Configuration Port 2 - HV debounce ............................................................................................. 107
Table 59 – HV Current output control register .................................................................................................... 107
Table 60 – HV Current output control register MLX81115 .................................................................................. 108
Table 61 – HV Current output with HVIBIASSEL=0 ............................................................................................... 108
Table 62 – HV Current output with HVIBIASSEL=1 ............................................................................................... 108
Table 63 – HV Bias Current select register ........................................................................................................... 109
Table 64 – HV Configuration Port 3 - inverted open drain output signal ............................................................. 109
Table 65 – HV Configuration Port 4 - digital or analog mode, RGB monitor measurement ................................ 109
Table 66 – HV Configuration Port 5 - wake up ..................................................................................................... 110
Table 67 – HV Configuration Port 6 - HV IO routing to other blocks .................................................................... 110
Table 68 – HV Status Port ..................................................................................................................................... 110
Table 69 – Test pulses Supply Line ....................................................................................................................... 113
Table 70 – Test pulses LIN .................................................................................................................................... 114
Table 71 – Test pulses signal lines ........................................................................................................................ 114
Table 72 – Test pulses shapes ISO7637-2............................................................................................................. 115
Table 73 – Test pulses shapes ISO7637-3............................................................................................................. 115
Table 74 – Pin description 9 pin mini circular connector of the Mini E-Mlx ........................................................ 121
Table 75 – History record ..................................................................................................................................... 125

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2.3. Abbreviations
ADC Analog Digital converter
API Application Program Interface
ASSP Application Specific Standard Product
CPU Central Processing Unit
CRC Cyclic Redundancy Code
DMA direct memory access
EEPROM Electrically Erasable/Programmable Read-Only Memories
ECC Error Correction Code
ECU Electronic Control Unit (with µ-Controller/µ-Processor)
HV High Voltage Pin
IC Integrated Circuit
ID Identifier
IO Input Output
IP Intellectual Property
LIN Local Interconnect Network
LSB Least Significant Bit
NB Narrow Body
NVRAM Non-Volatile Random-Access Memory (EEPROM with separate RAM)
MCU Microcontroller Unit
MSB Most Significant Bit
OSI Open Systems Interconnection Model
PHY Physical Layer
PWM Pulse Width Modulator
RAM Random Access Memory
ROM Read Only Memory
SBIF Single Bit Interface
SMD Surface Mount Device
SW Switch
TBD To Be Defined

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3. References
Following documents are referred to in this document:

[1] MLX16x8 Data book, Softdist download area

[2] Melexis LIN API documentation, Softdist download area
[3] MLX81115 errata sheet, Softdist download area

This documentation as well as application notes, SW tools, libraries and descriptions is not scope of this
specification and can be found under http://softdist.melexis.com/.
Please contact your Melexis Sales channel for getting access.

[4] LIN consortium, "LIN specification package 2.2A," 2010-12-31.

[5] LIN consortium, "LIN specification package 2.1," 2006-11-24.
[6] LIN consortium, "LIN specification package 2.0," 2003-09-16.
[7] LIN consortium, "LIN specification package 1.3," 2002-12-12.
[8] Automotive Electronics Council, “Stress test qualification standard AEC-Q100,” rev. F2, 2003-07-18.
[9] LIN consortium, “LIN Slave Node Position Detection Implementation Note” rev. 1.0, 2008
[10] Melexis Application note, LIN-AA according Bus Shunt Method (BSM) Slave Node Position Detection
(SNPD)

The descriptions in this document overrule the descriptions in the referred documents.

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4. Technical description
4.1. Package data DFN12 4x4
The chip will be assembled in a 12Pin DFN 4x4 package with wettable flanks.

Please keep in mind that the package has tie bars. Landing pattern recommendations can be requested from
Melexis.

Figure 1 - DFN12 4x4 Package

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4.2. IC Marking
DFN12 4x4

12345 Product Code (81115, 81120)

Silicon Revision
ABC SW Version

XXXXXX Lot Number

yyww Assembly Date Code – week number

Assembly Date Code – Year

1

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4.3. Pin out description

MLX81115
Pin No. Voltage
Pin name Remarks and description
range

2 HV0 IO HV High voltage I/O

4 HV1 IO HV High voltage I/O
5 HV2 IO HV High voltage I/O
12 HV3 IO HV High voltage I/O
11 HV4 IO HV High voltage I/O
10 HV5 IO HV High voltage I/O
3 GND Pwr Ground pin
8 LIN_IN Ana HV Connection to LIN bus, bus shunt Input
7 LIN_OUT Ana HV Bus shunt output
Battery supply voltage; external protection against reverse
1 VS Pwr HV
polarity needed, external blocking capacitors
6, 9 GND Pwr Power Ground
EXP EXP Exposed pad should be connected to Ground
Ana – analogue pin, Pwr – power/supply pin, IO HV – multifunctional pin (configurable pin), HV – high voltage, VBAT or VS related

Package view

Top view of the package DFN12

VS 1 12 HV3
MLX 81115
DFN12 4x4

HV0 2 11 HV4

GND 3 10 HV5

HV1 4 9 GND

HV2 5 8 LIN_IN

GND 6 7 LIN_OUT

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4.4. Electrical characteristics

4.4.1. Absolute maximum ratings
All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings
given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding
any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device.
Reliable operation of the controller is only specified within the limits shown in “Operating conditions”.

Limit Limit
Parameter Symbol Condition Unit
Min Max
t < 5 min -0.3 +28
VS t < 2h - +27
t < 500 ms - +45
ISO 7637-2 pulse 1 [1]
VS.tr1 -100
VS=13.5V, TA=(23 5)°C
Supply voltage ISO 7637-2 pulse 2 [1]
VS.tr2 +75
VS=13.5V, TA=(23 5)°C
ISO 7637-2 pulses 3A, 3B [1]
VS.tr3 -150 +100
VS=13.5V, TA=(23 5)°C
ISO 7637-2 pulses 5b [1] V
VS.tr5 +45
VS=13.5V, TA=(23 5)°C
LIN Bus VLIN T < 500ms -40 +40
ISO 7637-3 pulse 1 [2]
VLIN.tr1 -100
VS=13.5V, TA=(23 5)°C
ISO 7637-2 pulse 2 [2]
VLIN.tr2 +75
VS=13.5V, TA=(23 5)°C
ISO 7637-2 pulses 3A, 3B [2]
VLIN.tr3 -150 +100
VS=13.5V, TA=(23 5)°C
Voltage on HV IOs VIN_HV Pins HV[6:0], -0.3 +45
Maximum latch–up free according to JEDEC JESD78,
ILATCH -250 250 mA
current at any pin AEC-Q100-004
ESD capability of pin VS ESD_VS_IEC According to IEC 61000-4-2 -6 +6
according IEC 61000-4-2 [6]
ESD capability of pin LIN ESD_LIN_IEC According to IEC 61000-4-2 -8 +8
according IEC 61000-4-2 [6] kV

ESD capability of any pin ESD_HBM Human Body Model [4] -2 +2

according AEC-Q100-002
ESD capability of any pin ESD_CDM Charge Device Model [5] -750 +750
according ESD STM5.3.1 V

Storage Temperature Tstg -55 150 °C

Junction Temperature TJ -40 150 °C
JEDEC 2s2p board [3]
Thermal resistance
Rth Junction Ambient (JA) 43 K/W
DFN12 4x4
Table 1 – Absolute maximum ratings

[1] ISO 7637-2 test pulses are applied to VS via a reverse polarity diode and blocking capacitor. Further
information about the test conditions can be found in chapter 22.1.
[2] ISO 7637-3 test pulses are applied to LIN via a coupling capacitance of 1nF. Further information about
the test conditions can be found in chapter 22.1.

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[3] Simulated value for low conductance board (JEDEC).

[4] Equivalent to discharging a 100pF capacitor through a 1.5kΩ resistor conform AEC-Q100-002.
[5] ESD is applied according to joint standard ANSI/ESDA/JEDEC JS-002
[6] ESD performance according to IEC 61000-4-2 (150 pF, 330Ω) has been verified by an external test house.
More details can be found in chapter 22.2

4.4.2. Operating conditions

The IC can have 6 different hardware modes. The exact functionality of these modes depends on the hardware
and software configuration:

 Reset:
o Triggered by hardware. When VS or VDDA or VDDD drop below a critical level, the complete
chip is powered down.
o The analogue and digital supply regulators are disabled. No functionality is available in this
mode.
 Normal mode. Main application running
o Microcontroller fully functional
o Analogue fully functional
 Low power mode (managed via firmware). Digital part running at lower frequency (250kHz)
o Microcontroller fully functional
o LIN not possible
o Analogue fully functional
 Under voltage: triggered by the hardware under voltage detection interrupt (EXT4_IT: UV_VS, see
chapter 7.8 Supply voltage VS over and under voltage detection).
o Microcontroller fully functional.
o Power down behaviour can be managed via software.
o Reduced current capability on HVx below VS=5.5V.
 Over voltage: triggered by the hardware over voltage detection interrupt (EXT4_IT: OV_VS, see chapter
7.8 Supply voltage VS over and under voltage detection).
o Microcontroller fully functional
o Behaviour can be managed via software.
 Sleep Mode: Triggered by the software.
o Microcontroller powered down
o Digital and analogue supply powered down.
o Sleep Mode and wake-up functionality running on help supply Vaux

Limit
Parameter Symbol Conditions Unit
Min Typ Max
Supply Voltage Range VS 5.5 18 V
Ambient Temperature TA -40 125 °C
Table 2 – Operating conditions

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4.4.3. Electrical parameter specification

Following characteristics are valid over the full temperature range of TA = -40°C to +125°C and a supply range of
5.5V ≥ VS ≤ 18V unless otherwise noted.
If several pins are charged with transients above VS and below GND, the summary of all substrate currents of
the influenced pins should not exceed 10mA for correct work of the device.
All voltages refer to ground of IC, which is built by short of all existing ground pins, which were split to meet
EMC performance and lowest possible noise influence.

Limits
Parameter Symbol Conditions Unit
Min Typ Max
Global parameters
Normal working all pins are inputs, IC is trimmed,
Inom 6 10 mA
current no DC loads
all pins are inputs, chip in SLEEP
MODE;
SLEEP MODE VS=14V, TA=27°C 28 µA
Isleep
current VS=18V, TA=85°C 38 µA

Frequencies
Tolerance of RC
frc_24M fRC=24MHz -5 +5 %
oscillator
Frequency separate
10kHz RC oscillator
frc_10k 5 10 20 kHz
for the analogue
Watchdog
Temperature
frc_
dependency of the ∆frc_10k/∆T -10% 10%
10k
10kHz RC oscillator
Startup time of the Not tested in production; for
system after Power tstartup_POR information only; time until 500 s
On internal dig reset is inactive
Startup time of the
Not tested in production; for
system after
tstartup_SLEEP information only; time until 250 s
Release of SLEEP
internal dig reset is inactive
MODE
POR parameters (VS based; for information only)
POR off Vpor_lh only for information 3.6 V
POR on Vpor_hl only for information 3.15 V
Vhyst_por
Hysteresis for POR only for information 250 mV

VS – Programmable under voltage interrupt parameters

PRUV (ANA_OUTG[9:8])
00
Programmable 5.5 6 6.5
01
range for under Vuv_range_vs 6.5 7 7.5
10
voltage level 7.5 8 8.5 V
11
8.5 9 9.5
(See Table 63)
Hysteresis for under
Vhyst_uv_vs 0.1 1 V
voltage
Debouncing for
tuv_vs 10 30 60 µs
under voltage only for information
VS – Over Voltage (Load dump) interrupt related parameters

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Level for load dump

Vldh 29 31 33 V
interrupt
Hysteresis for load
Vhyst_ld 1 2 3 V
dump interrupt
Debouncing for load
tld only for information 50 100 s
dump interrupt
ADC (10Bit) related parameters
VRH3 ADC_REF[1:0]=11 2.46 2.5 2.53 V
VRH2 ADC_REF[1:0]=10 1.47 1.5 1.53 V
Reference voltage
VRH1 ADC_REF[1:0]=01 0.73 0.75 0.77 V
high
ADC_REF[1:0]=00
VRH0 0 V
ADC reference disabled
Differential only characterized; no
DNL -1 +1 LSB
nonlinearity production test
only characterized; no
Integral nonlinearity INL -3 +3 LSB
production test
Quantization steps RESADC 1024 LSB
Quantification error ADCERR -0.5 +0.5 LSB
Minimum for max ADC input
Tconv 6 s
conversion Time frequency = 2MHz
Multi purpose High voltage IOs
Common parameters
Leakage current in
IleakHV -5 5 A
case HVIOs
RGB leakage
See Chapter 20.2 50 62 96 kΩ
compensation
Port HVxDEB[1:0]
00 (default)
Programmable 0
01
Debounce time for tdebHV 1 ms
10
HVs 4
11
8
(See Table 58)
ADC input divider 300 kΩ
Digital Input for WAKE UP (VAUX supplied)
Digital WU input Active in SLEEP MODE
V
threshold level Vinlh_wuHV 2.4
L => H
Digital WU input Active in SLEEP MODE
threshold level Vinhl_wuHV 1.2 V
H => L
Hysteresis Vhyst_wuHV 0.1 V
Fast Digital Input; (not active in SLEEP MODE)
Fast Digital Input
V
threshold level VinlhHV 2.4
L => H
Fast Digital Input
1.0
threshold level VinhlHV V
H => L
Hysteresis VhystHV 0.1 V
For rising and falling edge;
Max. delay dmaxHV For information only, not tested 25 ns
in production
Open Drain switch

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ON – resistance VS>5.3V
VoutlHV 20 40 Ω
HVOUT ANA_OUTF[15:0] = 0
Open Drain constant current source
Output current VS>5.3V
IoutlHV 3 30 mA
HVOUT ANA_OUTG[2] = 0
Output current
3 mA
HVOUT stepsize
Output current VS>6V
IoutlHV 36 48 mA
HVOUT ANA_OUTG[2] = 1
Output current
6 mA
HVOUT stepsize
6V≤ VS ≤18V
Output current
[1] TA = 35°C ±7 %
HVOUT relative IoutlHV_err
3mA≤ Iout ≤30mA
error

Temperature
TC_Iout -0.025 %/K
coefficient
Current for RGB monitor
HVENFCMx = 1
Monitor current I_mon 0 2 mA
(Register page Table 65)
Output voltage
I_mon_voutswing VS-4 VS V
swing
Relative current TA = 25°C
I_mon_relcurerr 1 %
error (<100us) TC saved in NVRAM
[1]
S&H settling time I_mon_SHsettl 5 10 us
[1]
Output current INL I_mon_inl 1 %
Absolute Output [1]
I_mon_ageerr 1 %
current aging error
Differential Amplifier for RGB monitor
Monitor Input VS≥ 8.5V V
VIN_mon VS- 3.7 VS-1.5
Voltage Range
Diagnosis Input
VIN_diag VS≥ 8.5V VS- 4 VS V
Voltage Range
VRH3-
Output Voltage Internal output range of sense VRH3
VOUT 0 VIN*0. V
Range amplifier (ADC)
2
Output Voltage VIN_mon 2 %
VOUT_err
relative error VIN_diag 5 %
Gain GAIN 0.2
Wake up related parameters
Wake up filter time SLEEP MODE, HVx rising &
tWU 25 50 s
pins HVx falling edge
Time for dominant level after
Wake up filter time
tWU_LIN SLEEP MODE 30 150 s
pin LIN
Temperature Sensor related parameters
Temperature Shutdown circuit
Tot_on 160 170 180 C
Over temperature tested by special test mode only
Tot_off 130 140 150 C
shutdown
Tot_hyst [1] 10 C
Temperature Sensor (for ADC measurement)
Temperature range Trange For information only -40 150 C
Accuracy Tacc For information only -10 10 C

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Shunt resistance amplifier (HV4 and HV5)

VIN_differential 0 250
Input voltage range mV
VIN_abs 0 800
Output voltage Internal output range of sense
VOUT [1] VOFF 0 2.5 V
range amplifier
Amplifier output
VOFF Gain=10 10 250 700 mV
within input is zero
Input Offset voltage
1 2 mV
for Sense amplifier
Gain GAIN T=25°C 9.8 10 10.2
ppm/
Gain drift GAINDRF [1] 150
K
8-Bit DAC for overcurrent threshold
Reference voltage
VREF 2.5 V
high
Differential
DNL -1 +1 LSB
nonlinearity
Settling time Tsetling_DAC8 [1] 10 µs
Table 3 – Electrical parameter specification
[1]
Guaranteed by design & characterization, not tested in production

Limits
Parameter Symbol Conditions Unit
Min Typ Max
VDDA related parameters
3.3V supply information parameter,
VDDA 3.2 3.3 3.4 V
voltage range (DC) with trimmed VBG
Internal current
Iddint_VDDA Only for information 10 mA
capability
V1V8 related parameters
1.8V supply
V1V8 with trimmed VBG 1.77 1.85 1.93 V
voltage range
Internal current
Iddint_VDDD Only for information 10 mA
capability
V5V6 related parameters
5.6 supply voltage
V5V6 with trimmed VBG 5.69 5.75 5.81 V
range
current capability Iddint_V5V6 Only for information 2 mA
VDDA based UV RESET parameters
Undervoltage
Vuvr_hl_VDDA information parameter 2.7 2.85 3 V
reset on
Undervoltage
Vuvr_lh_VDDA information parameter 2.85 3 3.15 V
reset off
Vhyst_uvr_VDD
Hysteresis for
A [1] 0.1 V
undervoltage reset

Debouncing for
tuvr_VDDA information parameter 1 3 10 s
UVR
VDDD based UV RESET parameters
Undervoltage
Vuvr_hl_VDDD information parameter 1.525 1.6 1.675 V
reset on
Undervoltage
Vuvr_lh_VDDD information parameter 1.6 1.675 1.75 V
reset off

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Vhyst_uvr_VDD
Hysteresis for
D information parameter, [1] 0.05 V
undervoltage reset

Debouncing for
tuvr_VDDD information parameter 1 3 10 s
UVR
Table 4 – Electrical information parameters specification
[1]
Guaranteed by design & characterization, not tested in production

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LIN related parameters (adapted from Lin spec rev. 2.x)

Limit
Parameter Symbol Conditions Unit
Min Typ Max
Pin LIN_IN
Transmitter
Short circuit bus VBUS = VBAT, driver
IBUS_LIM 40 200 mA
current on
Pull up resistance bus,
normal & standby RSLAVE (LIN_IN) VS=8V to 18V 28 30 40 kOhm
mode LIN_IN

Pull up current, ILIN_PU-Sleep VBUS=0, VBAT=12V,

-100 µA
SLEEP MODE SLEEP MODE
Input Leakage at the VBUS=0, VBAT=12V -1
IBUS_PAS_dom mA
receiver incl. PU
driver off,
Bus reverse current, 8V<VBAT<18V,
IBUS_PAS_rec 20 A
recessive 8V<VBUS<18V,
VBUS > VBAT
VS = 0V, 0V < VBUS <
Bus reverse current 18V
IBUS_NO_BAT 23 A
loss of battery LIN 2.1

VS = VGND=12V,
Bus current during 0 < VBUS < 18V
IBUS_NO_GND
loss of ground J2602 -100 100
µA

Transmitter network load =500Ω /

VolBUS 0 0.2 VS
dominant voltage TxDx = 0
Transmitter
VohBUS TxDx open 0.8 1 VS
recessive voltage
BUS input
Pulse response via
capacitance;
CBUS 10k, VPULSE = 12V, 25 35 pF
MLX Value for LIN
VS open
conformance test
Receiver
Receiver dominant
VBUSdom 0.4 VS
voltage
Receiver recessive
VBUSrec 0.6 VS
voltage
VBUS_CNT=(
Centre point of
VBUS_CNT VBUSdom+ VBUSrec 0.475 0.5 0.525 VS
receiver threshold
)/2
VBUS_CNT =( VBUSrec
Receiver Hysteresis VBUS_hys 0.175 VS
- VBUSdom)
AC Parameters
Propagation delay CRxD =25pF
trx_pdf 6 s
receiver [1], [2], [5] falling edge
Propagation delay CRxD =25pF
trx_pdr 6 s
receiver [1], [2], [5] rising edge
Prop. delay receiver
trx_sym trx_pdf - trx_pdr -2 2 s
symmetry [5]
Receiver debounce trec_deb LIN rising & falling 0.5 4 s

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time [6] edge

20kbps operation ,
LIN duty cycle 1 [2] [3] D1 0.396 -
normal mode
20kbps operation ,
LIN duty cycle 2 [2] [3] D2 0.581 -
normal mode
10.4kbs operation ,
LIN duty cycle 3 [2] [3] D3 0.417 -
low speed mode
10.4kbs operation ,
LIN duty cycle 4 [2] [3] D4 0.590 -
low speed mode
trec(max) – 10.4kbs operation ,
Δt3 15.9 s
tdom(min) [4] low speed mode
trec(min) – 10.4kbs operation ,
Δt4 17.28 s
tdom(max) [4] low speed mode
TxD dominant time normal mode, VTxD =
tTxD_to 64 ms
out [7] 0V

LIN auto-configuration LIN_IN/LIN_OUT

Functional range LIN
VS 9 - 15 V
auto-addressing
LIN slave pull up
RLIN,SLAVE 27.66 - 40 kΩ
resistance
Bus pull-up source 1
VS,MAX / VS,MIN /
for auto-addressing VBUS=0V … 2.5V
IPU,AA,PRE,1 RLIN,SLAVE, - RLIN,SLAV mA
PRE-Selection Phase VS > VBUS + 6V
MIN E,MAX
(OPTION1)
Bus pull-up source 2
VBUS=0V … 2.5V
for auto-addressing IPU,AA,SEL 2.26 - 1.84 mA
VS > VBUS + 6V
Selection Phase
BUS voltage range VBUS 0 - 2.5 V
PRE-Selection phase
ITH_PRE 1.2 mA
current threshold
Selection phase
ITH_SEL 1.2 mA
current threshold
LIN shunt resistor Rshunt (internal) 0.61 0.78 0.96 
Table 5 – LIN related parameters

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Shunt differential amplifier

LIN AA Common
SA_CMIR < -0.2 1.6 > +2.5 V
mode input range
[7]
DC closed loop gain SA_GAIN trimmable, step size 40 -40 -120 -160
Settling time SA_SETTLE 10 20 us
[6]
0.1% error hold time SA_HOLD 680 us
Voltage reference SA_VREF 1.8 2 2.2 V
VDDA-
Output Voltage SA_VOUT 0.2 V
0.2
[7]
LIN AA current SA_ILIN 0 40 mA
Table 6 – RGB monitoring parameters

[1] This parameter is tested by applying a square wave signal to the LIN. The access to internal signals
RxD,TxD will be performed by test mode. The minimum slew rate for the LIN rising and falling edges is
50V/us.
[2] See Figure 2: LIN timing diagram
[3] Standard loads for duty cycle measurements are 1KΩ/1nF, 660Ω/6.8nF, 500Ω/10nF, internal termination
disabled
[4] In accordance to SAE J2602
[5] Parameter in relation to internal signal TxD
[6] Guaranteed by design & characterization, not measured in production
[7] Trim value saved in NVRAM

As shown in figure, both worst case duty cycles can

be calculated as follows :
Dwc1 = tBUS_rec(min) / 2 * tBit
Dwc2 = tBUS_rec(max) / 2 * tBit
Thresholds for duty cycle calculation in accordance
to LIN2.x:

Baud rate 20kBaud 10.4kBaud

tBit 50µs 96µs
Dwc1 D1 D3
Dwc2 D2 D4
THREC(MAX) 0.744 VS_TX 0.778 VS_TX
THDOM(MAX) 0.581 VS_TX 0.616 VS_TX
THREC(MIN) 0.422 VS_TX 0.389 VS_TX
THDOM(MIN) 0.284 VS_TX 0.251 VS_TX
Figure 2 – LIN timing diagram: Relation between propagation delay and duty cycle

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5. Typical application examples

The following section shows typical application examples. Please refer to additional Melexis application notes
for more details. The signal order in all application diagrams does not reflect any pin order of the device
(therefore see chapter 4.3 if needed). The following application diagrams are only principle examples, showing
how the controller could be embedded into a system. Detailed application data must be worked out by
customers to meet the needs of their dedicated application.

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5.1. Application Example MLX81115

VS

VBat HV0
0 ... 48mA
VS VS

Optional
component
HV1
0 ... 48mA
VS

MLX81115
HV2
0 ... 48mA

VS

HV3
0 ... 48mA

Optional components VS

LIN_IN

LIN_OUT HV4
0 ... 48mA

VS

EXP
GND HV5
0 ... 48mA

Figure 3 – Application schematic sample

MLX81115 offers more flexibility due to the higher pin count making 3 additional HV pins available. They can be
used to drive a second RGB-LED.

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6. Block diagram

VS Power Supply VDDD

VDDA
ADCx
UVLO
Aux Supply +
INTx WakeUp Logic POR / AWD
HV0 HVDIN
HVINEN WakeUp LIN
HV1
HVDOUTB
PWMx Out
WakeUp HVx
HV2
LIN Dig TX
HV3 0 ... 48mA

HV4
HV5
ADCx ... ADCVS
...
PWM5 ... 0

...

ADC 16-bit
Divider Test/Debug
GND
and Mux
PWM Interface
INT LIN Autoconfig

LIN _OUT
RC-Osc.
10-bit ADC to ADC MUX

Window LIN_IN
WD LIN LIN
MCU-Core Controller PHY
Timer
16kByte 2048byte 512byte
32kByte Flash
ROM RAM NVRAM

Figure 4 – Block Diagram

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7. System behavior description

The following chapter describes the behavior of the controller under normal and special conditions.
At first, entering and leaving RESET or force system to enter SLEEP after configuring WAKE UP sources has to be
done carefully by API.
Initialization of the system as well as saving any needed data later to memory is the precondition to keep
application running correctly.

7.1. The supply system

A set of different supplies deliver voltage to various parts of the system. The following section describes how
different supplies are used.

 Battery voltage VBAT and IC supply voltage VS

The car battery voltage VBAT is connected via the Reverse Polarity Diode to the IC Supply voltage VS.

To guarantee a certain remaining charge for finalize the writing process of the non-volatile memory, in case of
an VBAT drop, the capacitor value on VS has to be calculated depending on the current consumption of the
complete module.

A second smaller value ceramic capacitor is needed to stabilize VS for emission reasons, to ensure a stable
application in case of negative transients.

 SLEEP MODE supply VAUX

This internal voltage supplies those blocks of the controller, which are basically used to control the main
supplies (VDDA and VDDD), SLEEP MODE, RESET etc. VAUX is always active as long as enough voltage on VS is
available. Any blocks needed in SLEEP MODE are supplied by this voltage.

 Analogue Supply VDDA

This voltage supplies the analogue part of the controller. It is switched off during SLEEP MODE.

 Digital Supply VDDD

This voltage supplies the digital part of the controller. It is switched off during SLEEP MODE.

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7.2. Power On
The following block diagram shows an overview over the different Power supplies and the reset circuits:

VS

VDD VDD VDD

Regulator Regulator Regulator

VAUX OUT VDDA OUT VDDD OUT
( 2 … 3.6V) (3.3V) (1.85V)

TRIMVDDA TRIMVDDD

VDD VDD
VDD UV_ VDDA UV_ VDDD
POR
Bandgap VBG
IN VLH:3.6V OUT OUT OUT
(1.2xV) OUT IN VLH:3V IN VLH:1. 675V
VHL:3.15V VHL:1.6V
VHL:2.85V
TRIMBGP

UV_ VDDD
UV_ VDDA MRB
POR

Figure 5 – Supply and Under voltage concept

After connecting power to VS pin (assuming any needed external components are applied correctly) the system
will start to work. The on-chip supplies start to build the system voltages after reaching the defined minimum
voltage level on VS pin.
The MRB (for Master Reset, low active) is a digital signal which keeps the complete IC in reset state, as long as
one of the supplies is below the specified value.
MRB is active after Power On VS under the following condition
 as long as VS stays below its POR level (Vpor_lh) or
 as long as VDDA stays below its Under voltage reset level (Vuvr_lh_VDDA) or
 as long as VDDD stays below its Under voltage reset level (Vuvr_lh_VDDD).

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VS

VDDA
Vuvr_lh_VDDA
VAUX
Vpor_lh
VDDD
Vuvr_lh_VDDD

t
tdelay

EN_REG

PORB

UVB_VDDD

UVB_VDDA

MRB

Figure 6 – Signal behavior during Power On

With rising edge PORB after VS ramping up, the bandgap and the under voltage detection circuits for VDDA and
VDDD are switched on. After a built in delay time (tdelay) of typ.150us the bandgap has reached the valid
voltage level and the regulators for VDDA and VDDD are switched on. If VDDA and VDDD are above the under
voltage levels the Master Reset is switched off (MRB=1) and the system starts to work.

7.3. Power Off

When VDDA or VDDD are below their under voltage levels MRB is set active which disables all functions of the
chip.
If VS drops below its POR level, it will disable the VDDA and VDDD regulator and set the MRB active.

In case of application relevant data has been changed in the RAM area of the NVRAM and the power supply is
going down, API has to start as soon as possible saving values into NVRAM.
The available time for this save operation is limited by the energy of the external Capacitor at VS.

Note that incomplete save operations can leave invalid data in the NVRAM.

Saving data in NVRAM can be triggered by the under voltage interrupt or by measuring VS with the ADC.

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7.4. System initialization and Trimming

For correct system startup some analogue registers in the IO part will be restored after every RESET or WAKE
UP by writing with values taken from the non volatile memory. This will be handled by the Software Platform.
The customer don’t need to take care about it.

These values have been stored during Melexis chip test. The defined addresses are reserved for Melexis and it is
not allowed to be changed by API.

Startup steps:
1. Trimming FLASH (VREF, VMG)
2. Trimming Bandgap
3. Trimming VDDA supply voltage
4. Trimming VDDD supply voltage
5. Trimming Biasing current
6. Trimming RC Oscillator
7. Trimming ADC Reference voltages VRH1..3
8. Trimming NVRAM charge pump

7.5. Entering SLEEP MODE (GO TO SLEEP MODE = GTSM)

The SLEEP MODE of the controller is enabled by a write to a special port location. This mode is used to save
power by switching off any not needed function, keeping only some minimum parts alive, which will watch
events or conditions for possible WAKE UP requests.

To enter SLEEP MODE the following sequence has to be performed:

 Stop running ADC measurement

 Disable interrupt generation by using MASK register. For more details see chapter “11.3.1 Interrupt
enabling and masking”.
o External interrupts: Timer 16bit, PWM, HV as input
o Internal interrupts: Timer 15bit
 Save important RAM register content to the NVRAM
 Wait for NVRAM write access is finished
 If needed:
o configure HVs as wake up source
o configure local WAKE UP timer

A wakeup over LIN can’t be disabled.

The API starts the system shutdown process by stopping the communication and application CPU
(M4_RB=0 and HALT=1 set GTSM high).

Note that the system shutdown cannot be interrupted by any wake-up mechanism as long as the process has
not been completed.

With rising edge of GTSM the following sequence is started:

 GTSM is filtered, must be >50us high
 Internal GTSM pulse is generated
 Bandgap (VBG), undervoltage detection circuits and regulators for VDDA and VDDD are switched off.
 System is in SLEEP MODE
 WAKE UP is possible by LIN, HV-pins and internal wakeup timer.

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7.6. WAKE UP from SLEEP MODE

Before sending SLEEP MODE request API has to ensure, that in minimum one WAKE UP source is enabled,
otherwise only LIN activity or POR via VS can restart from SLEEP MODE.
After WAKE UP the software starts identically as after power on.
The source of the WAKE UP can be read from the analogue input port.

There are 3 different sources for a WAKE UP:

1. After a falling edge on the LIN bus followed by a dominant voltage level for longer than the specified
value (twu_LIN) and a rising edge on pin LIN it will cause a wake up. If the Sleep mode was initiated by
a short on the LIN (failure), and the short was removed afterwards, the LIN wakes up immediately by
the next rising edge. The integrated filter suppresses a WAKE UP via EMC interferences.
2. a local WAKE UP condition by detecting a falling or rising edge on HVx pins exceeding the input
comparator thresholds and the local WAKE UP debouncing time of tWU_HV
3. The configurable internal WAKE UP timer. It is possible to configure three different wake-up times. To
configure the wake-up time the bits WUI[1:0] in the ANA_OUTG register have to be set correctly.
Please refer to Table 63.

The wakeup source, causes the wakeup, will be signalized via the ANA_INB port (see Table 7).

IO port: ANA_INB
Address: 0x281E Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
- - - - - - - -
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
INTERNAL_
- - - - - LOCAL_WU LIN_WU
WU
LIN_WU Wakeup was caused by a wakeup via LIN request (=1)
LOCAL_WU Wakeup was caused by a falling or rising edge on HVx pins (=1)
INTERNAL_WU Wakeup was caused by the internal WAKE UP timer (=1)
Table 7 – Wakeup Source

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Vuvr_ lh _ VDDD and Vuvr_ lh_ VDDA

VDDA
VAUX
VDDD
VBG

WAKEUP
MRB
VBG _ ON ,
UV det . on

VDDA _ ON

VDDD _ ON

GTSM

Figure 7 – Signal behavior to and from SLEEP MODE

7.7. System behavior in case of different under voltage

conditions
The following table shows an overview, how the controller behaves, if the different voltages have the following
values:

VS VDDA VDDD System behavior

VS> 5.5V > Vuvr_hl_VDDA > Vuvr_hl_VDDD Normal working range
Under Voltage
Digital part fully functional.
3.9 ≤ VS < 5.5 V Current consumption on VDDA should
> Vuvr_hl_VDDA > Vuvr_hl_VDDD
be limited by software.
Analogue parameters cannot be
guaranteed.
Reset: MRB=Low; VAUX is still on;
≥ 3.9 V ≤ Vuvr_hl_VDDA X analogue and digital parts are in reset
State
Reset: MRB=Low; VAUX is still on;
≥ 3.9 V X ≤ Vuvr_hl_VDDD analogue and digital parts are in reset
State
VDDA and VDDD levels not
VS < 3.9
X X guaranteed.
Chip function cannot be guaranteed.
Table 8 – System behavior in different UV conditions

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7.8. Supply voltage VS over and under voltage detection

The over voltage and under voltage detection circuits are based on the same principle. The supply voltage VS is
divided internally and compared to the reference voltage of an internal bandgap supply (VBG). In Sleep Mode
the input voltage dividers and the comparators are disabled.
VS is connected through the analogue input ports to custom interrupt sources, see the “External Interrupts”
chapter for further detail.

VS
VDDA VDDA VDDD

Interrupt
OV_VS
comp FILTER Level Shifter
VBG

SBY

VS
VDDA VDDA VDDD

ANA_OUTG[9:8]
Interrupt
UV_VS
comp FILTER Level Shifter
VBG

SBY

Figure 8 – block diagram over- and under-voltage detection

The VS under voltage detection threshold can be programmed with ANA_OUTG[9:8] = PRUV[1:0] from 6V to 9V,
further information can be found in Table 63 and in the chapter Electrical parameter specification.

In the Software Platform C-macros are available to enable the over- and under-voltage detection.

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7.9. Enter the Low Power Mode

In this mode the system clock will be switched to 250kHz reducing the controller current consumption. This can
be done via the PLL_EN bit in the RC_CTRL port (Table 9).

Following limitations have to be taken into account:

 LIN communication is not possible
 PWM frequency will be reduced
 ADC sampling time will be increased
 15bit- and 16bit-timer will run slower
 The number of operations between the watchdog acknowledges must be reduced.

IO port: RC_CTRL
Address: 203Eh Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Melexis reserved RC_EN
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
Melexis reserved
Melexis reserved Write access is not allowed
1 – Enable 24MHz clock
RC_EN 0 – Enable 250kHz clock
(read- and writeable)
Table 9 – RC-Control port

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8. CPU core MULAN3 – MULtiple CPU with

Analogue and Network support
The controller is designed with the Melexis 4 Bit / 16-Bit-RISC-CPU MULAN3.
For more information regarding the MULAN3 (CPU architecture, instruction set, register set, addressing modes
etc.) see the mentioned documentation at the beginning of this specification. The MULAN3 core has co-
processor for fast multiplication and division of 32bit values (for further information see [1]).

8.1. MULAN3 compared to MULAN2

The MULAN3 core is functional 100% compatible to the MULAN2.

The differences are in memory organization and interrupt vectors for the system level interrupts, i.e.
 MULAN3 adds 16kByte ROM.
o The power up code and the SW for the LIN-CPU (MLX4) is executed from ROM.
o The ROM contains a boot loader supporting flash reprogramming over LIN
 the ROM will be located at addresses 0xC000h to 0xFFFF
o 8kByte is used by MLX4 (0xC000 to 0xDFFF)
o 8kByte by MLX16 (0xE000 to 0xFFFF)
 MULAN3 will include a BIST block for testing the ROM
 the far page 6 (FP6) will be pointing into ROM at address 0xFF00h
 MULAN3 redirects all level 0 interrupts (Reset, Stack, Protection Error, Invalid Address, Program Error)
into ROM (to FP6)
 MULAN3 changes the interrupt type of Protection error, Invalid Address Error and Program Error (=
flash error) type to JUMP (instead of CALL)
 port bits are added to control the relocation of MLX4 code from ROM to FLASH (in CONTROL_EXT2
port)
 port bits are added to determine the access priority for reading the ROM from MLX4 or MLX16 (in
CONTROL_EXT2 port)

8.2. MULAN3 CPU Performance

The system clock of the controller is derived from the 24 MHz RC Oscillator.

Exempted the debouncing times for some WAKE UP sources from standby mode and the analogue watchdog,
all timings are derived from this system clock.
If not mentioned explicitly, this MULAN3 main system clock is referred to as CK in the following documentation.

This gives the following instruction length, in case the oscillator is running on its typical frequency.

Typical 24 MHz clock

Instruction length Typically 4+1 clock periods
Calculation power <= 4.8 MIPS
Table 10 – CPU performance

8.3. Math Co-Processor

The MULAN3 core has co-processor for fast multiplication and division of 32 bit values (for further information
see [1]).

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8.4. CPU Architecture

Custom digital and analog

System
Clock

RB
Test
controller
Mlx16 Mlx4
periphery periphery

Mulan3

Interrupt CPUs
Mlx16-(X)8 Mlx4
controller interface

ROM
RAM
Flash
arbiter
Arbiter

EEPROM ROM
RAM
NVRAM Flash

Mlx4 - Mlx16 shared resources

Figure 9 – CPU architecture

This architecture has been selected for the following reasons:

 separation of protocol load from application software load by 2 processors
 keeping the protocol adaptable to different revision by software solution
 protocol safety is implemented, the risk to crash the communication by a software error in the
application software is minimized
 full CPU power of the MLX16X8 for application
 Flash programming

8.5. CPU Address space

Mlx4 and Mlx16 share a common ROM and RAM. From the 2 CPUs a unified 16 bit bus is created (Von Neumann
architecture). On this bus are hooked the ROM/Flash, the RAM, the NVRAM and the Mlx16-(x)8 peripherals.
Two arbiters are in charge of creating a unique memory address and corresponding access signals for
ROM/Flash and RAM.

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Notes:
 The Mlx4 ports are on a separate bus, so there is no need for a port arbiter.
 The NVRAM is only accessed by the Mlx16, so it does not need an arbiter.

8.6. Memory mapping

The unified 16 bit bus is accessing devices as shown on Figure 10.

Mlx16-(x)8
Allowed

System Write
User Write
Memory space

Fetch
F000 - FFFF 16kByte Mlx16 User Library
E000 - EFFF ROM Mlx16 LIN loader
D000 - DFFF ROM Mlx4 code
C000 - CFFF ROM Mlx4 code
7000 - BFFF 32kByte Mlx16 code
6000 - 6FFF FLASH Mlx16 code
5000 - 5FFF FLASH Mlx16 code
4000 - 4FFF FLASH Mlx16 code
3000 - 3FFF Not Used
2800 - 2FFF Mlx16 User ports 2kByte
2000 - 27FF Mlx16 System Ports 2kByte
1200 - 1FFF Not used
1180 - 11FF NVRAM Melexis Area 128 Byte (2)
1100 - 117F NVRAM / NVRAM 128 Byte (2)
1080 - 10FF NVRAM Melexis Data 128 Byte (2)
1000 - 107F NVRAM / NVRAM 128 Byte (2)
0800 - 0FFF Not used (1)
0000 - 07FF RAM (1) RAM: 2048 Byte (1)

(1): See RAM sharing for Mlx4-Mlx16 distribution and protection

(2): Fetch enabled in this area for patch codes
Figure 10 – Memory mapping

There are some restrictions for accessing certain areas depending on the type of access:

 Mlx4 can fetch anywhere from physical addresses 0xC000 to 0xDFFF (12 bits word address)
 Mlx16 can on fetch in:
o FLASH: Normal case
o ROM
o NVRAM: Patch-code
o RAM
 Mlx4 and Mlx16 can read any RAM location (limited to 256 bytes for Mlx4)

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The predefined pages of the Mlx16X8 are encoded as given below.

32K
Name Flash Note
size
2)
Fp0: BF00 Last FLASH / ROM page (used by interrupt controller)
2)
Fp1: BE00 Could be used for C runtime
2)
Fp2: BD00 Could be used for C runtime
2)
Fp3: BC00 Could be used for C runtime
2)
Fp4: BB00 Could be used for C runtime
2)
Fp5: BA00 Could be used for C runtime
2)
Fp6: FF00 Could be used for C runtime
Fp7: 1000 In NVRAM to allow single instruction patch start
1) Mlx16 private RAM;
Dp: 0000
16 byte shared between MLX4 and MLX16
1)
Io: 2800 User Ports
Legend:
1) Fixed address for any FLASH / ROM size
2) Address depending on the FLASH / ROM size
Table 11 – Mlx16 pre-defined pages

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9. IO Registers
9.1. General
There are 2 port spaces for the Mlx16:
 System protected ports (starting at address 0x2000), Mlx16 bit USER must be cleared.
 User ports (starting at address 0x2800), not protected.

Writing to non-existing custom ports will have no effect and reading from non-existent custom ports will always
return 0.

9.2. System Protected ports

Table 12 shows the available system ports. All of these ports are system protected, meaning they are only
accessible with bit USER=0.

Access
Name Address Description Page
Mode
0x2057
0x2056
0x2055
0x2054
0x2053
0x2052
0x2051
0x2050
0x204F
ANA_OUTF 0x204E HV current output control register 107
0x204D
ANA_OUTE 0x204C Analog chip ports - ADCREF trimming 88
0x204B
ANA_OUTD 0x204A Analog chip ports - ADCREF trimming 88
0x2049
0x2048
0x2047
0x2046
0x2045
0x2044
0x2043
LIN_XKEY 0x2042 Word/Byte Enables LINXCFG port
0x2041
0x2040
0x203F
RC_CTRL 0x203E Word/Byte RC control 34
0x203D
Second level interrupt controller – over-temperature,
XI4_PEND 0x203C 57
overvoltage …
0x203B
XI3_PEND 0x203A Word/Byte Second level interrupt controller 57
0x2039
XI2_PEND 0x2038 Word/Byte Second level interrupt controller – PWM unit 57
0x2037
XI1_PEND 0x2036 Word/Byte Second level interrupt controller – Timer2 unit 57
0x2035
XI0_PEND 0x2034 Word/Byte Second level interrupt controller – Timer1, 3 unit 57
0x2033
Second level interrupt controller – over-temperature,
XI4_MASK 0x2032 Word/Byte 57
overvoltage …

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Access
Name Address Description Page
Mode
0x2031
XI3_MASK 0x2030 Word/Byte Second level interrupt controller 57
0x202F
XI2_MASK 0x202E Word/Byte Second level interrupt controller - PWM unit 57
0x202D
XI1_MASK 0x202C Word/Byte Second level interrupt controller – Timer2 unit 57
0x202B
XI0_MASK 0x202A Word/Byte Second level interrupt controller – Timer1, 3 unit 57
CK_TRIM 0x2029 Byte Melexis reserved
FL_CTRL1 0x2028 Word/Byte Flash control register
0x2027
FL_CTRL0 0x2026 Word/Byte Flash control register 47
0x2025
NV_CTRL 0x2024 Word/Byte NVRAM Control register 50
0x2023
ANA_TEST 0x2022 Word/Byte Melexis reserved
0x2021
ANA_OUTC 0x2020 Word/Byte Melexis trim register
0x201F
ANA_OUTB 0x201E Word/Byte Melexis trim register
0x201D
ANA_OUTA 0x201C Word/Byte Melexis trim register
0x201B
PATCH3_A 0x201A Word/Byte 4th Patch start address
0x2019
PATCH2_A 0x2018 Word/Byte 3rd Patch start address
0x2017
PATCH1_A 0x2016 Word/Byte 2nd Patch start address
0x2015
PATCH0_A 0x2014 Word/Byte 1st Patch start address
0x2013
PATCH3_I 0x2012 Word/Byte 4th Patch jump instruction
0x2011
PATCH2_I 0x2010 Word/Byte 3rd Patch jump instruction
0x200F
PATCH1_I 0x200E Word/Byte 2nd Patch jump instruction
0x200D
PATCH0_I 0x200C Word/Byte 1st Patch jump instruction
SLVIT 0x200B Melexis reserved
SLVCMD 0x200A Word/Byte Melexis reserved
0x2009
PEND 0x2008 Word/Byte Pending interrupt flags
0x2007
MASK 0x2006 Word/Byte Interrupt mask 55
0x2005
PRIO 0x2004 Word/Byte Interrupt priority
SHRAM_H 0x2003 Byte Mlx4 private RAM start address
SHRAM_L 0x2002 Word/Byte Max number of bytes writable by Mlx4
0x2001
CONTROL 0x2000 Word/Byte System control register 51
Table 12 – System Protected Ports Overview

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9.3. Standard ports

Table 13 shows the available standard ports. These ports are always accessible independent from the status of
the USER bit.

Access
Name Address Description Page
Mode
0x28ED
SC_CTRL 0x28EC Word/Byte Control register for LIN AA
0x28EB
ANA_OUTP 0x28EA Word/Byte Control register for HVDIFF
0x28E9
ANA_OUTO 0x28E8 Word/Byte Control register for shunt measurement unit 106
0x28E7
ANA_OUTN 0x28E6 Word/Byte HV[4] and HV[5] current selection register
0x28E5
ANA_OUTM 0x28E4 Word/Byte Current trim register for HVDIFF
0x28E3
ANA_OUTL 0x28E2 Word/Byte Current control and trim register
0x28E1
ANA_OUTK 0x28E0 Word/Byte 10Bit DAC for HVDIFF
0x28DF
ANA_OUTI 0x28DE Word/Byte HV differential measurement control
0x28DD
ANA_OUTH 0x28DC Word/Byte LIN Auto Addressing and current control
0x28DB
ANA_OUTG 0x28DA Word/Byte HV Bias Current select register 109
0x28D9
HV_TMR 0x28D8 Word/Byte Timer channel A or B to HV 110
0x28D7
HV_ENWU 0x28D6 Word/Byte HV - Enables wakeup detection 110
0x28D5
HV_INEN 0x28D4 Word/Byte HV - Threshold config / Input comparator type 109
0x28D3
HV_OUTOD 0x28D2 Word/Byte HV - Open drain outputs 109
0x28D1
HV_DEB 0x28D0 Word/Byte HV - Debounce configuration 107
0x28CF
HV_CFG 0x28CE Word/Byte HV configuration 107
0x28CD
HV_IN 0x28CC Word/Byte HV - Debounced and un-debounced input from pin 110
0x28B1
0x28B0
0x28AF
0x28AE
0x28AD
0x28AC
0x28AB
0x28AA
0x28A9
0x28A8
0x28A7
0x28A6
0x289F
0x289E
0x289D
0x289C
0x289B
0x289A
0x2885

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Access
Name Address Description Page
Mode
PWM6_CMP 0x2884 Word/Byte PWM 6 - Compare interrupt threshold register 66
0x2883
PWM6_HT 0x2882 Word/Byte PWM 6 - High threshold register 66
0x2881
PWM6_LT 0x2880 Word/Byte PWM 6 - Low threshold register 65
0x287F
PWM6_PER 0x287E Word/Byte PWM 6 - Period duration 66
PWM6_PSCL 0x287D Byte PWM 6 - Prescaler register 67
PWM6_CTRL 0x287C Word/Byte PWM 6 - Control register 67
0x287B
PWM5_CMP 0x287A Word/Byte PWM 5 - Compare interrupt threshold register 66
0x2879
PWM5_HT 0x2878 Word/Byte PWM 5 - High threshold register 66
0x2877
PWM5_LT 0x2876 Word/Byte PWM 5 - Low threshold register 65
0x2875
PWM5_PER 0x2874 Word/Byte PWM 5 - Period duration 66
PWM5_PSCL 0x2873 Byte PWM 5 - Prescaler register 67
PWM5_CTRL 0x2872 Word/Byte PWM 5 - Control register 67
0x2871
PWM4_CMP 0x2870 Word/Byte PWM 4 - Compare interrupt threshold register 66
0x286F
PWM4_HT 0x286E Word/Byte PWM 4 - High threshold register 66
0x286D
PWM4_LT 0x286C Word/Byte PWM 4 - Low threshold register 65
0x286B
PWM4_PER 0x286A Word/Byte PWM 4 - Period duration 66
PWM4_PSCL 0x2869 Byte PWM 4 - Prescaler register 67
PWM4_CTRL 0x2868 Word/Byte PWM 4 - Control register 67
0x2867
PWM3_CMP 0x2866 Word/Byte PWM 3 - Compare interrupt threshold register 66
0x2865
PWM3_HT 0x2864 Word/Byte PWM 3 - High threshold register 66
0x2863
PWM3_LT 0x2862 Word/Byte PWM 3 - Low threshold register 65
0x2861
PWM3_PER 0x2860 Word/Byte PWM 3 - Period duration 66
PWM3_PSCL 0x285F Byte PWM 3 - Prescaler register 67
PWM3_CTRL 0x285E Word/Byte PWM 3 - Control register 67
0x285D
PWM2_CMP 0x285C Word/Byte PWM 2 - Compare interrupt threshold register 66
0x285B
PWM2_HT 0x285A Word/Byte PWM 2 - High threshold register 66
0x2859
PWM2_LT 0x2858 Word/Byte PWM 2 - Low threshold register 65
0x2857
PWM2_PER 0x2856 Word/Byte PWM 2 - Period duration 66
PWM2_PSCL 0x2855 Byte PWM 2 - Prescaler register 67
PWM2_CTRL 0x2854 Word/Byte PWM 2 - Control register 67
0x2853
PWM1_CMP 0x2852 Word/Byte PWM 1 - Compare interrupt threshold register 66
0x2851
PWM1_HT 0x2850 Word/Byte PWM 1 - High threshold register 66
0x284F
PWM1_LT 0x284E Word/Byte PWM 1 - Low threshold register 65
0x284D
PWM1_PER 0x284C Word/Byte PWM 1 - Period duration 66
PWM1_PSCL 0x284B Byte PWM 1 - Prescaler register 67
PWM1_CTRL 0x284A Word/Byte PWM 1 - Control register 67

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Access
Name Address Description Page
Mode
0x2841
TMR3_CNT 0x2840 Word/Byte Timer 3 - Counter 82
0x283F
TMR3_REGA 0x283E Word/Byte Timer 3 - Channel A 80
0x283D
TMR3_REGB 0x283C Word/Byte Timer 3 - Channel B 80
0x283B
TMR3_CTRL 0x283A Word/Byte Timer 3 - Control register 81
0x2839
TMR2_CNT 0x2838 Word/Byte Timer 2 - Counter 82
0x2837
TMR2_REGA 0x2836 Word/Byte Timer 2 - Channel A 80
0x2835
TMR2_REGB 0x2834 Word/Byte Timer 2 - Channel B 80
0x2833
TMR2_CTRL 0x2832 Word/Byte Timer 2 - Control register 81
0x2831
TMR1_CNT 0x2830 Word/Byte Timer 1 - Counter 82
0x282F
TMR1_REGA 0x282E Word/Byte Timer 1 - Channel A 80
0x282D
TMR1_REGB 0x282C Word/Byte Timer 1 - Channel B 80
0x282B
TMR1_CTRL 0x282A Word/Byte Timer 1 - Control register 81
0x2829
0x2828
0x2827
0x2826
0x2825
0x2824
0x2823
0x2822
0x2821
LIN_XCFG 0x2820 Word/Byte Configuration port for external LIN phy or protocol layer
0x281F
ANA_INB 0x281E Word/Byte Wake up sources 31
0x281D
ANA_INA 0x281C Word/Byte Interrupt source of generated interrupts 57
0x281B
AWD_CTRL 0x281A Word/Byte Analog Watchdog (AWD) interface 98
0x2819
0x2818
0x2817
0x2816
0x2815
ADC_DBASE 0x2814 ADC Data base pointer 87
0x2813
ADC_SBASE 0x2812 ADC Mux, Reference and Trigger source selection 87
0x2811
ADC_CTRL 0x2810 ADC control register 88
0x280F
0x280E
0x280D
0x280C
0x280B
0x280A
0x2809
0x2808
0x2807

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Access
Name Address Description Page
Mode
TIMER 0x2806 Word/Byte Timer control register 68
0x2805
WD_TG 0x2804 Byte Intelligent watchdog tag register 96
WD_CTRL 0x2803 Byte Core watchdog - Control register 96
WD_T 0x2802 Byte Core watchdog - Timeout register 96
HW_VER 0x2801 MULAN3 Hardware Version
VARIOUS 0x2800 Byte NVRAM Status Register 50
Table 13 – Standard Ports Overview

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10. Memories
10.1. RAM sharing
MLX4 and MLX16 share the RAM by a mechanism controlled by 2 ports, SHRAML and SHRAMH. The principle is
shown in Figure 11

Private
M4

MLX4 private
RAMSize

MLX16 private
Shared
M4

MLX16 + MLX4 shared

SHRAML = M4Private + M4Shared

SHRAMH = Last RAM Address - M4Private

Figure 11 – MLX4 and MLX16 RAM sharing principle

Notes:
 Ports SHRAMH and SHRAML can only be changed when Mlx4 is in reset (e.g. M4_RB = 0). When Mlx4 is
running, writing to those ports has no action (e.g. ports are unchanged) and no error is flagged to
Mlx16.

10.2. Flash sharing

Each CPU has its own code lying into Flash but there is no specific mechanism to isolate them. The linker
program merge the two programs and verify that there is no overlapping, but if at execution time an error
happens that one CPU jumps into the code of the other one, it will of course execute unpredictable instructions
and this situation will be detected either by watchdogs or will generate a protection error.

10.3. Flash memory

The 32k byte flash memory is organized in 256 pages a 32 double-words (32 user bits per double-word).

The 32 user bits are secured by a hardware ECC mechanism (ECC= Error Checking and Correcting) and additional
7 bits. By this the memory can correct single bit fail per double word, and detect double bit fail per double
word. The MLX16 doesn't check if there was a double bit failure. In case there is a double bit failure an invalid
opcode can be fetched from the MLX16. This will cause a reset of the complete device.
The write of a flash memory page takes typically 5ms the erase procedure typically 40ms. The memory is read
by the CPU at full system clock speed.

Furthermore, the memory has a special range. It is a latch based buffer, which is used to read or write the non-
volatile memory array by page. This buffer has the size of 1 page

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39 bits

Data Bits Check Bits

Mlx16 Byte 32 bits 7 bits
Address
BFFF

32 DW Main Page 255

BF80

5FFF

32 DW Main Page 63 MAIN ARRAY

256K bits
Mlx16 5F80 32K Bytes
Fetch/Read
16K Words
Area
8K DWords

40FF
32 DW Main Page 1

4080
407F

32 DW Main Page 0

4000

Figure 12 – Flash organization (8Kx32)

The macro uses the 1.8 and 3.3 volt power supply to perform both read and in-system programming (ISP), built-
in charge pumps generate the high voltages for write and erase operations.

The Flash can be programmed:

 Via the test pin interface using the Melexis emulator under lab conditions
 In the application via the pin LIN
o using the standard LIN protocol and Melexis USB LIN Master
o using nonstandard fast LIN protocol and the Melexis programming tool
o
o using the Melexis recommended production tool PTC04

Data retention after min. 56000h at Tj ≤ 85°C

up to 1,000 programming / erase cycles at Tj,av ≤ min. 6800h at Tj ≤ 125°C

85°C
min. 2000h at Ta ≤ 150°C with Tj ≤ 155°C

Data retention after

up to 10 programming / erase cycles at Tj,av ≤ min. 15 years at Tj ≤ 85°C

85°C

Table 14 – Flash Cycles and data retention

The maximum programming and erase temperature is 85degC.

Data retention is still guaranteed after applying the maximum allowed number of cycles.

10.3.1. Flash Trimming

For a proper work the Flash macro needs to be trimmed during the startup. The customer does not need to take
care for this trimming. In the following the procedure for the trimming is described only for better
understanding.
During Melexis production test the digital values for 2 Flash voltages (VMG and VREF) are defined and stored in
one part of the NVRAM (see also chapter 10.4 NVRAM).
After POR or SLEEP MODE an internal hardware state machine replaces the Flash data by a sequence of 6
instructions that will make the CPU read the Flash trimming words from NVRAM page2 and copy in the flash

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trimming system ports FLASHTRIMx. The last instruction of the state machine is a jump back to the reset
address and a stop of flash data replacement.
After this last instruction the firmware will execute normally.

10.3.2. Flash ports

IO port: FLCTRL0
Address: 2026h Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
FL_WRERA_ FL_WRERA_
Melexis reserved testmode bits FL_DBE FL_DETECT
SEL EN
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
Melexis reserved testmode bits
Melexis reserved
write is ignored, read back to all=0
testmode bits
Define the action when CPU writes into Flash:
FL_WRERA_SEL 1: Latches Area content stored into NV-Area target page
0: NV-Area target page erased
FL_WRERA_EN Enable NV-Area Write or Erase when CPU writes into it
Double Error Detected in Flash read. Will be set and kept until the bit will be cleared
FL_DBE by software. It must be cleared by software. The Bit will trigger a program error
interrupt.

0 if no flash present (only ROM/XROM) / 1 if there is a flash (read only bit, write is
FL_DETECT
ignored)
Table 15 – Flash control port

10.4. NVRAM
The controller incorporates 2 NVRAM blocks of 128 words (2K Bit) each. Each NVRAM is organized in 2 pages.

With this NVRAM it is possible to store non-volatile information of the customer’s application data.

The NVRAM has a built-in error detection and a single bit error correction.

The block has three modes of operation:

 SRAM mode,
 Nonvolatile recall mode
 Nonvolatile store mode.

In SRAM mode, the memory operates as a static RAM with fast read and write cycles.
The SRAM can be read and written with word access in unlimited number of times, while independent
nonvolatile data resides in NVRAM. The data of the NVRAM are unchanged during the SRAM mode.
The SRAM can be read and written at full CPU operating frequency.

In the nonvolatile modes the SRAM functions are disabled, because there is a data transfer between SRAM and
NVRAM. Once the recall or store cycle is initiated, further input or output are disabled until the cycle is
completed.

In nonvolatile storage operation, all data from the SRAM are transferred in one parallel step to NVRAM. The
store cycle has to be initiated under user control via a pin signal.
The store operation takes maximum <15ms. No SRAM access is allowed during storage operation.

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The nonvolatile recall mode is used for writing back the data from NVRAM to SRAM. Internally, recall is a two-
step procedure. First, the SRAM data is cleared and second, the nonvolatile data is written to the SRAM. The
content of the SRAM will be overwritten.
The recall operation does not affect the data in the NVRAM cells, they can be recalled an unlimited number of
times.
The recall operation takes maximum <10s. No SRAM access is allowed during recall operation.

The NVRAM can be programmed:

 Via the test pin interface using the Melexis emulator under lab conditions. This is the only mode to
access page 2 or to use any test mode functions of the NVRAM.
 In application mode via the pin LIN
o using the standard LIN protocol and Melexis USB LIN Master
o using nonstandard fast LIN protocol and the Melexis programming tool

Data retention after

up to 100,000 programming / erase cycles at Tj,av ≤ min. 56000h at Tj ≤ 85°C

25°C
min. 6800h at Tj ≤ 125°C
or
min. 2000h at Ta ≤ 150°C with Tj ≤ 155°C
up to 10,000 programming / erase cycles at Tj,av ≤
150°C
Table 16 – NVRAM Cycles and data retention

Application Hints:
Melexis supports Read, Write and Store with library routines
The store operation is completely under Software control. It can be done at any time by software.

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10.4.1. NVRAM organization

Size Address-
Device Page Read Write Usage
(words) range
2
0x1180 -
NVRAM2 (upper 64 User Testmode Melexis trim data
0x11FF
words)
1
0x1100 - Application
NVRAM2 (lower 64 User User
0x117F Customer
words)
2 Melexis patch area
0x1080 -
NVRAM1 (upper 64 User Testmode + trim data
0x10FF
words)
1
0x1000 - Application /
NVRAM1 (lower 64 User User
0x107F Customer
words)
Table 17 – NVRAM organization

Syntax:
User: Access to SRAM (volatile area) always possible;
Store and Recall (to/from non-volatile area) only in System mode possible
Testmode: Access possible only in test mode

Each page is separately selectable for non-volatile operation.

NVRAM2 page 2 is reserved for Melexis only, there are stored all the trimming data for the IC. Any change data
may result in malfunction of the IC.

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10.4.2. NVRAM ports

IO port: NV_CTRL
Address: 2024h Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
NV1_MEM_ NV1_MEM_ reserved NV_
Melexis reserved testmode bits NV_BUSY
ALLC SEL SRAMWR
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
MLX
NV2_MEM_ NV2_MEM_ reserved
NV_SEL Melexis reserved testmode bits
ALLC SEL testmode
bit
Melexis reserved
write is ignored, read back to all=0
testmode bits
0 - Select NVRAM1 for Store/Recall operation
NV_SEL
1 - Select NVRAM2 for Store/Recall operation
NV1(2)_MEM_ALLC Enables write in both (0) or only one page (1)
NV1(2)_MEM_SEL Selection between upper (1) and lower (0) page

Write mode = NV_CONF[1:0] :

- determine action of NVRAM block :
x0: SRAM mode
NV_CONF[1] / 01: Recall (NV Area -> SRAM)
NV_SRAMWR 11: Store (SRAM -> NV Area)
Read mode = NV_SRAMWR:
- reflects differences between SRAM and nonvolatile NV area ;
0: SRAM = NV Area, 1: SRAM was written, it may differ to NV area
NV_CONF[0] / NV_BUSY Read mode = NV_BUSY:
NV_BUSY - cleared when operation done
Table 18 – NVRAM control port

IO port: VARIOUS
Address: 2800h Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
NV_DED WKUP PHISTAT1 PHISTAT0 Melexis reserved SWI
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
Melexis reserved
Melexis reserved write is ignored, read back to all=0
SWI Software interrupt request (automatically cleared, write only bit)
PHISTAT0
LIN physical status (read only bit, write is ignored)
PHISTAT1
WKUP LIN wake-up (read only bit, write is ignored)

Double Error Detected in NVRAM read. Will be set and kept until the next NVRAM
NV_DED
read access. Cannot be cleared by software (read only bit, write is ignored).
Table 19 – NVRAM status port

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11. Interrupts
11.1. Introduction
This chapter explains how the interrupts are handled inside the chip. It clarifies and gives add-on information on
the description of the interrupts in the MLX16X8 data book. It also gives the customer an overview of the
interrupt allocation table.

11.2. Interrupt sources

There are a number of different interrupt sources in the chip:
 system interrupts like system reset, stack overflow, address error …
 user block interrupts like PWM interrupts, timer interrupts …

11.2.1. High level system interrupts

The system interrupts are the interrupts at position 0 to 8. For those interrupt routines, Melexis provides an
interrupt service routine to handle them correctly.
These routines handle:
 the correct start-up and power down of the chip, i.e. the MULAN core,
 communication between the MLX4 and MLX16X8 CPU’s,
 NVRAM write routines,
 invalid address errors,
 stack overflows, …

11.2.1.1. Reset interrupt and watchdog

This interrupt is generated at power on reset or if the intelligent watchdog asks for a reset. To be able to differ
between the reason for the reset the WD_BOOT bit in the CONTROL port can be used. More information can be
found in Table 20.

IO port: CONTROL
Address: 2000h Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Melexis
WD_BOOT Melexis reserved HALT
reserved
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
Melexis reserved
Melexis reserved Write access is not allowed.
1 – Last reset was triggered from watchdog
WD_BOOT 0 – Last reset was a POR
(read only bit, write is ignored)
1 – Halt the MLX16
HALT
(Write only bit, read access gives always “0”)
Table 20 – CONTROL port

11.2.1.2. Stack error

A stack error occurs when the Mlx16 uses the stack pointer to access an invalid or an unauthorized area. No
protection error or invalid address interrupt is generated. Obviously this interrupt uses a jump and does not
push the program counter into the stack.

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11.2.1.3. Exception error

There are 3 interrupts due to software errors on the Mlx16, being a protection error, an invalid address or a
program error. These interrupts are at level 0, therefore you cannot return to the interrupted program. The
program counter value pushed on the stack must be used only for debugging purpose.

11.2.1.4. Protection error

A protection error interrupt happens when the Mlx16 tries to do an unauthorized access or to clear the user bit
(Mlx16 M register). Here is an exhaustive list of possible causes:
 Write in user mode into the Flash, NVRAM.
 Access to NVRAM while it is busy (NV_BUSY=1 or NV_RDY = 0).
 Write in port while it is busy (NV_BUSY=1)
 ADC conversion request while ADC is busy (ADC_BUSY=1)
 Write in ANA_OUTx ports while corresponding OUTx_WE bit of port CONTROL is 0.
 Write in the Mlx4 RAM private area.
 Write in user mode into a system port.
 Access error in the Intelligent Watchdog
 Clear the user bit (try to enter system mode) not after a jump or call far page.

11.2.1.5. Invalid address

An invalid address interrupt occurs when the Mlx16 does an invalid memory access. Here is an exhaustive list of
possible causes:
 Read, write or fetch a word at an odd address
 Read, write or fetch into an unused area
 Write a byte or a bit in NVRAM or Flash.
 Write a bit in a digital port supporting only word or byte.
 Fetch into port area
 Access to an undefined custom I/O (user or system)

11.2.1.6. Program error

A program error occurs when the Mlx16 tries to execute an invalid Mlx16 instruction. Typically, it means that
Mlx16 has an invalid value in its program counter (PC).

11.2.2. User block interrupts

The user block interrupts contains interrupts coming from:
 Timer modules
 PWM modules
 UART module
 Watchdog attention interrupt

The user is supposed to write the appropriate interrupt handlers for these interrupts.

Those interrupts typically share a single interrupt line of the MULAN/Mlx16 interrupt controller. They are
organized in a second level interrupt controller as described below.

11.3. Interrupt management

11.3.1. Interrupt enabling and masking
Every non system interrupt can be enabled or masked. The mask bit does not disable the interrupt source.

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All the masking bits are grouped into dedicated ports; please refer to the ports map for detail. When the MASK
bit is set, the belonging interrupt is enabled.
After reset the MASK ports are reset, so all interrupts are disabled.

In case interrupts are:

 enabled with the enable flag, and
 disabled by priority,
the interrupt sources are still active. An interrupt is memorized only once, and it will be performed when CPU
runs on a priority again which enables this interrupt.

11.3.2. Pending interrupts

When an interrupt request (IRQ) occurs and it cannot be served immediately, the pending bit of this IRQ is set.
All the pending bits are into dedicated ports; please refer to the ports map for detail.
Even if interrupts are masked, the state of the sources can be checked by reading the pending bits.

The pending bit is set only once, even when more than one IRQ occurred before being serviced.

Software can clear a pending interrupt source by setting the corresponding bit in the IO port PEND / XIxPEND.

11.3.3. Call and jump interrupts

When an interrupt occurs, the interrupt controller suppresses the next instruction fetched from memory and
displays another instruction to the MLX16 CPU instead.
This instruction is typically a CALL to the specified interrupt vector address. (for reset and stack error a JUMP
instead of CALL is issued)

At the interrupt vector the priority is set and a jump to the appropriate interrupt service routine (ISR) follows.
At the end of the ISR a return can be placed, and the program counter returns to where it came from before the
IRQ occurred.

As after a stack error or a reset a return point cannot be defined, those interrupts execute a JUMP to the vector
address.

11.4. Interrupt priorities

Every interrupt source has its own priority. The priorities are grouped into eight classes, from priority zero to
priority seven; zero is the highest priority, seven the lowest. An ISR can be interrupted by any other IRQ with the
same priority or higher – i.e. the same class or lower.

There are some mechanisms that define the interrupt priority:

 The user priority defines the current working priority level of the running software. This is set by the PR
bits in the MLX16 M register and is used to decide, if an interrupt request is allowed to interrupt the
current code (ISR or normal routines).
 The software priority (or absolute priority) defines the priority of the interrupt request. It must be
higher or equal than the current user priority (lower number) to allow interrupting the current code.
The software priority of the non-system interrupts can be programmed through the corresponding
port.
 The hardware priority (or priority position) is used as conflict resolver in case 2 interrupt sources of
same software priority are pending.

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11.4.1. User priority

During execution of every piece of code, there is a certain level of interrupt masking. The PR bits in the M
register of the MLX16X8 -see MLX16X8 data book- define the interrupt priority of an IRQ that can interrupt the
currently executing code.
Every IRQ with a software interrupt priority equal or higher (equal or lower number) than this value can
interrupt this routine.
This is true for all pieces of code, ISR as well as the main loop. If during the main loop, these PR bits are set to 4,
an IRQ of priority 5 will never be seen.

It is the responsibility of the customer to make sure that in the main loop these PR bits have the correct value
so that all wanted interrupts can be acknowledged. In the Melexis firmware platform, this interrupt level is set
to seven (lowest priority) when entering the main function. This means that every IRQ can interrupt the main
function.

When entering an ISR, the first instruction has to be a PSUP, #constant instruction that pushes this M register
on the stack and sets a new value in the PR bits (#constant parameter in this instruction, value from 0 to 7). By
writing a new value in the PR bits in the ISR, another level of interrupts can be masked.

It is possible that an ISR of an IRQ with software priority 5 sets these bits to 2. By doing so, all IRQs with
software priority less than 2 (higher number) are blocked. This means that an ISR routine of an IRQ with
software priority 5 can block an IRQ with software priority 4 by changing the PR bits in its ISR. This is called
“interrupt priority inversion”. The customer has the responsibility to check if this can cause problems in his
application.

The M register has to be manually restored when exiting the ISR by popping it from the stack. This has to be the
very last instruction of the ISR.

The PSUP and pop instructions to keep track of the M register and PR bits are handled automatically in the
Melexis firmware platform.

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11.5. Mlx16 interrupt table

Column “Pos” represents the interrupt input position in the interrupt controller.
Column “Abs” represents the absolute priority of the input.
Column “Rel” represents the relative priority for inputs having an identical absolute priority.
Column “Typ” defines which instruction will be issued by the interrupt controller in case of interrupt.

Description Pos Priority Type Note Ports

Abs Rel PRIO MASK PEND
Reset + Watchdogs Reset 0 0 0 Jump 1,3,4
Stack error 1 0 1 Jump 1,3,4
Protection error 2 0 2 Call 2,3,4
Invalid address 3 0 3 Call 2,3,4
Program error 4 0 4 Call 2,3,4
Exchange request 5 1 0 Call 3,5 MASK[0] PEND[0]
Task reset 6 1 1 Call 3 MASK[1] PEND[1]
Watchdog attention 7 1 2 Call MASK[2] PEND[2]
Mutex 8 2 0 Call MASK[3] PEND[3]
Signal, Handshake, Event, [Mutex] 9 5 0 Call MASK[4] PEND[4]
Timer 15bit 10 3-6 1 Call 6 PRIO[1:0] MASK[5] PEND[5]
ADC end of conversion 11 3-6 2 Call 6 PRIO[3:2] MASK[6] PEND[6]
Not used 12 3-6 3 Call 6 PRIO[5:4] MASK[7] PEND[7]
External Interrupt 0 – Timer 16bit 13 3-6 4 Call 6 PRIO[7:6] MASK[8] PEND[8]
External Interrupt 1 – not used 14 3-6 5 Call 6 PRIO[9:8] MASK[9] PEND[9]
PRIO[11:1
External Interrupt 2 – PWMs 15 3-6 6 Call 6 MASK[10] PEND[10]
0]
PRIO[13:1
External Interrupt 3 – UART 16 3-6 7 Call 6 MASK[11] PEND[11]
2]
PRIO[15:1
External Interrupt 4 – IOs 17 3-6 8 Call 6 MASK[12] PEND[12]
4]
Software interrupt 18 7 0 Call MASK[13] PEND[13]
Table 21 – Interrupt inputs
Notes:
1. Abort current instruction
2. Abort current instruction; Return is NOT possible
3. No disable possible
4. Priority 0 can only be reached in system mode
5. For conformance test
6. If Abs = 5, Pos 9 int. has always priority over Pos 10 to 17

Reminder:
For Mlx16X8, the highest priority is 0 and the lowest is 7.
The absolute priority is compared to Mlx16 priority to trigger an interrupt
The relative priority is used by interrupt controller to decide between identical absolute priority interrupts fired
at the same time: Lowest is issued first.

Note:
The level 0 of priority is not reachable in user mode. When Mlx16X8 sets priority to 0 in user mode, it is
interpreted as priority 1 by the interrupt controller.

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11.5.1. Interrupt vectors

Figure 13 shows the interrupt vectors table as well as the type of interrupt generated (call or jump). They all use
Far Page 0 (e.g. top of the Flash/ROM).

Description Pos Priority Type Interrupt in Fp0:

Abs Rel Addr Name
Reset + Watchdogs Reset 0 0 0 Jump Fp6:68 RST_WD_IT
Stack error 1 0 1 Jump Fp6:70 STACK_IT
Protection error 2 0 2 Jump Fp6:78 PROT_ERR_IT
Invalid address 3 0 3 Jump Fp6:80 INV_AD_IT
Program error 4 0 4 Jump Fp6:88 PROG_ERR_IT
Exchange request 5 1 0 Call Fp0:90 EXCHANGE_IT
Task reset 6 1 1 Call Fp0:98 TASK_RST_IT
Watchdog attention 7 1 2 Call Fp0:A0 WD_ATT_IT
Mutex 8 2 0 Call Fp0:A8 M4_MUTEX_IT
Signal, Handshake, Event, [Mutex] 9 5 0 Call Fp0:B0 M4_SHE_IT
Timer 15bit 10 3-6 1 Call Fp0:B8 TIMER_IT
ADC end of conversion 11 3-6 2 Call Fp0:C0 ADC_IT
Not used 12 3-6 3 Call Fp0:C8
External Interrupt 0 – Timer1 / Timer3 16bit 13 3-6 4 Call Fp0:D0 EXT0_IT
External Interrupt 1 – Timer2 16bit 14 3-6 5 Call Fp0:D8 EXT1_IT
External Interrupt 2 – PWMs 15 3-6 6 Call Fp0:E0 EXT2_IT
External Interrupt 3 – UART 16 3-6 7 Call Fp0:E8 EXT3_IT
External Interrupt 4 – IOs 17 3-6 8 Call Fp0:F0 EXT4_IT
Software interrupt 18 7 0 Call Fp0:F8 SOFT_IT
Figure 13 – Interrupt vectors

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11.6. External Interrupts

Every external interrupt can be masked independently. Also separate clearing of pending interrupts is
supported by the according ports. The priority is defined in the setting for the external interrupts in the
MULAN3 interrupt controller, as described in the previous chapter.

The sources are distributed to the five second level interrupt controllers as follows:

External Interrupt 0 sources

Local name Rel PORT PORT
Interrupt Source Description Pos
Inside block Priority MASK PEND
Capture Int Ch A, Timer
TMR1_CAPA_IT TMR1_INT1 0 1 XI0MASK[9] XI0PEND[9]
1
Capture Int Ch B, Timer
TMR1_CAPB_IT TMR1_INT5 1 2 XI0MASK[8] XI0PEND[8]
1
Compare Int Ch A,
TMR1_CMPA_IT TMR1_INT2 2 3 XI0MASK[7] XI0PEND[7]
Timer 1
Compare Int Ch B,
TMR1_CMPB_IT TMR1_INT4 3 4 XI0MASK[6] XI0PEND[6]
Timer 1
TMR1_OVF_IT Overflow Int Timer 1 TMR1_INT3 4 5 XI0MASK[5] XI0PEND[5]
Capture Int Ch A, Timer
TMR3_CAPA_IT TMR3_INT1 5 6 XI0MASK[4] XI0PEND[4]
3
Capture Int Ch B, Timer
TMR3_CAPB_IT TMR3_INT5 6 7 XI0MASK[3] XI0PEND[3]
3
Compare Int Ch A,
TMR3_CMPA_IT TMR3_INT2 7 8 XI0MASK[2] XI0PEND[2]
Timer 3
Compare Int Ch B,
TMR3_CMPB_IT TMR3_INT4 8 9 XI0MASK[1] XI0PEND[1]
Timer 3
TMR3_OVF_IT Overflow Int Timer 3 TMR3_INT3 9 10 XI0MASK[0] XI0PEND[0]

External Interrupt 1 sources

Local name Rel PORT PORT
Interrupt Source Description Pos
Inside block Priority MASK PEND
Capture Int Ch A, Timer
TMR2_CAPA_IT TMR2_INT1 0 1 XI1MASK[9] XI1PEND[9]
2
Capture Int Ch B, Timer
TMR2_CAPB_IT TMR2_INT5 1 2 XI1MASK[8] XI1PEND[8]
2
Compare Int Ch A,
TMR2_CMPA_IT TMR2_INT2 2 3 XI1MASK[7] XI1PEND[7]
Timer 2
Compare Int Ch B,
TMR2_CMPB_IT TMR2_INT4 3 4 XI1MASK[6] XI1PEND[6]
Timer 2
TMR2_OVF_IT Overflow Int Timer 2 TMR2_INT3 4 5 XI1MASK[5] XI1PEND[5]

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External Interrupt 2 sources

Rel PORT PORT
Interrupt Source Description Pos
Priority MASK PEND
PWM1_CMPI PWM1 compare interrupt 0 1 XI2MASK[15] XI2PEND[15]
PWM1_CNTI PWM1 counter interrupt 1 2 XI2MASK[14] XI2PEND[14]
PWM2_CMPI PWM2 compare interrupt 2 3 XI2MASK[13] XI2PEND[13]
PWM2_CNTI PWM2 counter interrupt 3 4 XI2MASK[12] XI2PEND[12]
PWM3_CMPI PWM3 compare interrupt 4 5 XI2MASK[11] XI2PEND[11]
PWM3_CNTI PWM3 counter interrupt 5 6 XI2MASK[10] XI2PEND[10]
PWM4_CMPI PWM4 compare interrupt 6 7 XI2MASK[9] XI2PEND[9]
PWM4_CNTI PWM4 counter interrupt 7 8 XI2MASK[8] XI2PEND[8]
PWM5_CMPI PWM5 compare interrupt 8 9 XI2MASK[7] XI2PEND[7]
PWM5_CNTI PWM5 counter interrupt 9 10 XI2MASK[6] XI2PEND[6]
PWM6_CMPI PWM6 compare interrupt 10 11 XI2MASK[5] XI2PEND[5]
PWM6_CNTI PWM6 counter interrupt 11 12 XI2MASK[4] XI2PEND[4]

External Interrupt 3 sources

Rel PORT PORT
Interrupt Source Description Pos
Priority MASK PEND
0 1 XI3MASK[15] XI3PEND[15]
1 2 XI3MASK[14] XI3PEND[14]
UART1_RRI UART1 End of reception interrupt 2 3 XI3MASK[11] XI3PEND[11]
UART1_TRI UART1 Start of transmission interrupt 3 4 XI3MASK[10] XI3PEND[10]
UART1 Receive shifter overflow
UART1_RSI 4 5 XI3MASK[9] XI3PEND[9]
interrupt
UART1 Transmit shifter empty
UART1_TSI 5 6 XI3MASK[8] XI3PEND[8]
interrupt
UART1_SBI UART1 Start bit error interrupt 6 7 XI3MASK[7] XI3PEND[7]
UART1 Transmit error interrupt
UART1_TEI 7 8 XI3MASK[6] XI3PEND[6]
(collision)

External Interrupt 4 sources

Rel PORT PORT
Interrupt Source Description Pos
Priority MASK PEND
ANA_INA[15] Custom interrupt 15 (=OVT) 0 1 XI4MASK[15] XI4PEND[15]
ANA_INA[14] Custom interrupt 14 (=UV_VS) 1 2 XI4MASK[14] XI4PEND[14]
ANA_INA[13] Custom interrupt 13 (=OV_VS) 2 3 XI4MASK[13] XI4PEND[13]
ANA_INA[12] Custom interrupt 12 (=OC_SENSE) 3 4 XI4MASK[12] XI4PEND[12]
ANA_INA[11] Custom interrupt 11 (=HVINT[3]) 4 5 XI4MASK[11] XI4PEND[11]
ANA_INA[10] Custom interrupt 10 (=HVINT[2]) 5 6 XI4MASK[10] XI4PEND[10]
ANA_INA[9] Custom interrupt 9 (=HVINT[1]) 6 7 XI4MASK[9] XI4PEND[9]
ANA_INA[8] Custom interrupt 8 (=HVINT[0]) 7 8 XI4MASK[8] XI4PEND[8]
ANA_INA[7] Custom interrupt 7 (=HVINT[5]) 8 9 XI4MASK[7] XI4PEND[7]
ANA_INA[6] Custom interrupt 6 (=HVINT[4]) 9 10 XI4MASK[6] XI4PEND[6]
ANA_INA[5] Custom interrupt 5 10 11 XI4MASK[5] XI4PEND[5]
ANA_INA[4] Custom interrupt 4 11 12 XI4MASK[4] XI4PEND[4]
ANA_INA[3] Custom interrupt 3 12 13 XI4MASK[3] XI4PEND[3]
ANA_INA[2] Custom interrupt 2 13 14 XI4MASK[2] XI4PEND[2]

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ANA_INA[1] Custom interrupt 1 14 15 XI4MASK[1] XI4PEND[1]

ANA_INA[0] Custom interrupt 0 15 16 XI4MASK[0] XI4PEND[0]

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12. PWM
12.1. General introduction and features
The controller has 6 independent PWM modules which can be mapped to the different HVs. The mapping can
be found in the chapter ‘Routing of PWM outputs to external pins’.

The following description refers to a single PWM module only.

Characteristics of one PWM module are:

 PWM resolution of up to 16 bit
 Programmable prescaler.
 Programmable duty cycle: 0 – 100%.
 Programmable phase shift and/or output period with double buffers.
 Mirror mode with double buffer for symmetrical output waveform creation.
 Programmable interrupt output signal anywhere within the PWM period.
 Fix interrupt output signal when new programmable data becomes active (PWM-Counter == 0 and
Master mode active)
 supports synchronized operation between multiple PWM modules (Master-Slave)
 double buffer mechanism for the threshold and period registers, their update is always connected to
the low threshold ports write and the counter equal to 0

To make the use of the PWM module more comfortable a macro library and an application note are available at
the Softdist server.

The following chapters are intent to give a more detailed technical description of the PWM unit.

12.2. Block diagram and description

The functional block diagram of one PWM module is shown below. This diagram is identical for the four
implemented PWMs.

Master control inputs Mirror mode

= SET_OUT from MASTER
SET_EXT Update Shadow
SET_OUT
CNT Buffers Logik Low threshold (PLT) PLT

SET_OUT
PLT shadow buffer
EXT
FPWMO

Mirror Pulse
Generation

1 PWMO
0 sel

= CNT from MASTER Comparator

CNT_EXT PLT ≤ CNT ≤ PHT MODE
Period register (PPER) PLT PHT
SET_OUT
PPER shadow buffer PHT shadow buffer
SET_OUT FPWMO
High threshold (PHT)
1 CNT
0 sel
CK Prescaler Counter
Independent mode

Prescaler control EXT

register (PPSCL) CNTI
Counter equal to 0

CMPI
Equality Comparator

Compare reg (PCMP)

EBLK EXT MODE EPI SET_OUT
Control register (PCTRL) ECI CNT
Slave control
Interrupt generation output(s)

Figure 14 – Functional diagram of one PWM module.

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One PWM module is programmed by the following IO ports:

 PCTRL : contains control and flag bits, determines the global operating state
 PPER : defines the PWM period duration in number of PWM clocks
 PPSCL : PWM prescaler, defines the relation from system to PWM clock
 PLT, PHT: the low and high threshold ports define the PWM output shape
 PCMP : the compare port determines the time for the programmable PWM interrupt

Each PWM module supports two main schemes to impact the shape of the generated output signal:
 Independent mode
 Mirror mode

In mirror mode the output is a pulse centered on the middle of the output period.
In independent mode the duty cycle and the phase shift of the output are controlled by software with two
threshold levels.

Following PWM parameters are programmable by software:

 the period (register PPER)
 the 2 edges within the PWM period by 2 threshold values, low and high (PLT and PHT) . Those
thresholds define duty cycle and phase shift in independent or pulse length in mirror mode.
 the compare register PCMP that triggers the PWM compare interrupt

These three parameters PPER, PLT and PHT are double buffered and updated at the end of the current output
period (CNT==0). This double buffer system prevents unexpected output waveform while modifying
parameters.

A programmable synchronous counter defines the period of the corresponding PWM output. A programmable
prescaler fixes the ratio between the clock of this counter and the input clock frequency.

The PWM module can create 2 interrupts, the fix counter interrupt CNTI at counter = 0, and the programmable
PWM compare interrupt CMPI. The compare interrupt triggers, when the internal counter reaches the value
programmed into port PCMP. PCMP is not buffered and can be updated any time.

12.3. PWM frequency control

The PWM frequency is programmable by the ports PPSCL and PPER. The PPER port can’t be reset, it needs an
initial write before enabling a PWM module.

The PWM counters clock selector is controlled by the port PPSCL. The value of this port is not buffered and can
be updated at any time.

The period length value PPER is double buffered, it will be update in case the counter value CNT is equal to 00h.
The PPER value is hardware limited to 0xFFFEh, even if the PPER port is written to0xFFFFh, the shadow register
will be updated to 0xFFFEh.

The frequency Fcnt of the PWM counter is given by the following equation:
f CK 1
Equation 1 f CNT  
M 2N
Where: Fck : PWM input frequency ; equal to the main system clock CK.
Fcnt : clock frequency of PWM internal counter
M : Programmed predivider between 0 and 15. Value fixed in IO port PPSCL[7:4].
N : Programmed predivider between 0 and 11. Value fixed in IO port PPSCL[3:0].

And the frequency Fpwmo of the PWM output PWMO is given by the equation:

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f CNT
Equation 2 f PWM 
PPER
Where: Fpwm : PWM frequency
PPER : programmed period width, internal counter CNT is restarted,
when this value is reached.

Both equations can be combined as follows:

f CK 1 1
Equation 3 f PWM   N
M 2 PPER

12.4. PWM frequency parameter selection

When determining the parameters for the PWM frequency it needs to be taken into consideration, that there
are overlapping PWM frequency ranges:

Fck / 2N-1

Fck / 2N

Fck / 2N+1

PPERmax
PWM output resolution

PPERmax / 2

PWM output frequency

Figure 15 – Relation between PWM resolution and frequency (M=0)
This reflects the PWM frequency formula as given above:
f CK 1 1
f PWM   N
M 2 PPER
For operating at highest possible resolution with the PWM frequency needed, the following definition scheme is
recommended:
 Select first the minimum value for N (PPSCL[3:0])
 select the maximum value for the period PPER
 choose the M value (PPSCL[7:4]) so that the target PWM frequency requirements are met

Example:
Assumptions:
PWM with 24kHz at max resolution is needed,
Fck=24MHz

Definition steps:
 start with N=0, M=0
 PPER = Fck/Fpwm = 24MHz / 24kHz = 1000
 PPER = 1000 => Fpwm = 24MHz/1000 = 24.00 kHz
 max resolution possible is > 10 bit (10bit=1024, 11bit=2048) for M = 0

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12.5. Synchronization of the PWM modules

The PWM unit provides the synchronous operation of multiple PWM modules.
Synchronization means the PWM modules are running on one PWM counter at the same frequency, but with
different pulse shape.

To allow this, the PWM modules are connected internally in a daisy-chain-like hierarchical scheme.

PWM1 PWM2 PWM3 PWM4

Figure 16 – Internal daisy chain connection of the PWM modules.

The PWM module generating the time regime is called “master”, the block running on an external counter (or
frequency resp.) is called “slave”.
Every PWM module can be either master or slave to the previous one. A single master following multiple slaves
is also possible; all share then the time base of the master.

MASTER SLAVE SLAVE MASTER

EXT=0 EXT=1 EXT=1 EXT=0

Figure 17 – sample configurations with multiple master and slave modules.

This bit EXT controls if a PWM module operates as master or slave. EXT=1 means a PWM module is slave to the
previous PWM module.

After Reset all PWM modules act as independent masters, not taking into account the external connections.

12.6. Independent mode

In independent mode the duty cycle and the phase shift of the output are controlled by software with the two
threshold levels PHT and PLT. The independent mode is the default operating scheme of the PWM modules, it
corresponds to the control bit MODE set to 0.
Assuming
 The control bit MODE is low,
 TCK is the input clock period,
 TCNT is the counter clock period
 The low threshold value PLT is lower than the high threshold value PHT, and
 The high threshold value PHT is lower than the period value PPER,

In this mode, the PWM high time is defined by the following equation:

Equation 4 t PWM _ HIGH 

Thigh

1

PHT  PLT   1
PPER f PWM PPER f PWM

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output period, PPER+1 output period, PPER+1

TCNT Thigh = PHT-PLT Thigh = PHT-PLT

1
PWMO 0

CNT=0 CNT=0
CNT=PLT CNT=PHT CNT=PPER CNT=PLT CNT=PHT CNT=PPER

Figure 18 – PWM output signal in independent mode.

The COMPARE always uses the PLT and PHT values in the shadow registers only, therefore the ports can be
updated at any time. The port values are transferred only after the PLT register was written, when the PWM
counter CNT getting equal to 0.

If the PWM module operates as slave (bit EXT=1 in PCTRL port), the external counter input CNT_EXT with the
master counter is used instead of the internal counter. The write of the masters PLT register will enable the
transfer of the threshold values and the period into the shadow registers for the slaves as well.

Special cases:
 PPER=0 : PWMO is frozen to the state being active at shadow register update
 PHT < PLT, PHT and PLT < PPER : identical phase shift and duty cycle, inverted PWMO signal
 PLT < PPER < PHT : PWMO stays at always high
 PHT < PPER < PLT : PWMO stays at always low
 PLT and PHT > PPER: PWMO is frozen to the state being active at shadow register update
 PHT = PLT, PHT and PLT < PPER : PWMO stays at always low

12.7. Mirror mode

When the control bit MODE is high, the mirror mode is selected. The output waveform will be a pulse with the
length specified in PLT port, centered in the PWM period (PPER+1).

Assuming
 The control bit MODE is high,
 TCK is the oscillator clock period,
 TCNT is the counter clock period,
 The pulse length value PLT is lower than the period value PPER,

In this mode, the PWM high time is defined by the equation:

Thigh 1 PLT 1
Equation 5 t PWM _ HIGH    
PPER f PWM PPER f PWM

Once the value Thigh has been written in the IO port PLT_x, the low and high thresholds are updated as
described below:
 The low threshold PLT is computed and the resulting value is used to set PLT; i.e. the previous value is
discarded. If this result is lower than 0, i.e. LT > PPER, PWM, data are forced to 0000h and the output
PWMO will be forced to 0.
 The high threshold PHT is computed and the resulting value is use to set PHT. If this result is greater
than PPER, i.e. PLT > PPER, the output PWMO will be forced to 1.
The new desired pulse length value is memorized in buffer. Due to this double buffer mechanism, threshold
values can be updated at any time.

Important: The new desired period value PPER must be updated before PLT.

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output period, PPER + 1

Thigh (↔ PLT)
TCNT Thigh/2

1
PWMO 0

CNT=0 CNT=(PPER+1) / 2 CNT=PPER

CNT=(PPER+1)/2 – PLT/2 CNT=(PPER+1)/2 + PLT/2

Figure 19 – PWM output signal in mirror mode.

In mirror mode the PLT and PHT values are recalculated only after the PLT port was written, when the PWM
counter CNT getting equal to 0.

If the PWM module operates as slave (bit EXT=1 in PCTRL port), the external counter input CNT_EXT with the
master counter is used instead of the internal counter. The write of the masters PLT register will enable the
write of the shadow registers for the slaves as well.

Special cases:
 PLT = 0 : PWMO stays at always low
 PLT > PPER: PWMO stays at always high (also valid for PPER=0 )

12.8. PWM control and command ports

Most of the ports are not reset during power up. It is recommended to set all PWM related ports to a correct
value before releasing the PWM_EBLK bit in the control register PWMx_CTRL.

IO port: PWM1_LT, PWM2_LT, PWM3_LT, PWM4_LT, PWM5_LT, PWM6_LT

Address: 0x284E, 0x2858, 0x2862, 0x286C, 0x2876, 0x2880 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
PLT[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

PLT[15:8]
PLT[15:0]: Low threshold level for PWM
Table 22 – PWM ports – Low Threshold (no Reset)

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IO port: PWM1_HT, PWM2_HT, PWM3_HT, PWM4_HT, PWM5_HT, PWM6_HT

Address: 0x2850, 0x285A, 0x2864, 0x286E, 0x2878, 0x2882 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
PHT[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

PHT[15:8]
PHT[15:0]: High threshold level for PWM
Table 23 – PWM ports – High Threshold (no Reset)

Due to a double buffer mechanism the port values PHT and PLT can be updated at any time.
Writing the PWM low threshold (PLT) enables the transfer of the port values into the double-buffer shadow
registers by default. The shadow registers will be written next time the counter CNT gets equal 0.

IO port: PWM1_CMP, PWM2_CMP, PWM3_CMP, PWM4_CMP, PWM5_CMP, PWM6_CMP

Address: 0x2852, 0x285C, 0x2866, 0x2870, 0x287A, 0x2884 Access mode: Word - Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
PCMP[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

PCMP[15:8]
PCMP[15:0]: Compare level for PWM, not RESET!
Table 24 – PWM bits – Compare Threshold (no Reset)

The PWM comparator value PCMP is used to generate interrupt independently of the threshold values.
This interrupt signal CMPI will be high active during one period of CK. An interrupt is generated when control bit
PWM_ECI is high and CNT reaches the value of PCMP.

IO port: PWM1_PER, PWM2_PER, PWM3_PER, PWM4_PER, PWM5_PER, PWM6_PER

Address: 0x284C, 0x2856, 0x2860, 0x286A, 0x2874, 0x287E Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
PPER[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

PPER[15:8]
PPER[15:0]: Period value for PWM (read the current value, after double buffer), no RESET!
Table 25 – PWM bits – Period value (no Reset)

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IO port: PWM1_CTRL, PWM2_CTRL, PWM3_CTRL, PWM4_CTRL, PWM5_CTRL, PWM6_CTRL

Address: 0x284A, 0x2854, 0x285E, 0x2868, 0x2872, 0x287C Access mode: Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
- - - PWM_ECI PWM_EPI PWM_MODE PWM_EXT PWM_EBLK
- unused
Enable control for PWM comparator interrupt PCMPI
PWM_ECI:
1 = interrupt output enabled 0 = interrupt output is forced to 0
Enable control for PWM counter interrupt PCNTI
PWM_EPI:
1 = interrupt output enabled 0 = interrupt output is forced to 0
Mode selector
PWM_MODE:
1 = Mirror mode 0 = Independent mode
External counter selector
PWM_EXT:
1 = PWM in slave mode, CNT=CEXT 0 = PWM in master mode, CNT=CINT
Enable signal
PWM_EBLK:
1 = PWM module enabled 0 = PWM module disabled
Table 26 – PWM ports – control bits (Reset=00h)

The prescaler port PPSCL controls the bits PWM_PRDV1[3:0] and PWM_PRDV0[3:0]. The IO port update can be
done at any time.

IO port: PWM1_PSCL, PWM2_PSCL, PWM3_PSCL, PWM4_PSCL, PWM5_PSCL, PWM6_PSCL

Address: 0x284B, 0x2855, 0x285F, 0x2869, 0x2873, 0x287D Access mode: Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
PWM_PRDV1[3:0] PWM_PRDV0[3:0]
PWM_PRDV1[3:0]: PWM prescaler, first part; clock frequency divided by ‘PWM_PRDV1[3:0]+1’
PWM_PRDV0[3:0]: PWM prescaler, second part; clock frequency divided by ‘2 PWM_PRDV0[3:0]’
Table 27 – PWM ports – Prescaler value (no Reset)

12.9. Interrupt connections

The PWM interrupts are connected into MULAN3 external interrupts block.

12.10. Routing of PWM outputs to external pins

The internal 4 PWM blocks are routed in the following way to external pins:

PWM block 1  pin HV0

PWM block 2  pin HV1
PWM block 3  pin HV2
PWM block 4  pin HV3
PWM block 5  pin HV4
PWM block 6  pin HV5

The routing can be activated by dedicated control bits, for further detail please refer to the ports descriptions in
the according HV IO chapters (see 20.4).

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13. Timers
There are 4 timer hardware blocks integrated. One simple 15bit timer and 3 universal 16bit timer with 6
different operation modes. More information can be found in the chapters below.

13.1. Simple 15bit Timer

The timing generation principle is shown in Figure 20.

1 MHz
Trimming
MULAN Programmable TIMER_IT (*)
System dividier (1µs to
Clock by 1 to 32768 32768µs)
1
15 (*) : Can be disabled by interrupt
Port TIMER controller
Figure 20 – Simple Timer

A 15 bits free running counter clocked by 1MHz is available to generate TIMER_IT interrupt at a rate varying
from 1µs (TIMER [14:0] = 0) to 32768µs (TIMER [14:0] = 32767). The timer is made of a down counting loadable
binary counter. It is enabled by TMR_EN (bit 15) of port TIMER. Once enabled, each time it reaches 0x0000; it is
reloaded by the value of port TIMER [14:0] and generates a TIMER_IT interrupt. Reading port TIMER reads the
current value of the counter when TMR_EN = 1 or an unknown value when TMR_EN = 0.

IO port: TIMER
Address: 0x2806 Access mode: Byte – Read and Write
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR_EN TIMER[14:8] TIMER[7:0]
At reset 0 x x x x x x x x x x x x x x x
Table 28 – Timer port

The generation of long timer delays can be done in software.

13.2. Universal 16bit Timer

13.2.1. Introduction and Features
The controller comprises a Timer block with 3 Timer modules. Each of those Timer module is identical and can
work in one of the following main function modes:
 Single 16-bits auto-reload timer
 Dual 16-bits timer compare
 Dual 16-bits timer capture
 16-bits timer compare and capture
 Single 16-bits pulse accumulator
 Programmable single input debouncer

The Timer block is used in association with the MLX16X8. According to the selected mode the block generates
one digital output signal and up to 5 edges sensitive interrupt signals.

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A programmable and reset-able 16-bits synchronous counter is the principal part of the Timer block; and,
except for the Pulse accumulator mode, a programmable pre-divider fixes the ratio between the clock of this
counter and the input clock frequency.

For each exclusive mode, different parameters are programmable by software:

 In Single 16-bits auto-reload timer mode:
o The pre-divider ratio between the CPU clock and the 16-bits timer clock
 In Dual 16-bits timer, compare mode:
o The pre-divider ratio between the CPU clock and the 16-bits timer clock
o The two values to be compared to the 16-bits timer value
 In Dual 16-bits timer capture:
o The pre-divider ratio between the CPU clock and the 16-bits timer clock
o The active edge of each channel: Rising, Falling, or Rising and Falling
 In 16-bits timer compare and capture mode:
o The pre-divider ratio between the CPU clock and the 16-bits timer clock
o The value to be compared to the 16-bits timer value
o The active edge of the capture channel: Rising, or Falling, or Rising and Falling
 In Single 16-bits pulse accumulator mode:
o The active edge: Rising, or Falling, or Rising and Falling
 In Programmable single input debounce mode:
o The debounce delay

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13.2.2. Block diagram and description

The functional block diagram of the Timer module is shown in Figure 21. The description has been made to
support multiple timer instantiations, in the controller we have only 1 block installed. The “_x” in any of the
names refers to the index of this timer, e.g. “_1”.

Mode selector Channel B

TREGB_x
TIMx_MODE[2:0] Function Channel A
0 0 0 Timer 16 -bit register
TREGA_x
0 0 1 Dual timer compare (TIMx_CAPB / TIMx_CMPB) DATA
0 1 0 Dual timer capture 16-bit register
0 1 1 Timer capture/compare (TIMx_CAPA / TIMx_CMPA) RESET
1 0 0 Pulse accumulator
1 0 1 Debouncer Equalty comparator
1 1 0 unused (EQ)
1 1 1 unused Equalty comparator INTERRUPT
(Tx_EQ) Tx_INT1
Interrupts Tx_INT2
Edge selector block Tx_INT3
Tx_INA (EDGA) selector Tx_INT4
Edge selector INTERRUPT
(Tx_EDGA) Tx_INT5
Tx_INB

INTERRUPT
EN_DIV
PCK DATA
CK Pre-divider 16-bit up counter
RESET

TCNT_x
Control register

TIMx_DIV TIMx_MODE TIMx_ENCMP

DATA
TIMx_OVR TIMx_DOUT TIMx_EDGB

RESET
TIMx_EDGA TIMx_START TIMx_EBLK

TCTRL_x

Figure 21 – Functional diagram of Timer module.

Note:
The symbol ‘x’ reflects the number of the timer module.
The IO port associated to the Control and flag bits, e.g. TIMx_EXT, is the port TCTRL_x.
The IO port associated to the counter value TIMx_CNT is the port TCNT_x.
The IO port associated to the TIMER are the ports TREGA_x and TREGB_x.

The mode in which Timer unit work is defined by the control bits TIMx_MODE[2:0]. All modes use a common
set of hardware -see Figure 21- according to the selected mode:
The hardware is connected or not to the input and output pins.
Up to 5 interrupts signals Tx_INT[5:1] are generated. All interrupt are rising-edge sensitive and high
during one period of the main clock CK

13.2.3. Timer mode

This mode allows the block to generate an interrupt Tx_INT4, so called INT_TIMER, at fixed intervals.

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EN_DIV TCNT_x
CNT_CK
Pre-divider

CK 16-bit up counter

RST

TIMx_CNT 16
TX_INT1
2 Tx_INT2
unused
TIMx_OUT_GE Greater or Equal comparator INT_TIMER Interrupts Tx_INT3
(TxGE) block Tx_INT4
INT_TIMER
Tx_INT5
unused
control register
16
TIMx_DIV0
TIMx_START
TIMx_DIV1
TIMx_CMPB
TCTRL_x
TREGB_x
Channel B

Figure 22 – Timer mode block diagram.

The IO port associated to the Compare value TIMx_CMPB is the port TREGB_x.

The counter clock, CNT_CK, is the CPU clock, CK, divided by a pre-defined number, TIMx_DIV, being 1, 16 or
256. The counter is incremented on CNT_CK rising edge and a pre-defined comparator value, TIMx_CMPB, is
loaded in the 16-bits IO port TREGB_x.
The comparator output, TIMx_OUT_GE, is set to 1 if the counter value, TIMx_CNT, is bigger than or equal to
TIMx_CMPB. And the counter will be reset to ‘0000h’ on the next CK rising edge.
An interrupt, Tx_INT4=INT_TIMER, is generated if the counter reaches the pre-defined comparator value,
TIMx_CMPB.

Assuming TIMx_CMPB<>0x0000, and clock enabled input EN_DIV=1, the period, TINT_TIMER, of the interrupt
signal INT_TIMER is given by the following equations:

Fck
Equation 6 FCNT_CK 
TIM x_DIV
TIMx_DIV
Equation 7 TINT_TIMER    TIMx_CMPB 1
Fck

Equation 8 1 Fck 1
FINT_TIMER   
TINT_TIMER TIMx_DIV TIMx_CMPB 1 

Or, if the comparator value TIMx_CMPB is extracted from the equation:

Equation 9  Fck 1 
TIMx_CMPB    1
 TIMx_ DIV FINT _ TIMER 

Where: Fck is the frequency of the CPU clock,

FCNT_CK is the frequency of the 16-bits up counter, and
TIMx_DIV = 1, 16, or 256.

If TIMx_CMPB=0x0000 the interrupt signal, INT_TIMER is frozen to 1.

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13.2.4. Dual Timer Compare mode

Channel A TREGA_x
TIMx_CMPA

16

Greater or Equal comparator INT_CMPA

(TxGE)
EN_DIV
Tx_INT1 unused
CK Pre-divider Tx_INT2
TIMx_CNT 16 TCNT_x INT_CMPA
Interrupts Tx_INT3
CNT_CK unused
block Tx_INT4
16-bit up counter INT_CMPB
RST Tx_INT5
unused
TIMx_CNT 16

TIMx_OUT_GE Greater or Equal comparator INT_CMPB

(TxGE)

control register
16
TIMx_START TIMx_ENCMP
TIMx_CMPB
TCTRL_x
TREGB_x
Channel B

Figure 23 – Dual timer compare block diagram.

The IO ports associated to the Compare values TIMx_CMPA and TIMx_CMPB are the ports TREGA_x and
TREGB_x.

This mode uses the 16-bits counter as a free running counter. The counter clock, CNT_CK, is the CPU clock, CK,
divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256 – see paragraph 13.2.9. The counter is
incremented on the CNT_CK rising edge.
Two pre-defined comparator values, TIMx_CMPA and TIMx_CMPB, are loaded in the 16-bits IO ports TREGA_x
and TREGB_x.

An interrupt, Tx_INT2=INT_CMPA, is generated when the counter value is equal to the pre-defined comparator
value TIMx_CMPA.
The programmed time for this interrupt signal, TINT_CMPA, is given by the following equation:

TIMx_DIV
Equation 10 TINT_CMPA   TIMx_CMPA 1
Fck
Where: Fck is the frequency of the CPU clock, and
TIMx_DIV = 1, 16, or 256.

The same equation matches for the interrupt Tx_INT4=INT_CMPB with its compare value TIMx_CMPB.

The reset of the 16-bits counter is controlled with the control bits TIMx_ENCMP and TIMx_START.
 If TIMx_ENCMP is set to 1, the 16-bits counter is reset when its value reaches the comparator value
TIMx_CMPB.
 If TIMx_ENCMP is set to 0, the 16-bits counter will be reset when the maximum counting value 0xFFFF
is reached.

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13.2.5. Dual Timer Capture mode

13.2.5.1. Functional block diagram

Channel A INT_CAPA

Tx_INA = IN_CAPA TREGA_x

Edge selector OVRA
TIMx_CAPA
CK (TxEDGA)
TIMx_CNT 16

EN_DIV TCNT_x
CNT_CK
CK Pre-divider INT_OVF
16-bit up counter
RST Tx_INT1
INT_CAPA
control register Tx_INT2
OVRA
TIMx_EDGB1 TIMx_EDGA1 Interrupts Tx_INT3
TIMx_START INT_OVF
TIMx_EDGB0 TIMx_EDGA0 block Tx_INT4
TIMx_CNT OVRB
TCTRL_x 16 Tx_INT5
INT_CAPB

Tx_INB = IN_CAPB
Edge selector OVRB
TIMx_CAPB
CK (TxEDGB)
TREGB_x
INT_CAPB

Channel B

Figure 24 – Dual timer capture block diagram.

The IO ports associated to the Capture values TIMx_CAPA and TIMx_CAPB are the ports TREGA_x and TREGB_x.

This mode uses the 16-bits counter as a free running counter. The counter clock, CNT_CK, is the CPU clock, CK,
divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256 – see paragraph 13.2.9. The counter is
incremented on the CNT_CK rising edge.
The input signal, IN_CAPA, is sampled by CPU clock, CK, and when an event is detected on channel A:
The content of the free-running counter TIMx_CNT is saved in the 16-bits IO port TREGA_x,
An interrupt, Tx_INT1=INT_CAPA, is generated.
The edge selector can be programmed with the control bits TIMx_EDGA[1:0] to detect the following events:
rising, falling, or rising and falling edges.

The input signal, IN_CAPB, is also sampled by CPU clock CK, and when an event is detected on channel B:
The content of the free-running counter is saved in the 16-bits IO port TREGB_x,
An interrupt, Tx_INT5=INT_CAPB, is generated.
The edge selector can be programmed with the control bits TIMx_EDGB[1:0] to detect the following events:
rising, falling, or rising and falling edges.

An interrupt, Tx_INT3=INT_OVF, is generated when the counter overflows, i.e. reaches the values 65535. Using
this interrupt the counter length can be extended by software.
The interrupt signals, Tx_INT2=OVRA and Tx_INT4=OVRB, respectively controlled by channel A and B, are
generated if two consecutive capture actions occur without CPU reading operation in between. The first value
memorized in the corresponding port is not overwritten. Beware on interrupt management (priority, clear
pending operation) because up to 5 interrupt can be generated in the same time.

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13.2.5.2. Output signals

The functionality of the Timer unit in Capture mode is summarized Table 29.

TIMx_STA
INT_CAPA / OVRA INT_CAPB / OVRB NOTES
RT
event event CPU
detected (1) detected (1) read
(1) According to
the
INT_CAPA
1 - programming of
the edge
OVRA
selector EDGA.
TIMx_CAPA TIMx_CAPA
updated not updated

event event CPU

detected (2) detected (2) read
(2) According to
the
INT_CAPB
1 - programming of
the edge
OVRB
selector EDGB.
TIMx_CAPB TIMx_CAPB
updated not updated

- Timer Capture
INT_CAPA INT_CAPB
0 stay endlessly to '0' 0 stay endlessly to '0'
mode disabled
0
OVRA
0 stay endlessly to '0'
OVRB
0 stay endlessly to '0'
- 16-bits counter
0 0 reset to 0000h.
Table 29 – Timer capture output signals.

13.2.5.3. Usage and example

Typical usage: Time stamping events.

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13.2.6. Timer Capture/Compare mode

13.2.6.1. Functional block diagram
Channel A
TREGA_x
TIMx_CMPA

16

Equality comparator INT_CMPA

(TxEQ)

TIMx_CNT 16
EN_DIV
CNT_CK
CK Pre-divider
16-bit up counter INT_OVF
RST Tx_INT1 unused
control register Tx_INT2
TCNT_x INT_CMPA
TIMx_EDGB1 Interrupts Tx_INT3
TIMx_START INT_OVF
TIMx_EDGB0 TIMx_CNT 16 block Tx_INT4
OVRB
2 TCTRL_x Tx_INT5
INT_CAPB
IN_CAP2
Edge selector OVRB
CK TIMx_CAPB
(TxEDGB)
TREGB_x INT_CAPB

Channel B

Figure 25 – Timer compare/capture block diagram.

Note:
The symbol ‘x’ should be replaced by ‘1’, ‘2’ or ‘3’ depending on the Timer speaking about.
The IO port associated to the Compare value TIMx_CMPA is the port TREGA_x.
The IO port associated to the Capture value TIMx_CAPB is the port TREGB_x.

Compare Channel A
This mode uses the 16-bits counter as a free running counter. The counter clock, CNT_CK, is the CPU clock, CK,
divided by a pre-defined number, TIMx_DIV, being 1, 16 or 256 – see paragraph 13.2.9. The counter is
incremented on the CNT_CK rising edge.
Assuming bit TIMx_START is high, the 16-bits counter is reset when its value reaches the maximum counting
value 0xFFFF.
An interrupt, Tx_INT1=INT_CMPA, is generated when the counter value TIMx_CNT is equal to the pre-defined
comparator value TIMx_CMPA.
The programmed time for this interrupt signal, TINT_CMPA, is given by the following equation:

TIMx_ DIV
Equation 11 TINT_CMPA   TIMx_ CMPA  1
Fck
Where: Fck is the frequency of the CPU clock, and
TIMx_DIV = 1, 16, or 256.

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As long as the bit TIMx_START is not set to 0, the counting sequence is repeated indefinitely; and the frequency
at which the interrupt signals is generated is given by Equation 12:

Fck 1
FOUT  
Equation 12 TIMx_ DIV 65536

Capture Channel B
The input signal, IN_CAPB, is sampled by CK, and when an event is detected on channel input B:
The content of the free-running counter is saved into the 16-bits IO port TREGB_x,
An interrupt, Tx_INT5=INT_CAPB, is generated.

The edge selector can be programmed with the control bit TIMx_EDGB[1:0] to detect the following events:
rising, falling, or rising and falling edges.

An interrupt, Tx_INT3=INT_OVF, is activated when the counter overflows. The counter length can be extended
by software using this interrupt.
The interrupt signal, Tx_INT4=OVRB, is generated if two consecutive capture actions occur without CPU reading
operation in between. The first value TIMx_CAPB, memorized in port TREGB_x, is not overwritten.

13.2.6.2. Output signals

The functionality of the Timer unit in Compare/Capture mode is summarized Table 30.

TIMx_S
INT_CMPA INT_CAPB / OVRB NOTES
TART

DIV
TINT_CMPA FOUT
TINT_CMPA   TIMx_ CMPA  1
Fck
1 INT_CMPA
- Fck 1
FOUT  
0 TIMx_CMPA 65535 TIMx_ DIV 65536

event event CPU

detected (2) detected (2) read

INT_CAPB (2) According to the programming

1 -
of the edge selector EDGB.
OVRB

TIMx_CAPB TIMx_CAPB
updated not updated

INT_CAPB
0 stay endlessly to '0'
- Timer Compare/Capture mode
0 INT_CMPA stay endlessly to '0'
disabled
OVRB
0 stay endlessly to '0'
0 CMPA 65535 0
- 16-bits counter reset to 0000h.
Table 30 – Timer Compare/Capture output signals.

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13.2.7. Pulse accumulator mode

13.2.7.1. Functional block diagram
EN_DIV Tx_INT1
TCNT_x
Tx_INT2 unused
Tx_INA = IN_ACC Edge Setector CNT_CK
INT_OVF Tx_INT3
(TxEDGA) Interrupts INT_OVF
CK 16-bit up counter block Tx_INT4
RST
Tx_INT5 unused
2
control register
TIMx_EDGA1
TIMx_START
TIMx_EDGA0
TCTRL_x

Figure 26 – 16-bits pulse accumulator block diagram.

Note:
The symbol ‘x’ should be replaced by ‘1’, ‘2’ or ‘3’ depending on the Timer.

This mode uses the 16-bits counter as an event counter. The clock of the counter CNT_CK is the CPU clock, CK,
controlled by EN_DIV – see paragraph 13.2.9.
The input signal, IN_ACC, is sampled by CK when input EN_DIV is high, and when an event is detected the
counter is incremented by 1. The edge selector can be programmed to detect the following events on IN_ACC:
rising, falling, or rising and falling edges.

If the control bit TIMx_START is low the Pulse accumulator mode is disabled and output INT_OVF is frozen to 0.
An interrupt, Tx_INT3=INT_OVF, is generated when the counter overflows, i.e. value 65535 is reached. Using
this interrupt the counter length can be extended by software. This interrupt signal must be connected to a
rising-edge sensitive interrupt inputs.

13.2.7.2. Output signals

The input to monitor, IN_ACC, passes through an edge selector block that can be programmed to detect the
following events:
Rising edges
Falling edges
Rising and falling edges
The active edge is selected with the control bits TIMx_EDGA1 and TIMx_EDGA0.

TIMx_EDGA1 TIMx_EDGA0 TIMx_CNT = TIMx_CNT + 1

0 0 on no edge.
0 1 on IN_ACC falling edge.
1 0 on IN_ACC rising edge.
on IN_ACC rising and falling
1 1
edge.
Table 31 – Control bit for edge selector.

13.2.7.3. Usage and example

Typical usage: Event counting (integrator, frequency measure, etc…)

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13.2.8. Debouncer mode

13.2.8.1. Functional block diagram
EN_DIV TCNT_x
CNT_CK
CK Pre-divider
RST 16-bit up counter

Edge selector
IN_DEB
(TxEDGB) R/S

TIMx_OUT_GE Greater or Equal

comparator (TxGE)
Tx_INT1
16
Tx_INT2
unused
Interrupts Tx_INT3
block Tx_INT4
TIMx_CMPB INT_EDGF
Tx_INT5
TREGB_x INT_EDGR
control register TCTRL_x
TIMx_DIN1
TIMx_START FREEZE INT_EDG
TIMx_DIN0

2
Output Block Tx_OUT_DEB
internal debounced helper signal

Figure 27 – Debouncer block diagram.

The IO port associated to the Compare value TIMx_CMPB is the port TREGB_x.

This mode uses the 16-bits counter as delay counter. The counter clock, CNT_CK, is the CPU clock, CK, divided
by a pre-defined number, TIMx_DIV, being 1, 16 or 256 – see paragraph 13.2.9. The counter is incremented on
the CNT_CK rising edge.

A pre-defined comparator value, TIMx_CMPB, is loaded in the 16-bits IO port TREGB_x and defines the
debounce delay. The equality comparator output, TIMx_OUT_GE, is set to 1 when the counter reaches this
value; and an R/S block manages the freeze control of the internal debounced helper signal Tx_OUT_DEB.

This edge selector is programmed to detect rising and falling edges. By using the two control bits, TIMx_DIN1
and TIMx_DIN0, the debounce method can be changed. The bits TIMx_DIN select the time at which the falling
and/or rising edge detection are displayed on output INT_EDGF and INT_EDGR (i.e. immediately or delayed by
the debounce delay counter).
So when a rising edge is detected on Tx_OUT_DEB
An interrupt, Tx_INT4= INT_EDGR, can be generated immediately or after the debounce delay counter
And when a falling edge is detected on Tx_OUT_DEB
An interrupt,Tx_INT5 INT_EDGF, can be generated immediately or after the debounce delay counter

If the control bit TIMx_START is low, the Debouncer mode is disabled and outputs INT_EDGR, INT_EDGF and
Tx_OUT_DEB are frozen to 0.

Note: The case where the debounce delay TIMx_CMPB=0000h is to be avoided. If TIMx_CMPB=0000h the
following two cases are defined:
if TIMx_DIN1 = TIMx_DIN0 = 1, then Tx_OUT_DEB is equal to IN_DEB delayed by one period of CK, and
if TIMx_DIN1 = TIMx_DIN0 = 0 then Tx_OUT_DEB is equal to IN_DEB delayed by two periods of CK.

13.2.8.2. Output signals

The pre-divider is controlled with bits TIMx_DIV1 and TIMx_DIV0.
Assuming the bit TIMx_START is high, the functionality of the two bits, TIMx_DIN1 and TIMx_DIN0, in the
control port TCTRL_x is described in Table 32.

The input signal, IN_DEB, is sampled by CK, and when a rising or falling edge is detected the output value,
Tx_OUT_DEB, is frozen to 0 or 1, until the programmed delay is reached.
An interrupt signal is generated each time Tx_OUT_DEB toggle.

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Particular case, if the debounce delay is shorter than the bouncing period: The signal Tx_OUT_DEB will change
according to the bits TIMx_DIN and to the state of the input IN_DEB after the debounce delay counter. The
rules are the same than for the standard case, see Table 32.

TIMx_DIN1 TIMx_DIN0 IN_DEB / Tx_OUT_DEB / INT_EDGR / INT_EDGF

DELAY DELAY

IN_DEB

0 0
Tx_OUT_DEB

INT_EDGR

INT_EDGF

DELAY DELAY

IN_DEB

Tx_OUT_DEB
0 1
INT_EDGR

INT_EDGF

DELAY DELAY

IN_DEB

Tx_OUT_DEB
1 0
INT_EDGR

INT_EDGF

DELAY DELAY

IN_DEB

1 1 Tx_OUT_DEB

INT_EDGR

INT_EDGF

Table 32 – Debounce method selection.

13.2.8.3. Usage and example

Typical usage: Switch debounce

13.2.9. Timers IO ports

The update of the IO ports must be done when the control bit TIMx_START is low.

All the IO ports involved in a single timer module (TIMER_x) programming are summarized below:
The Data ports TREGA_x and TREGB_x,
The Control port TCTRL_x, and
The Counter port TCNT_x.

According to the selected Timer mode –see previous paragraphs-, the data saved in the port
TREGA_x is referred as the compare value TIMx_CMPA, or as the capture value TIMx_CAPA.
TREGB_x is referred as the compare value TIMx_CMPB, or as the capture value TIMx_CAPB.

For detailed address location please refer to the ports map description chapter.

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IO port: TMR1_REGA, TMR2_REGA, TMR3_REGA

Address: 0x282E, 0x2836, 0x283E Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
TIMA_REGA[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

TIMA_REGA[15:8]
TIMx_REGA[15:0]: Data for the channel A of Timer_x; only accessible in Word
Table 33 – Timer ports – data port for channel A.

IO port: TMR1_REGB, TMR2_REGB, TMR3_REGB

Address: 0x282C, 0x2834, 0x283C Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
TIMx_REGB[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

TIMx_REGB[15:8]
TIMx_REGB[15:0]: Data for the channel B of Timer_x; only accessible in Word
Table 34 – Timer ports – data port for channel B.

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IO port: TMR1_CTRL, TMR2_CTRL, TMR3_CTRL

Address: 0x282A, 0x2832, 0x283A Access mode: Word, Byte, Bit – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
TIMx_DIN[1:0] TIMx_EDGB[1:0] TIMx_EDGA[1:0] TIMx_START TIMx_EBLK

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

TIMx_DIV[1:0] TIMx_MODE[2:0] TIMx_ENCMP TIMx_OVRB TIMx_OVRA
Predivider ratio between CPU clock and Timer counter clock. This selector is use in all Timer
TIMx_DIV[1:0]: modes except in the Pulse accumulator mode.
00 = div by 1 01 = div by 16 10 = div by 256
Mode selector.
000 = Timer mode 100 = Pulse accumulator mode
TIMx_MODE[2:0]: 001 = Dual timer compare 101 = Debouncer mode
010 = Dual timer capture
011 = Timer capture/compare
Enable comparison to reset timer value. This enable bit is use in Dual timer mode only.
TIMx_ENCMP: 0 = counter is reset when ‘FFFFh’ is reached
1 = counter reset when the value TIMx_REGB is reached
Overrun flag for the channel B; indicates to consecutive capture action on channel B, without
CPU reading operation between. This flag is use in Dual timer capture or in capture/compare
TIMx_OVRB: mode.
0 = a capture action set TIMx_REGB with current counter value.
1 = all future capture action masked until reading capture value
Overrun flag for the channel A. Indicates to consecutive capture action on channel A, without
CPU reading operation between. This flag is use in Dual timer capture mode.
TIMx_OVRA:
0 = a capture action set TIMx_REGA with current counter value.
1 = all future capture action masked until reading capture value
Control bit to fix the debounce method or the output waveform. This selector is used in
TIMx_DIN[1:0]:
Debounce mode.
Edge selector for channel B, to generate a capture event ; This selector is use in Dual capture
and capture/compare mode.
TIMx_EDGB[1:0]:
00 = no capture event 11 = capture event on rising and falling edge
01 = capture event on falling edge 10 = capture event on rising edge
Edge selector for channel A, to generate a capture event; This selector is use in Dual capture
and Pulse accumulator mode.
TIMx_EDGA[1:0]:
00 = no capture event 11 = capture event on rising and falling edge
01 = capture event on falling edge 10 = capture event on rising edge
Enable bit for the selected mode.
TIMx_START: 1 = mode enabled; Timer is working in the selected mode. 0 = mode disabled; output
forced to 0
Enable Timer block
TIMx_EBLK:
1 = Timer module enable 0 = Timer module disabled
Table 35 – Timer ports – control port.

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IO port: TMR1_CNT, TMR2_CNT, TMR3_CNT

Address: 0x2830, 0x2838, 0x2840 Access mode: Word – Read only
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
TIMx_CNT[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

TIMx_CNT[15:8]
TIMx_CNT[15:0]: Current counter value of Timer_x; can only be Read in Word access.
Table 36 – Timer ports – counter value.

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13.2.10. Interrupt connections

The following table summarizes the possible interrupt sources of one timer module in the different modes of
operation.

Interrupt
Mode / output / top level name Interrupt description
name
/ Greater than or equality comparator.
Timer INT_TIMER / Tx_INT4
TMRx_CMPB_IT (TIMx_CNT > TIMx_REGB)
/ Equality comparator. (TIMx_CNT =
INT_CMPA / Tx_INT2
TMRx_CMPA_IT TIMx_REGA)
Dual
Greater than or equal (TIMx_CNT >
Compare
INT_CMPB / Tx_INT4 /TMRx_CMPB_IT TIMx_REGB). Reset TIMx_CNT if control bit
TIMx_ENCMP is high.
Capture signal for channel A. Active edge
INT_CAPA / Tx_INT1 / TMRx_CAPA_IT programmed with the control bit
TIMx_EDGA.
Capture signal for channel B. Active edge
INT_CAPB / Tx_INT5 / TMRx_CAPB_IT programmed with the control bit
Dual TIMx_EDGB.
Capture
/ Overrun on Channel A. Previous interrupt
INT_OVRA / Tx_INT2
TMRx_CMPA_IT INT_CAPA not executed.
/ Overrun on Channel B. Previous interrupt
INT_OVRB / Tx_INT4
TMRx_CMPB_IT INT_CAPB not executed.
INT_OVF / Tx_INT3 / TMRx_OVF_IT Counter overflow. (TIMx_CNT > FFFFh)
/ Equality comparator. (TIMx_CNT =
INT_CMPA / Tx_INT2
TMRx_CMPA_IT TIMx_REGA)
INT_OVF / Tx_INT3 / TMRx_OVF_IT Counter overflow. (TIMx_CNT > FFFFh)
Capture
/ Overrun on Channel B. Previous interrupt
Compare INT_OVRB / Tx_INT4
TMRx_CMPB_IT INT_CAPB not executed.
Capture signal for channel B. Active edge
INT_CAPB / Tx_INT5 / TMRx_CAPB_IT
programmed with TIMx_EDGB.
Pulse
INT_OVF / Tx_INT3 / TMRx_OVF_IT Counter overflow. (TIMx_CNT > FFFFh)
Accumulator
/
INT_EDGF / Tx_INT4 Falling edge detected on Tx_OUT_DEB
Debouncer TMRx_CMPB_IT
INT_EDGR / Tx_INT5 / TMRx_CAPB_IT Rising edge detected on Tx_OUT_DEB
Table 37 – Interrupts functions

The Timer interrupts are connected into MULAN3 external interrupts block.

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14. RC-Oscillator
The digital part of controller is supplied by a RC oscillator, which is trimmed via software according to the ports
map description and NVRAM allocation table.

The RC oscillator starts with power on at VDDA.

The RC oscillator is switched off in SLEEP MODE.

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15. Temperature Detection

There are two different, separate temperature detections implemented:
1. Temperature detection in case of overheating due to internal overload or a too high ambient
temperature
2. Measurement of the on chip temperature with the ADC (see also under the chapter 16 AD converter
system)

1.) In case of over temperature detection the Bit OVT in port ANA_INA (for details see chapter 11.6) is set. This
can create an interrupt, if the corresponding external interrupt source ANA_INA[15] has been activated. With
this interrupt software should reduce the clock frequency and the power consumption of external components
at pin VDDA as much as possible.
It is also useful to switch off parts of the IC to reduce internal power and to protect external devices. This
especially covers output drivers (e.g. pwm, high voltage ...).
There is no automatic shutdown of any parts of the IC.

If the internal temperature falls below the lower threshold (Tot_off) all drivers can be switched on again.
The over-temperature detection circuitry is active after Power On, but can be deactivated separately by the
corresponding bits in the ports map (see ANA_OUTx ports).

2.) During the Melexis wafer test the temperature values for -40 °C, 35 °C and 125 °C are saved into NVRAM 2,
page 2. These values are used as reference points for the on chip temperature sensor.
The reference values are stored at following addresses:

Memory address Description

0x11BD Temperature reference value for 125°C, MSB
0x11BC Temperature reference value for 125°C, LSB
0x11BB Temperature reference value for 35°C, MSB
0x11BA Temperature reference value for 35°C, LSB
0x11B9 Temperature reference value for -40°C, MSB
0x11B8 Temperature reference value for -40°C, LSB
Table 38 – Memory map of temperature reference values

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16. AD converter system

The controller uses a 10Bit ADC with Direct Memory Access. The ADC is running with two address pointers. The
first one is pointing at the channel list. The second pointer is referring to the result list.
The ADC is reading the channel list and transferring the results into the result list without CPU load.

The channel list contains up to 255 entries (channels in words) + delimiter (0xFFFF). The delimiter is signaling
the ADC that the end of the channel list is reached.

C-macros are available in the Software Platform for configuration and start of the ADC.

16.1. ADC Block diagram

Channel
select

VS Channel[0]
TEMP Channel[1]
VDDD Channel[2] SYSTEM CLOCK
DIV
VDDA / 2 Channel[3]
V5V6 / 4 Channel[4]
CLK

VAUX / 2 Channel[5] ANA_OUTE[15:14] OUT

LINAAMP Channel[6]
Channel[7]
LINVCMO
Channel[8..15]
IN
ADC EOC
Trigger
(SOC)

ADC_EOC_SYNC
TMR1_CAPA_IT
HV[0..3] Channel[16..19]
Ref

TMR1_CAPB_IT
HVIODIFFx Channel[20] TMR1_CMPA_IT
TMR1_CMPB_IT
PWM4_CMPI TRIG_SRC
PWM3_CMPI
PWM2_CMPI
Trigger

VRH3
select

PWM1_CMPI
PWM4_CNTI VRH2
PWM3_CNTI
VRH1 to ADC Interrupt
PWM2_CNTI
select

PWM1_CNTI SOFT_TRIG
Ref

RAM RAM
Transfer0 Transfer0
Config 0 Read Write SIN[3:0] SREF[7:4] SREF[1:0] Read Write Sample 0
Config 1 Sample 1
DMA request ADC control unit DMA request
... fe
r N ...
ns Address SBASE counter DBASE counter Address Tr
Tr
a a
ns
... fer
N ...
DMA channel DMA channel
Config N Sample N
ADC_SBASE[15:0] ADC_DBASE[15:0]
16bits 16bits
LOOP
START
SREF SREF
SIN[3:0] ADC[9:0]
[7:4] [1:0]
Input Hardware reference ADC result
channel trigger voltage

BIT[15] BIT[0] BIT[15] BIT[0]

Figure 28 – AD converter overview illustrating control including DMA and channel multiplexing

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16.2. ADC control and command ports

There are 5 configuration ports in the ADC interface:
 ADC_CONTROL port: control bits.
 ADC_SBASE: base address for input channel and reference voltage.
 ADC_DBASE: base address for conversion results.
 ANA_OUTE port: ADC conversion frequency and trim value for ADC reference voltage 2.5V
 ANA_OUTD port: trim value for ADC reference voltage 0.75V and 1.5V

Each port is 16-bits wide and accessible by bytes or words.

At reset, the control register is 0, ADC_SBase and ADC_DBase are undefined.

During the power-up procedure (low_level_init.c: low_level_init) the initialization of ADC trimming register will
be executed. So there is no need to do a re-initialization of the ADC trimming register.

IO port: ADC_SBASE
Address: 0x2812 Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
ADC_SBASE[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

ADC_SBASE[15:8]
Base address for SIN (input channel) and SREF (reference voltage) storage. Address range is
ADC_SBASE[15:0]: limited to RAM
000b $ADC_SEL[4:0], $ADC_TRIG[3:0] 00b $ADC_REF[1:0]
Table 39 – ADC Interface – ADC Mux, Reference and Trigger source selection

IO port: ADC_DBASE
Address: 0x2814 Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
ADC_DBASE[7:0]

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

ADC_DBASE[15:8]
ADC_DBASE[15:0]: base address for conversion results
Table 40 – ADC Interface – Base addresses for results

IO port: ADC_CTRL
Address: 0x2810 Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
ADC_SYNC_
- - LOOP TRIG_SRC START
SOC

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

ADC_EOC_S
SOFT _TRIG
YNC
Signalize that the ADC is running or not.
0 .. ADC is stopped
START
1 .. ADC is busy

Set ADC trigger source to HW or SW

TRIG_SRC 0 .. SW trigger
1 .. HW trigger

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Single or continuous ADC conversion

LOOP 0 .. single cycle of ADC conversion -> one time complete channel list
1 .. continuous cycles of ADC conversion -> ADC conversion never stops

Set if first ADC conversion is valid or not.

ADC_SYNC_SOC 0 .. first ADC conversion result is thrown away in case of HW trigger
1 .. first ADC conversion result is valid in case of HW trigger
When TRIG_SRC is 0 (software trigger selected), a conversion starts when this bit is
set.
SOFT_TRIG
This bit is automatically reset after a start of conversion. One write access to the bit
will start the conversion of next configured ADC channel.
Synchronized End Of Conversion signal from the ADC.
ADC_EOC_SYNC This signal can be used to see if the current conversion is finished before starting a
new one. (i.e. it will be set for each conversion in a conversion cycle)
Table 41 – ADC interface ports – Control register.

IO port: ANA_OUTE
Address: 0x204C Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Melexis
TR_ADCREF3
reserved

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

ADCFREQ Melexis reserved
TR_ADCREF3 Trimming values for ADC reference voltage 2.5V
ADC conversion frequency
00 – 2MHz
ADCFREQ 01 – 1MHz
10 – 3MHz
11 – 4MHz
Table 42 – ADC configuration Register ANA_OUTE

IO port: ANA_OUTD
Address: 0x204A Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Melexis
TR_ADCREF1
reserved

Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]

TR_ADCREF2
TR_ADCREF1 Trimming values for ADC reference voltage 0.75V
TR_ADCREF2 Trimming values for ADC reference voltage 1.5V
Table 43 – ADC configuration Register ANA_OUTD

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16.3. ADC Channel selection Guide

ADC_SIN[4:0] Settling
Source Input Remark
CH time
voltage range
4 3 2 1 0
Internal high ohmic divider 1:14
0 0 0 0 0 0 VS 0 .. 14*VRHx 5us
[1]
0 0 0 0 1 1 TEMP internal Internal temperature sensor 5us
0 0 0 1 0 2 VDDD internal Digital supply voltage 5us
Analogue supply voltage, divided
0 0 0 1 1 3 VDDA/2 internal 5us
by 2
Analogue supply voltage 5.6V,
0 0 1 0 0 4 V5V6/4 internal 5us
Divided by 4
Auxiliary analogue supply voltage,
0 0 1 0 1 5 VAUX/2 internal 100us
divided by 2
0 0 1 1 0 6 LINAAMP internal LIN autoconfig amplifier output 10us
LIN autoconfig common mode
0 0 1 1 1 7 LINVCMO internal 10us
voltage
Offset calibration for ground
0 1 0 0 0 8 HV[4] related differential measurement
[2]
Ground related differential
0 1 0 0 1 9 HV[5]-HV[4]
measurement [2]
0 1 0 1 0 10
0 1 0 1 1 11
0 1 1 0 0 12
0 1 1 0 1 13 HV[3] 0 .. 4*VRHx[3] with internal divider 1:4 [1] 10us
0 1 1 1 0 14 HV[4] 0 .. 4*VRHx[3] with internal divider 1:4 [1][2] 10us
0 1 1 1 1 15 HV[5] 0 .. 4*VRHx[3] with internal divider 1:4 [1][2] 10us
1 0 0 0 0 16 HV[0] 0 .. 4*VRHx[3] with internal divider 1:4 [1] 10us
1 0 0 0 1 17 HV[1] 0 .. 4*VRHx[3] with internal divider 1:4 [1] 10us
1 0 0 1 0 18 HV[2] 0 .. 4*VRHx[3] with internal divider 1:4 [1] 10us
1 0 0 1 1 19 HV[3] 0 .. 2*VRHx[3] with internal divider 1:2 [1] 10us
Difference:
VRHx - ((VS - VHV) / 5)
1 0 1 0 0 20 HVIODIFF[x] VS .. VS-VRHx 10us
VHV - input voltage on HVx pin
VRHx - reference voltage
HVDIFF=
1 0 1 0 1 21 HVIODIFF[0] VS .. VS-HVDIFF 10us
VRHx - ((VS – HV[0]) / 5) [3][4]
HVDIFF=
1 0 1 1 0 22 HVIODIFF[1] VS .. VS-HVDIFF 10us
VRHx - ((VS – HV[1]) / 5) [3][4]
HVDIFF=
1 0 1 1 1 23 HVIODIFF[2] VS .. VS-HVDIFF 10us
VRHx - ((VS – HV[2]) / 5) [3][4]
HVDIFF=
1 1 0 0 0 24 HVIODIFF[3] VS .. VS-HVDIFF 10us
VRHx - ((VS – HV[3]) / 5) [3][4]
HVDIFF=
1 1 0 0 1 25 HVIODIFF[4] VS .. VS-HVDIFF 10us
VRHx - ((VS – HV[4]) / 5) [2][3][4]
HVDIFF=
1 1 0 1 0 26 HVIODIFF[5] VS .. VS-HVDIFF 10us
VRHx - ((VS – HV[5]) / 5) [2][3][4]
Table 44 – ADC channels selection

[1] Accuracy of internal resistor dividers is in the range of 2%

[2] Channel exists for MLX81115 only

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[3] ADC Reference Voltage

[4] Hardware Trigger for ADC conversion implemented

16.4. ADC Reference Voltage and Hardware Trigger Selection

The reference voltages are selected by ADC_REF[1:0] as follows:

ADC_REF[1:0] Reference voltage VRHx

3 2.50
2 1.50
1 0.75
0 off
Figure 29 – ADC Reference voltage selection

The hardware trigger sources are selected by the bits ADC_REF[7:4] (see Table 45).
In case of ADC Channel [26:21] become selected: The chosen ADC Trigger from table below is pre-processed by
SC Filtering Circuit and forwarded as DMA trigger after <counter time> delay – see IO-map SC counter values.
The counter time shall delay the ADC trigger into the on-time of the PWM duty cycle. For each of the different
RGB channels a separate <counter time> can be used.

ADC_REF[7:4] ADC trigger from

16 SC_HW_TRIG
15 PWM6_CMPI enable PWM6 compare interrupt as ADC trigger
14 PWM5_CMPI enable PWM5 compare interrupt as ADC trigger
13 PWM6_CNTI enable PWM6 counter interrupt as ADC trigger
12 PWM5_CNTI enable PWM5 counter interrupt as ADC trigger
11 TMR1_CAPA_IT Capture Interrupt channel A
10 TMR1_CAPB_IT Capture Interrupt channel B
9 TMR1_CMPA_IT Compare Interrupt channel A
8 TMR1_CMPB_IT Compare Interrupt channel B
7 PWM4_CMPI enable PWM4 compare interrupt as ADC trigger
6 PWM3_CMPI enable PWM3 compare interrupt as ADC trigger
5 PWM2_CMPI enable PWM2 compare interrupt as ADC trigger
4 PWM1_CMPI enable PWM1 compare interrupt as ADC trigger
3 PWM4_CNTI enable PWM4 counter interrupt as ADC trigger
2 PWM3_CNTI enable PWM3 counter interrupt as ADC trigger
1 PWM2_CNTI enable PWM2 counter interrupt as ADC trigger
0 PWM1_CNTI enable PWM1 counter interrupt as ADC trigger
Table 45 – ADC Hardware trigger selection

16.5. Hardware SC filter triggered RGB channels

For AD conversion of Channels <31:26> - a SC filter circuit is implemented. Before starting the ADC, the SC Filter
is controlled in a defined way to prepare the AD input signal.

16.6. ADC result list format

ADC result list format
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 10 Bit ADC result (0 – 1023 -> 0x0 – 0x3FF)
Table 46 – ADC result format

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16.6.1. Calculation Instruction for the measured Input Voltage

[ ]

Where
 VRHx is the reference voltage (see Figure 29)
 Divider is the input divider of the ADC channel (see Table 44)

16.6.2. Accuracy of the HVIODIFFx Input Channel

The HVIODIFFx input channel can only be used in the below specified accuracy ranges (2% and 5%) for VS ≥
8.5V. Depending on the selected ADC reference voltage VRHx the input voltage range is defined as shown in
Table 47.

Accuracy VRHx HVIODIFFx Input Voltage Range

Min. Max.
2% >1.25V VS-3.7V VS-1.5V
(for monitoring) ≤1.25V VS-3.7V VS-(1.25V-VRHx)*5
5% >1.25V VS-4V VS
(for diagnostic) ≤1.25V VS-4V VS-(1.25V-VRHx)*5
Table 47 – Accuracy of the HVIODIFFx Input Channel

16.7. Trimming of ADC reference voltage

The trimming of the ADC reference voltage is done at start-up of the IC via low level routines. It is not necessary
to trim it in the application.

16.8. ADC conversion time

The ADC can run with different clock speeds which are shown in the following table:

ANA_OUTE address: 0x204C

ADC frequency conversion time
Bit15 Bit14
0 0 2 MHz (default) 6us
0 1 1 MHz 12us
1 0 3 MHz 4us
1 1 4 MHz 3us
Table 48 – ADC conversion time

16.9. Stopping the ADC conversion

The ADC is stopped when the ADC_START bit is ‘0’. In case this bit is ‘1’ the ADC is busy with a conversion, DMA
transfer or waiting for the next event.

For stopping the ADC following steps have to be done:

1. Don’t stop the generation of the ADC triggers. Otherwise the ADC_START bit will never be cleared.

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2. Turn-off the LOOP bit to stop the infinite conversion. Otherwise it will never end.
3. Wait until the ADC_START bit is cleared.
4. The ADC_CTRL port can be set to 0 in case the ADC_START bit is cleared.

Code-Example:

/* stop the current ADC action */

ADC_INT_DISABLE(); /* disable ADC interrupt */
ADC_CTRL &= ~(ADC_LOOP | ADC_TRIG_SRC | ADC_SYNC_SOC);
/* set single cycle conversion */
/* and set trigger source to */
/* software trigger */

while ( (ADC_CTRL & ADC_START) == ADC_START ) {

/* In case ADC is active, wait */
/* to finish it */
ADC_CTRL |= ADC_SOFT_TRIG; /* start next conversion */
/*using the software trigger */
}/*while*/

16.10. Disabling the ADC

The ADC can be disabled which reduces the current consumption about ~0.5mA.
Therefore the ADC should be loaded with a channel which contains 0V as ADC reference voltage.
The ADC will be disabled by starting it with such a channel.

Code-Example:
uint16 adcRes[1] = {0};
uint16 adcOff[2] = {0x0000, 0xFFFF};

ADC_SBASE = (uint16) &adcOff;

ADC_DBASE = (uint16) &adcRes;
ADC_SELECT_ADCFREQ(ADC_SET_FREQ_2MHZ); /* set default ADC frequency */
ADC_CTRL = ADC_START;
MLX8110x_USEC_DELAY(10); /*10us*/
ADC_CTRL = 0;

16.11. Measuring the chip temperature

The temperature measurement can be used for watching temperature drifts in the system.
For temperature measurement three calibration points can be used. During the production test the measured
ADC values at -40°C, 35°C and 125°C will be saved to the NVRAM. The used ADC reference voltage is 2.5V.

Please also refer to package Rth data if approximation of ambient temperature is needed.

NVRAM Address Remark

0x11B8 ADC value measured at -40°C
0x11BA ADC value measured at 35°C
0x11BC ADC value measured at 125°C
Table 49 – NVRAM Position of the calibration data for temperature measurement

To calculate the temperature from an ADC value a linear abstraction can be used. With this approach following
software example can be used:

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#define SCALE_FACTOR 5 /* 2^5 -> 32 -> used for scaling

temperature via fixpoint arithmetic */

#define LOWTEMP -40 /* low temperature */

#define HIGHTEMP 125 /* high temperature */
#define MIDTEMP 35 /* middle temperature */

extern volatile uint16 EEP_mTempHigh __attribute__((nodp, addr(0x11BC)));

/* Raw ADC value of internal temperature sensor @125C (measured with 2.5V
ADC reference voltage)*/
extern volatile uint16 EEP_mTempMid __attribute__((nodp, addr(0x11BA)));
/* Raw ADC value of internal temperature sensor @35C (measured with 2.5V
ADC reference voltage)*/
extern volatile uint16 EEP_mTempLow __attribute__((nodp, addr(0x11B8)));
/* Raw ADC value of internal temperature sensor @-40C (measured with 2.5V
ADC reference voltage)*/

/* calculate linear dependency of internal temperature sensor */

hightemp_m = ((int16)(((int16)EEP_mTempHigh - (int16)EEP_mTempMid) <<
SCALE_FACTOR) / (int16)((int16)HIGHTEMP - (int16)MIDTEMP));
hightemp_b = (int16)(EEP_mTempMid << SCALE_FACTOR) - (hightemp_m *
MIDTEMP);

lowtemp_m = ((int16)(((int16)EEP_mTempMid - (int16)EEP_mTempLow) <<

SCALE_FACTOR) / (int16)((int16)MIDTEMP - (int16)LOWTEMP));
lowtemp_b = (int16)(EEP_mTempMid << SCALE_FACTOR) - (lowtemp_m *
MIDTEMP);

/* check if the temperature is above 35C */

if (EEP_mTempMid > adcValue) {
internalTemperature = ((int16)((adcValue <<
(int16)SCALE_FACTOR) - hightemp_b) / hightemp_m);
}else {
internalTemperature = ((int16)((adcValue <<
(int16)SCALE_FACTOR) - lowtemp_b) / lowtemp_m);
}

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17. Digital Watchdog

17.1. Introduction and features
The MULAN3 core contains a separate watchdog (WD) running on a 250 kHz clock derived from the MULAN3
main clock.
It can work in one of the following main modes:
 Simple timer Watchdog
 Window Watchdog
 Intelligent Watchdog

The timeout delays programmable in wide range by using a clock pre-divider

The WD outputs are only interrupts.

17.2. Applications
The Watchdog block is used in association with the MLX16. According to the selected mode the block waits for a
MLX16 acknowledgement between different time limits, or else a System reset interrupt is generated.
A MLX16 acknowledgement resets the internal WD counter.

 In the Simple Timer mode:

the Watchdog is a reset-able free-running up counter. The acknowledge signal should appear before
the internal WD counter reaches a predefined timeout value.

 In Window mode:
the Watchdog is a reset-able free-running up counter. The acknowledge signal should appear only
within a time window starting at half of the predefined timeout value.

 In Intelligent Watchdog mode:

the Watchdog can have its counter programmed with different values. When the predefined timeout
value is reached, an WD attention interrupt is generated, and then a new waiting sequence starts. The
acknowledge signal should appear before the end of this second sequence.

The WD attention interrupt and the System reset interrupt will be used by the software.

17.3. Block diagram and description

The functional block diagram of the Watchdog block is shown in Figure 30.

WD_MODE WD_TO
WD_DIV
WD_CNT
CK250K Clock Timeout Unit
8 bits counter WD Reset Interrupt (SYS_WD_RST)
prescaler - mode control
- timeout generation WD Attention Interrupt (WD_ATT)
Reset - window checking
User Mode (from CPU) - protection mode Protection Error Intrrupt (SYS_PROT_ERR)
checking

WD_TG WD_ERR
WD_WND
Figure 30 – Functional diagram of the Watchdog block.

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The Watchdog mode, simple timer, window or intelligent is selected via the control bit WD_MODE. All modes
use a timeout value WD_TO, which determines the watchdog timeout WD_TO. An 8 bit free-running counter
WD_CNT is counting using the pre-scaled input clock until it reaches the value WD_TO.

The WD prescaler module supports the following ratios WD_DIV: 1/8, 1/32, 1/128, 1/512 of the 250kHz input
clock frequency. And the watchdog time-out value is defined by the following equation:

1
Equation 13 TimeOut   2 2WD _ DIV  8  WD _ TO
FCK
Where: Fck=1/Tck is the frequency of the WD input clock
WD_DIV is the WD predivider value, defined in IO port WCTRL
WD_TO is the time out value, defined in IO port WDT

For a given time, several combinations of WD_TO and WD_DIV can be found. It is recommended to use WD_TO
values as big as possible and to reduce WD_DIV.
Examples of timeout values for different Tosc values are given in Table 50.

Timeout (ms) for 250kHz input clock

1 5 10 50 100
WD_DIV WD_TO WD_DIV WD_TO WD_DIV WD_TO WD_DIV WD_TO WD_DIV WD_TO
0 31 0 156 1 78 2 98 2 195
Table 50 – Example of WD_DIV and WD_TO setting with Fck=250kHz.

The operating mode can be set only once after resetting, which usually happens in the system initialization. To
change the mode, a new system reset is needed. To acknowledge the watchdog, the IO port WDT must be
written.

The IO port associated to the Time Out value WD_TO is the port WDT.
The IO port associated to the Tag value WD_TG is the port WTG.
The IO port associated to the Control and flag bits, e.g. WD_MODE, is the port WCTRL.

17.4. Timer mode

In Timer mode the watchdog reset interrupt is generated simply when reaching the timeout value.
 The block can be acknowledged anytime by writing a dummy value into port WDT. This restarts the
free-running counter.
 The timeout value WD_TO is fixed and can be changed only before enabling the watchdog.
 An attempt to change the control bit WD_MODE or WD_DIV sets the flag bit WD_ERR to 1. An
interrupt PROT_ERR is generated.

17.5. Window mode

In Window mode the acknowledgement must happen in a “window” between the half timeout and the
timeout.
 An acknowledgement outside this window causes a CPU watchdog reset.
 The timeout value WD_TO is fixed and can be changed only before enabling the watchdog.
 The control bit WD_WND is set to 1 while the window is valid.
 An attempt to change the control bit WD_MODE or WD_DIV sets the flag bit WD_ERR to 1. An
interrupt PROT_ERR is generated.
 After the programmed timeout WD_TO an attention interrupt WD_ATT is generated,
 The watchdog reset USER_WD_RST occurs only in case WD_TO has not been updated until 1/8 of the
timeout after the first interrupt WD_ATT.

17.6. Intelligent mode

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The Intelligent mode is different from the previous ones, as it supposes the software to allocate for a given task
a given amount of time and a tag.
 After the timeout programmed, WD_TO:
o An attention interrupt WD_ATT is generated,
o the software can verify its state using the tag WD_TG,
o The software can set a new couple of timeout value and tag.
 The watchdog reset USER_WD_RST occurs only in case WD_TO and WD_TG had not been updated 1/8
of the timeout after the first interrupt WD_ATT.
 An attempt to change the control bit WD_MODE sets the flag bit WD_ERR to 1. An interrupt PROT_ERR
is generated.
 To write new values in the IO port, the MULAN3 user bit USER must be set to 0, i.e. ‘System mode’
must be selected. Or else the flag bit WD_ERR is set to 1 and an interrupt PROT_ERR is generated.

17.7. Watchdog Control and Command ports

All the IO ports involved in Watchdog programming are resumed in Table 51 to Table 53:
 The Tag port WD_TG,
 The Status and Control port WD_CTRL, and
 The TimeOut port WD_T.

IO port: WD_TG
Address: 0x2804 Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
WD_TAG[7:0]
WD_TAG[7:0]: tag value; using this port the Watchdog software can manage different owners
Table 51 – Watchdog ports – Tag value.

IO port: WD_CTRL
Address: 0x2803 Access mode: Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
WD_ERR WD_WND WD_MODE[1:0] - - WD_DIV[1:0]
Flag for access error; depends on the Watchdog mode. Read and clear bit.
WD_ERR: 1 = WD access error detected; the interrupt PROT_ERR is generated
0 = no WD access error
Flag to indicates the open windows; for windows mode only
WD_WND: 1 = window is open, Watchdog acknowledge is allowed
0 = window is closed, no acknowledge allowed
Watchdog mode.
WD_MODE[1:0]: 00 = Watchdog disabled 10 = Window Watchdog mode
01 = Timer Watchdog mode 11 = Intelligent Watchdog mode
Predivider for Watchdog counter. The Watchdog counter clock frequency is divided by:
WD_DIV[1:0]: 00 = division by 1*8 10 = division by 16*8
01 = division by 4*8 11 = division by 64*8
Table 52 – Watchdog ports – Status and Control port.

IO port: WD_T
Address: 0x2802 Access mode: Word, Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
WD_TO[7:0]
WD_TO[7:0]: Time Out value; to be compare with the internal free running counter.
Table 53 – Watchdog ports – Time Out value.

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17.8. Interrupts connections

The MULAN3 integrated watchdog is connected directly to the Watchdog attention and watchdog reset
interrupts. For further detail refer to chapter 11 Interrupts.

Analogue and digital watchdog use the same interrupts, as described in chapter
“18 Analogue Watchdog (AWD)”.

17.9. Reset state

After a Power-On-Reset or Watchdog-Reset the WD module is disabled and the IO ports are reset.

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18. Analogue Watchdog (AWD)

In the IC an Analogue Watchdog is implemented. This Watchdog has no external pin. Because of that there is no
external capacitor needed.

The watchdog uses a completely separate 10kHz oscillator. Its nominal period t AWD_PER is ~0.1ms. The watchdog
starts always with maximum timeout delay immediately after releasing the Master reset, so it has the same
behavior after POR or WAKE UP from SLEEP MODE.
The application has no possibility to stop this watchdog.

After half of the timeout (tAWD_TIMEOUT/2) the analogue watchdog generates an info signal AWD_ATT, which is
connected to watchdog attention interrupt.
When the timer reaches the AWD_TIMEOUT, a reset is issued. The reset feeds directly into the system reset
INT0.

The watchdog delay is programmable by application through the port AWD containing 8 bits for AWD_TIME and
2 bit for the clock prescaler AWD_CKDIV (division ratios are 1-4-16-64).
The delay can be updated via the AWD port at any time.
A write to the AWD port resets the watchdog counter and the AWD_WRITE_FAIL flag. The watchdog will be
acknowledged.

The watchdog timeout can be calculated by:

Equation 14 t AWD_TIMEOUT  t AWD_PER * AWD_CKDIV* AWD_TIME

The maximum programmable watchdog time is ~0.1ms * 64 * 256 = 1.6s typ.

18.1. AWD Ports

IO port: AWD_CTRL
Address: 0x281A Access mode: Word – Read
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
AWD_TIME[7:0]
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
AWD_
AWD_RST AWD_ ATT AWD_TF - - AWD_CKDIV[1:0]
WRITE_FAIL
timeout divider register
AWD_TIME
0x00 = 0xFF = max delay, reset to 0x00 by POR or WAKE UP, write to this register restarts the
[7:0]
internal AWD timer
AWD_CKDI AWD clock prescaler
V[1:0] 00=by 64 ; 01=by 16; 10=by 4; 11=by 1
This flag shows, that the data transfer to the AWD_CK clock domain is still ongoing; could be used
AWD_TF
for polling before next write; read only
this flag is set, when the data written from the CPU could not be transferred to the AWD_CK clock
AWD_WRIT
domain properly
E_FAIL
Read/Write , cleared by POR or WAKE UP or by write with 0
Watchdog info flag, memorizes a watchdog attention interrupt
AWD_ATT Read/Write , cleared by POR or WAKE UP or write with 0 twice (time between the two writes must
be at least two periods of AWD_CK or use flag AWD_TF)
Watchdog reset flag, memorizes an analogue watchdog reset.
AWD_RST
Cleared by POR or WAKE UP or write 0
Table 54 – AWD IO ports

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18.2. Interrupt connections

The analogue watchdog shares its 2 interrupt sources with the digital watchdog included in MULAN3. The
AWD_ATT and AWD_RST flags can be read to determine, that the watchdog reset was caused from analogue
watchdog.

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19. LIN Interface

19.1. Introduction
The LIN protocol is implemented on a MULAN3 core on the MLX4 part. The complete MLX16 part is free for the
application. With this dual core architecture the bus communication is decoupled from the application. The
complete LIN driver running on the MLX4 is part of the software development system and will be supported by
Melexis. The communication between both CPUs is done via an API. This API uses the common RAM area for
data exchange. The application task (running on MLX16) transmits all necessary LIN configuration data via the
API to the LIN task (running on MLX4) during the initialization process. Further information can be found in the
document [2].

MLX16 MLX4

Figure 31 – LIN OSI-Reference model

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19.2. LIN Physical Layer

The controller contains an integrated physical layer for applications of low speed vehicle serial data network
communication using the Local Interconnect Network (LIN) protocol. The device is designed in accordance to
the physical layer definition of the LIN Protocol Specification Package 2.x and the SAE J2602 standard. The
corresponding baudrate and slew rate can be set via API commands.
The sleep mode capability allows a shutdown of the whole application. The included wake-up function detects
incoming dominant bus messages and wakes up the IC.
Because of the good symmetry parameter of the transceiver the communication with RC based synchronization
accuracy is possible under all worst case conditions in Vbat - or Ground shift, even in case of recessive bus
voltages down to 5V.

RxD debounce
The RxD debouncing circuit and the integrated low pass filter in the receiver path prevent RxD spikes in case of
RF interferences and automotive pulses to guarantee a correct sampling of the master request.

TxD timeout
A special feature is the TxD timeout. In case of a faulty blocked TxD (MLX or LIN controller crash) the Bus output
is switched off automatically after the specified TxD timeout reaction time to prevent a dominant bus. The
transmission is continued by next TxD L to H transition without delay.

19.3. Application Recommendations for the pins LIN_IN and

LIN_OUT
In case the slave node position detection via the bus shunt method (BSM) is not used in the application Melexis
recommend making a direct electrical connection between the LIN_IN and LIN_OUT pin. This will improve the
EMC performance.

19.4. LIN Slave Node Position Detection (Auto-configuration)

The physical layer implemented supports LIN Slave node position detection (Auto-configuration) according to
the bus shunt method 'BSM' (refer to [9]) by providing a dedicated offset-compensated instrumentation
amplifier and special ADC channel.

Melexis provides a software library which supports the LIN-Auto Addressing via Bus Shunt Method. Further
technical information can be found in [10] Melexis Application note, LIN-AA according Bus Shunt Method (BSM)
Slave Node Position Detection (SNPD).

Figure 32 – Principle architecture of a LIN-network supporting auto-configuration measurements

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20. Multi purpose high voltage IOs (HVIOs)

Following features are supported:

 Low side driver output (open drain), controlled with PWM

 separate ADC channel per pin
 Schmitt trigger input with fixed thresholds
 Inputs can be configured as WAKE UP source
 Timer capture input
 pins can withstand external supply voltage levels (VS)
 Low side driver (Ron typ ~20 Ohms)
 48mA high accurate free configurable current source for RGB control
 HV divider for ADC measurements
 High precision adjustable active current source (low side) and differential amplifier (VS-V(HVIOx)
to support RGB LED monitoring

differential amplifier +
shift to ADC range is
HVDIFFSEL shared for all HVIOs
VS +
-

ADC Divider

HVADIV ... ADC

ADC
Mux
HVA
HVIO[x:0] HVPROT

HV_OUTOD fast digital

output from VDDA
port or other
sources
HV_IN fast digital
0 ... 30mA (3mA step size) input to port
36 … 48mA (6mA step size) HV_INEN and interrupt

HVENFCM

Adjustable current
I_fcm
0..2mA for RGB
monitor
HV_OUTOD
HVDIFFSEL

HV_ENWU
HVENFCM

HV_INEN

HV_IN

VAUX

Ports / Interrupts Debounce HVWU to wake up

(25..50)us logic
HV_ENWU
,
Figure 33 – HVIO functional diagram

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20.1. HV IOs Connection matrix

The following table summarizes the functions of the different pins:

Function HV[...]
5 4 3 2 1 0
Low side driver 48mA (open drain) ... X X X X X X
... with PWM output from block 6 5 4 3 2 1
ADC measurement via its own ADC channel X X X X X X
Digital Schmitt trigger input X X X X X X
Digital Schmitt trigger for WAKE UP X X X X X X
Programmable Debouncing for Inputs X X X X X X

Input for Timer-Capture X X X X X X

Current sense function for shunt current via
X X - - - -
differential measurement
Table 55 – HV[x:0] functions overview

20.2. RGB control

The structure of the RGB control block can be found in Figure 34.

The HV open-drain outputs are designed for LED controlling with a constant current to adapt the brightness and
color of RGB LEDs. This will be done via current modulation (see section 12). The maximum continuous current
during the on-time is defined by a high accuracy and high stability active current source.

Advantages of this approach are:

 No additional external components are needed for driving the LEDs

 Compensation of brightness and colors of RGB LEDs can be done during the EOL process
 Melexis guarantees a LED current accuracy as described in chapter 4.4.3 Electrical parameter
specification

In order to prevent undesired LED glowing at all HV-pins an internal leakage compensation can be enabled via
the bits HVPUSEL[0] and HVPUSEL[1] in the ANA_OUTG register (see Table 63).

In case higher current (>30mA) requirements, three additional current values (up to 48mA) can be configured.
The settings can be found in section 20.5 HVIO configuration ports. For this configuration the thermal condition
has to be considered (TA, Rth package, module encapsulation).

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VS

HVPUSEL[0]
HVIO[5:0] ANA_OUTG[1]

Open drain output RGB leakage

compensation
Structure and control
high accuracy & stability
HVDOUTB0 active current source
R

HV
HV0IOUTCTRL
ANA_OUTF[3:0] ESD

OPA
HVDOUTB1 G
HV1IOUTCTRL
ANA_OUTF[7:4]

Low TC current source

Calibration on
IHVOUT[0]
HVDOUTB2
HV2IOUTCTRL
B
HVIBIASSEL ANA_OUTF[11:8]
ANA_OUTG[2]

VS
HVPUSEL[1]
ANA_OUTG[10]

RGB leakage
compensation

HVDOUTB3
HV3IOUTCTRL R
ANA_OUTF[15:12]

HVDOUTB4
HV4IOUTCTRL G
ANA_OUTN[3:0]

HVDOUTB5
HV5IOUTCTRL
B
ANA_OUTN[7:4]

Figure 34 – Block diagram for RGB control at the HVs

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20.3. RGB monitoring

VS

differential
amplifier + shift to
ADC range
HVDIFFSEL VS
+
- ... ADC
ADC
Mux
HVIO[x]

HVENFCM

I_fcm

Programmable current
source 0 .. 2mA
for LED forward
voltage measurement

Figure 35 – Principle Inline current measurement

The inline current measurement is intended to detect aging and temperature effects at the diodes. It is
supported by
 Precision current source to GND (max. 2mA)
 special differential amplifier transferring the difference VS-V(HVIOx) to the ADC input < 1.25V

Principle:
 diode switched off during modulation period
 current source and differential amplifier switched on  the LED diode starts to conduct with
~1.5...3.7V voltage drop
 voltage is measured and compared with value stored at initial calibration (EOL programming at
customer)
 Diagnostic for OPEN ((VS-V(HVIOx)) > 3.7V) and SHORT ((VS-V(HVIOx)) < 1.5V) is supported

The differential amplifier can also be used in combination with the RGB current source.

Melexis provides a software library which supports the LED forward voltage measurement. The library is part of
the Melexis Software Platform.

20.4. Shunt Current Measurement

The HV-pins HV4 and HV5 offers a current sense function for shunt current via differential measurement. The
function blocks of the hardware unit can be found in Figure 36.

The two HV-pins can be used for:

 High voltage resistant inputs for read out the status of relay contacts
 Current sense function for shunt current via differential measurement

Melexis provides a software library which supports the shunt current measurement. The library is part of the
Melexis Software Platform.

The hardware unit will be controlled via the ANA_OUTO and the ADC_SIN[4:0] port. A description of
ADC_SIN[4:0] can be found in chapter 16.3 ADC Channel selection Guide. More details to ANA_OUTO can be
found in Table 56.

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IO port: ANA_OUTO
Address: 0x28E8 Access mode: Byte – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
D_8B
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
- - - - - - EN_SENSEOPAMP SBY_8BDAC
D_8B: 8 bit DAC overcurrent comparator
standby 8 bit DAC
SBY_8BDAC: 1 = DAC disabled
0 = DAC enabled
enable overcurrent opamp
EN_SENSEOPAMP: 1 = overcurrent detection enabled
0 = overcurrent detection disabled
Table 56 – Port ANA_OUTO

Vref = 2.5 V
ANA_OUTM[7] XTA1SEL[6]
Vref
Trim
ANA_OUTM[3]
TA1
ANA_OUTO[7]
XTA1SEL[7]
8 Bit
DAC

ANA_OUTO[0]

ANA_OUTO[8] SBY
VS

- OC_SENSE
EN
HV5 ANA_OUTO[9] R1 R2 +
EN

GAIN1 = -10
VSHUNT

Offset = 250mV
- ADC_MUX[9] ADCIN11_8
ADC_MUX[8]
EN
+

ANA_OUTO[9] ANA_OUTO[9]

HV4 R1 R2
V_gndshift

Figure 36 – Function Block of shunt measurement unit

The 8-bit DAC for the overcurrent threshold can be programmed via the ANA_OUTO[7:0] register (ANA_OUTO
[7:0]=0xFF => threshold=max=2.5V; Reset value for the ANA_OUTO[7:0] = 0x00 => 0V).

The amplifier offset value can be measured with ADC-converter using bit OFFSCAL and can be added to D_8B
[7:0] for compensation.

The implemented gain is 10.

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Via the signal OC_SENSE (see also portsmap) it’s possible to detect and react in case of an overcurrent event.

The portsmap bits OC_SENSE and RELCON1/2 have an interrupt capability.

20.5. HVIO configuration ports

The following tables describe the possibilities for the configuration of the HVIO pins:

IO port: HV_CFG
Address: 0x28CE Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
[1] [1]
- - HVIFRB5 HVIFRB4 HVIFRB3 HVIFRB2 HVIFRB1 HVIFRB0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
HVTMREN HVTMREN HVTMREN HVTMREN
- - [1] [1] HVTMREN1 HVTMREN0
5 4 3 2
HVIFRBx HV Interrupt on rising edge (=0) or falling edge (=1)
HVTMRENx Routing to the timer input enable
Table 57 – HV Configuration Port 1 - Interrupt config
[1] only valid for MLX81115

IO port: HV_DEB
Address: 0x28D0 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
HV3DEB1 HV3DEB0 HV2DEB1 HV2DEB0 HV1DEB1 HV1DEB0 HV0DEB1 HV0DEB0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
[1] [1] [1] [1]
- - - - HV5DEB1 HV5DEB0 HV4DEB1 HV4DEB0
HV Debouncing: for each HV[x] there are 2 bits to select the debounce time:00=off, 01=1ms,
HVxDEBy
10=4ms, 11=8ms
bits[15:12] unused
Table 58 – HV Configuration Port 2 - HV debounce
[1] only valid for MLX81115

IO port: ANA_OUTF
Address: 0x204E Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
HV1IOUTCT HV1IOUTCT HV1IOUTCT HV1IOUTCT HV0IOUTCT HV0IOUTCT HV0IOUTCT HV0IOUTCT
RL3 RL2 RL1 RL0 RL3 RL2 RL1 RL0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
HV3IOUTCT HV3IOUTCT HV3IOUTCT HV3IOUTCT HV2IOUTCT HV2IOUTCT HV2IOUTCT HV2IOUTCT
RL3 RL2 RL1 RL0 RL3 RL2 RL1 RL0
HV0IOUTCT
HV0 Current output control register
RLx
HV1IOUTCT
HV1 Current output control register
RLx
HV2IOUTCT
HV2 Current output control register
RLx
HV3IOUTCT
HV3 Current output control register
RLx
Table 59 – HV Current output control register

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[1]
IO port: ANA_OUTN
Address: 0x28E6 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
HV5IOUTCT HV5IOUTCT HV5IOUTCT HV5IOUTCT HV4IOUTCT HV4IOUTCT HV4IOUTCT HV4IOUTCT
RL3 RL2 RL1 RL0 RL3 RL2 RL1 RL0
HV4IOUTCT
HV4 Current output control register
RLx
HV5IOUTCT
HV5 Current output control register
RLx
Table 60 – HV Current output control register MLX81115
[1] only valid for MLX81115

HVIBIASSEL = 0
HVxIOUTCTRL3 HVxIOUTCTRL2 HVxIOUTCTRL1 HVxIOUTCTRL0 HV Current Output
1 0 0 0 3 mA
1 0 0 1 6 mA
1 0 1 0 9 mA
1 0 1 1 12 mA
1 1 0 0 15 mA
1 1 0 1 18 mA
1 1 1 0 21 mA
1 1 1 1 24 mA
0 1 1 0 27 mA
0 1 1 1 30 mA
Open Drain Mode
0 0 0 0 (max possible
current)
Table 61 – HV Current output with HVIBIASSEL=0

HVIBIASSEL = 1
HVxIOUTCTRL3 HVxIOUTCTRL2 HVxIOUTCTRL1 HVxIOUTCTRL0 HV Current Output
1 1 0 1 36 mA
1 1 1 0 42 mA
1 1 1 1 48 mA
Table 62 – HV Current output with HVIBIASSEL=1

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IO port: ANA_OUTG
Address: 0x28DA Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
WUI[1] WUI[0] HVIBIASSEL HVPUSEL[0]
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
HVPUSEL[1][1] PRUV[9] PRUV[8]
HVPUSEL[0] RGB leakage compensation HVIO[2:0]: 0=on, 1=off
HVPUSEL[1] RGB leakage compensation HVIO[5:3]: 0=on, 1=off
HVIBIASSEL HV Bias Current select register: 0=max 30mA current output, 1= max 48mA current output
Configure internal wake up time
00 – no Wake Up
01 – 4096 * 1/10kHz = 409.6 ms
WUI[1:0]
10 – 8192 * 1/10kHz = 819.2 ms
11 – 16384 * 1/10kHz = 1.6384 s

program under-voltage detection level

00 – 6V
01 – 7V
PRUV[9:8]
10 – 8V
11 – 9V

Table 63 – HV Bias Current select register

[1] only valid for MLX81115

IO port: HV_OUTOD
Address: 0x28D2 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
- - HVDOUTB5[1] HVDOUTB4[1] HVDOUTB3 HVDOUTB2 HVDOUTB1 HVDOUTB0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
- - HVENPWM5[1] HVENPWM4[1] HVENPWM3 HVENPWM2 HVENPWM1 HVENPWM0
HVDOUTBx HV open drain selection: 0=OD off, 1=OD on
HVENPWMx enable the routing from the PWM to the according bit
Table 64 – HV Configuration Port 3 - inverted open drain output signal
[1] only valid for MLX81115

IO port: HV_INEN
Address: 0x28D4 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
HVENFCM[5][1] HVENFCM[4][1] HVINEN5[1] HVINEN4[1] HVINEN3 HVINEN2 HVINEN1 HVINEN0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
HVDIFFSEL3 HVDIFFSEL2 HVDIFFSEL1 HVDIFFSEL0 HVENFCM3 HVENFCM2 HVENFCM1 HVENFCM0
Select HV input for the differential amplifier: 0000b== no HV selected, 0001b==HV0, 0010b==HV1, 0100b==HV2,
HVDIFFSELx
1000b==HV3.
Enable precision current source for corresponding HV pin: 0000b== no HV selected, 0001b==HV0, 0010b==HV1, 0100b==HV2,
HVENFCMx
1000b==HV3.
HVINENx Enable digital Schmitt-trigger input (=1), analog mode (=0) (e.g. for ADC measurement), reset value is 0
Table 65 – HV Configuration Port 4 - digital or analog mode, RGB monitor measurement
[1] only valid for MLX81115

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IO port: HV_ENWU
Address: 0x28D6 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
- - HVENWU5[1] HVENWU4[1] HVENWU3 HVENWU2 HVENWU1 HVENWU0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
- - - - - - HVDIFFSEL5[1] HVDIFFSEL4[1]
HVENWUx Enables the HV[x] as Wake Up Source
HVDIFFSEL
Select HV input for the differential amplifier: 00b== no HV selected, 01b==HV4, 10b==HV5
[5:4]
Table 66 – HV Configuration Port 5 - wake up
[1] only valid for MLX81115

IO port: HV_TMR
Address: 0x28D8 Access mode: Word – Read and Write
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
[1] [1]
- - HVTMR4 HVTMR5 HVTMR3 HVTMR2 HVTMR1 HVTMR0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
- - - -
HVTMRx =0 : route digital input to TMR0_A, =1 : route to TMR0_B input

Table 67 – HV Configuration Port 6 - HV IO routing to other blocks

[1] only valid for MLX81115

IO port: HV_IN
Address: 0x28CC Access mode: Word – Read
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
[1] [1]
- - HVDIN5 HVDIN4 HVDIN3 HVDIN2 HVDIN1 HVDIN0
Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8]
- - - - - - - -
HVDINx Inputs from HV pins – debounced or undebounced – dependent on port HV_DEB
Table 68 – HV Status Port
[1] only valid for MLX81115

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21. The safety concept

Especially in the field of automotive - more than in other applications - safety is a key property of a given
customer application. In minimum a clean restart after system break down must return an application to
normal operation. The controller supports different and independent ways to find such malfunction.

By detecting that the system operation is wrong, it is possible to save dump the current state like switch
positions and important system information from the application and force the system by hardware control to
restart with refreshed and valid data, breaking endless loops in API caused by unexpected conditions.

The following description goes into detail, how the controller hardware can be used to reach such a high quality
API behavior. Additional information can be taken from block descriptions.

A) A System hang-up
Sometimes it might happen that API runs into infinite loop, waiting for event which cannot arrive. Customer can
use a set of different watchdogs to cancel these endless loops by falling into reset state.
The MULAN3 processor offers a digital watchdog, which can be used to set different time frames for a known
subroutine to be finished, otherwise assuming that something goes wrong and such a routine should be
stopped because an expected event has not occurred.
If the controller does not receive a valid acknowledge signal of the independent analogue Watchdog – the
complete system will be reset, powered down – after then a system restart will be done with default inactive
loads.
The best way to come out of any self-locked states is to accept a complete and refreshed restart, discarding any
data and start from a well-known state again.

B) Checking system’s integrity

The multi-channel ADC system allows customer a periodical check of analogue voltages inside the chip. By
detecting results outside bounds, which are known by software – a system drift to dangerous operation
conditions can be early detected. Overheating by power consumption above an expected limit can be measured
with an integrated temperature sensor via one of the ADC’s channel or with external thermal resistors as well.

By taking the above features into the application software, it is possible to make the system safe against
malfunction caused by system disturbances. In such cases the silicon is able to return to normal operation after
problem has been removed.
If this is impossible – the system can protect itself by switching off disturbed functions and keeping non-
disturbed functions still alive if possible.
The protection of the application is the key feature of the controller.

C) Other security mechanism

 On chip temperature sensing
 On chip over temperature shutdown
 ECC on all NV memories

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21.1. IC Behavior in the fault case

21.1.1. Loss of battery

If the ECU is disconnected from the battery, the LIN_IN pin is in high Impedance State. There is no impact to the
LIN-bus traffic and to the ECU itself.
Supply voltage can be limited below under-voltage threshold. The controller will behave passive as described
for the fault condition “Under-voltage VS”.

21.1.2. Loss of Ground

In case of an interrupted ECU ground connection there is no influence to the LIN bus line.

21.1.3. Short circuit to battery

The LIN transmitter output current is limited to the specified value in case of short circuit to battery in order to
protect the controller itself against high current densities.

21.1.4. Short circuit to ground

If the bus line is shorted to negative shifted ground levels, there is no current flow from the ECU ground to the
LIN-bus and no distortion of the bus traffic.
If the controller detects a short circuit of the bus to ground (RxD timeout) the transceiver can be sent into sleep
mode. The internal slave termination resistor is switched off and only a high impedance termination is applied
to the bus. The failure current of the whole system can be reduced by at a factor of 10 to prevent a fast
discharge of the car battery. If the failure disappears, the bus level will become recessive again and will wake up
the system even if no local wake up is present or possible.

21.1.5. Thermal overload

Via the internal temperature diode, descripted in chapter 16.11 Measuring the chip temperature, it is possible
to protect the controller against thermal overload.

21.1.6. Under-voltage VS
If the ECU battery supply voltage is missing or decreases under the specified value, the LIN pin behaves passive.

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22. ESD and EMC

In order to minimize EMC influences, the PCB has to be designed according to EMC guidelines. The IC is an ESD
sensitive device and has to be handled according to the rules in IEC61340-5-2. The IC will apply the
requirements in the application according to the specification and to ISO7637-2, -3.
Prototype samples of the IC will be evaluated according AEC-Q100-002. The result will be published after
qualification. After ESD stress single parameters may be shifted out of their limit, but IC function will still be
correctly.

22.1. Automotive Qualification Test Pulses according to

ISO7637-2/3 and ISO16750-2
That means that automotive test pulses are applied to the module in the application environment and not to
the single IC. Therefore attention must be taken, that only protected pins (protection by means of the IC itself
or by means of external components) are wired to a module connector. In the recommended application
diagrams, the reverse polarity diode together with the capacitors on supply pins, the protection resistors in
several lines and the load dump protected IC itself will protect the module against the below listed automotive
test pulses. The exact value of the capacitors for the application has to be figured out during design-in of the
product according to the automotive requirements.

For the LIN pin the specification “LIN Physical Layer Spec 2.1 (Nov. 24, 2006)” is valid.
Supply Pin VS is protected via the reverse polarity diode and the supply capacitors. No damage will occur for
defined test pulses. A deviation of characteristics is allowed during pulse 1 and 2; but the module will recover to
the normal function after the pulse without any additional action. During test pulse 3a, 3b, 5 the module will
work within characteristic limits.

22.1.1. Test Pulses on supply Lines (directly connected to Car Battery)

test condition,
Parameter Symbol Min Max Dim Coupling
functional status
Transient test pulses in accordance to ISO7637-2 (supply lines) & VS=13.5V, TA=(23 5)°C
& (Document: “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”; Audi,
BMW, Daimler, Porsche, VW; 2009-12-02)
5000 pulses,
Test pulse #1 vpulse1 -100 V Direct
functional state C
5000 pulses,
Test pulse #2 vpulse2 75 V Direct
functional state A
1h,functional state
Test pulse #3a vpulse3a -150 V Direct
A
1h,functional state
Test pulse #3b vpulse3b 100 V Direct
A
1 pulse clamped to
27V (+13V (VS)),
(32V (+13V
65 87
Test pulse #5b vpulse5b (+13V (+13V V Direct (VS))for
(VS)) (VS))
applications for
north America),
functional state C
Table 69 – Test pulses Supply Line

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22.1.2. Test pulses on LIN_IN and LIN_OUT Lines

test condition,
Parameter Symbol Min Max Dim Coupling
functional status
Transient test pulses in accordance to ISO7637-3, VS=13.5V, TA=(23 5)°C
& (Document: “Hardware Requirements for LIN, CAN and FlexRay Interfaces in Automotive Applications”; Audi,
BMW, Daimler, Porsche, VW; 2009-12-02)
Direct
Vpulse
capacitive 1000 pulses,
Test pulse ‘DCC slow –‘ _ -100 V
coupled: functional state D
slow+
1nF
Direct
Vpulse
capacitive 1000 pulses,
Test pulse ‘DCC slow +‘ _ 75 V
coupled: functional state D
slow-
1nF
Direct
Vpulse
capacitive 10 min,
Test pulse ‘DCC fast a’ _ -150 V
coupled: functional state D
fast_a
100pF
Direct
Vpulse
capacitive 10 min,
Test pulse ‘DCC fast b’ _ 100 V
coupled: functional state D
fast_b
100pF
Table 70 – Test pulses LIN

22.1.3. Test pulses on signal lines, incl. LIN_IN, LIN_OUT

test condition,
Parameter Symbol Min Max Dim Coupling
functional status
Transient test pulses in accordance to ISO7637-3 (signal lines). VS=13.5V, TA=(23 5)°C
Direct
Vpulse
capacitive 1000 pulses,
Test pulse ‘DCC slow –‘ _ -30 -8 V
coupled: functional state C
slow+
100nF
Direct
Vpulse
capacitive 1000 pulses,
Test pulse ‘DCC slow +‘ _ +8 +30 V
coupled: functional state A
slow-
100nF
Direct
Vpulse
capacitive 10 min,
Test pulse ‘DCC fast a’ _ -60 -10 V
coupled: functional state A
fast_a
100pF
Direct
Vpulse
capacitive 10 min,
Test pulse ‘DCC fast b’ _ 10 40 V
coupled: functional state A
fast_b
100pF
Table 71 – Test pulses signal lines
Description of functional status

A: All functions of the device are performed as designed during and after the disturbance occurs.
B: All functions of the device are performed as designed during the disturbance occurs. One or more
functions can violate the specified tolerances. All functions return automatically within their normal
limits after the disturbance is removed.
C: A function of a device does not perform as designed during the disturbance occurs but returns
automatically to the normal operation after the disturbances is removed

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D: A function of a device does not perform as designed during the disturbance occurs and does not return
automatically to the normal operation after the disturbances is removed. The device needs to be reset
by a simple operation/action to return to the specified limits/function.

22.1.4. EMV Test pulse definition

EMV Test Pulse shapes (ISO7637-2 (supply lines))
Test Pulse 1 Test pulse 2
Ri = 10 Ohm Ri = 2 Ohm
200 ms 0.5...5s
V < 100 µs 50 µs
V 1 µs
12 V
0V
10% t
90%

vpulse1
vpulse2

90%
10%
1 µs 12V
2 ms 0V
0.5...5s 200 ms t

Test Pulse 3a Test Pulse 3b

Ri = 50 Ohm Ri = 50 Ohm
100 ns

V 5 ns
V 90%

12V 10%
vpulse3b
0V
t

vpulse3a vpulse3b
vpulse3a

12V 10%

100 µs 0V
10 ms 90 ms 90%
100 µs t 5 ns
10 ms 90 ms 100 ns

Test Pulse 5 (Load Dump)

Ri = 0.5…4 Ohm (clamped to 45V during test)

90% Pulse 5

Pulse 5 at
vpulse5 device
40V

10%
12V

t
tr = 0.1...10ms

td = 40...400ms

Table 72 – Test pulses shapes ISO7637-2

EMV Test Pulse shapes (ISO7637-3 (non-supply lines))

Test Pulse ‘DCC slow -’ Test pulse ‘DCC slow +’
Ri = 2 Ohm Ri = 2 Ohm

Test Pulse ‘Fast a, DCC’ Test Pulse ‘Fast b, DCC’

Ri = 50 Ohm Ri = 50 Ohm

Table 73 – Test pulses shapes ISO7637-3

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22.1.5. Circuitry recommendations for improved ESD and EMC behavior

In order to minimize EMC influences, the external application circuitry shall be designed as followed:

D12)
VS

C11) C22) + C32)

VS
Connector

R12) R22)
Signal-
LIN LIN Actuators line
Signal
-line

C41) C52) C61) Product C71)

D21) D31)
GND

GND

1) optional implemented
2) mandatory implemented

22.1.5.1. External Circuitry on Supply Lines

In order to minimize EMC influences, the external application circuitry shall be designed as followed:

Name Mounting Min Recommended Max Dim Comment

Ceramic SMD: 10%, 0805,
C1 recommended - 100 - nF ≥50V;
close to the connector
Inverse-polarity protection
D1 mandatory
diode
Ceramic SMD Murata X7R
4.7uF +-10% 50V
GCM31CC71H475KA03
In case function state A is
[1]
C2 mandatory 4.7 22 100 μF needed during pulse 2A
minimum 10µF (Ceramic SMD
Murata X7R 10uF +-10% 50V
GCM32EC71H106KA03) are
2
required.
Ceramic SMD: 10%, 0805,
C3 mandatory - 100 - nF ≥50V;
close to the pin

[1]
Tests were performed with Tantalum SMD: 10%, 7343, 35V
[2]
During the test higher voltage than 50V can occur. It would be verified that neither the DUT nor the capacitor
will be damaged.

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22.1.5.2. External Circuitry on LIN Lines

In order to minimize EMC influences, the external application circuitry shall be designed as followed:

Name Mounting Min Recommended Max Dim Comment

ESD protection Diode: SOD323
D2 no - PESD1LIN - close to the connector;
optional part
Ceramic SMD: 10%, 0805, ≥50V;
CSlave≤ CD2+C4+C5+C6+CIC
C4 no - - - pF
CSlave≤250pF;
optional part
Serial resistor: 0805;
R1 mandatory - 0 - Ω
or optional Ferrite
Ceramic SMD: 10%, 0805, ≥50V;
C5 mandatory - 220 - pF CSlave≤ CD2+C4+C5+C6+CIC
CSlave≤250pF
Ceramic SMD: 10%, 0805, ≥50V;
CSlave≤ CD2+C4+C5+C6+CIC
C6 no - - - pF
CSlave≤250pF;
optional part

22.1.5.3. External Circuitry on Signal Lines

In order to minimize EMC influences, the external application circuitry shall be designed as followed:

Name Mounting Min Recommended Max Dim Comment

Ceramic SMD: 10%, 0805, ≥50V;
C7 no - 10 - nF
optional part
Serial resistor: 0805;
R2 mandatory - 390 - Ω
or optional Ferrite
ESD protection Diode: SOD323
D3 no - PESD1LIN - close to the connector;
optional part

22.2. ESD Robustness according to IEC61000-4-2

Test for ESD robustness according to IEC61000-4-2 “Gun test” (150 pF, 330 Ω) have been performed. The results
and test conditions are available in a separate test report.

Parameter Discharge Point Condition Min. Max. Unit

VBAT -15 +15
ESD capability of pin
LIN_IN Acc. To IEC 61000-4-2 [1][2] -14 +14 kV
VS, LIN versus GND

ESD capability of
HV5 Acc. To IEC 61000-4-2 [1][2] -10 +10 kV
HVx-pin versus GND

[1] Equivalent to discharging a 100pF capacitor through a 1.5kΩ resistor conform AEC-Q100-002.
[2] Tested by external test house (IBEE Zwickau, EMC test report no. 04-10-17).

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Figure 37 – Used application circuitry for the IEC 61000-4-2 test

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23. Debugging Facilities

Hardware and software debugging tools are available for the MULAN3 based products.

23.1. Debug Interface

For programming purpose the pins

 HV0, HV1, HV2, HV3

must be accessible on the application PCB. A schematic with further information can be found in Figure 38.

It is not possible to use the debugging pins simultaneously in the application and for debugging. There must be
an option (e.g. jumper) to separate the debugging pins from the application circuitry

It is important to mention that for debugging/programming the controller must be supplied from the Mini E-
Mlx. The Mini E-Mlx itself has to be connected to a 12V power supply (Figure 38).

For debugging purpose there is a device version with higher pincount available. It gives access to the debug
interface and the HVx application pins at the same time.

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Figure 38 – RGB-controller debug interface with the Melexis Mini E-Mlx emulator

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23.2. Melexis Mini E-Mlx emulator

To use the controller debugging interface directly with the Melexis Mini E-Mlx connector it is necessary to put
external components (see Figure 38) and a 9 pin mini circular connector with shield on the PCB. The connector
could be a MD-90SM from CUI INC. This part can be ordered for instance from Digi-Key (CP-2290-ND).

It is important to mention that for debugging/programming the controller must be supplied from the Mini E-
Mlx. The Mini E-Mlx themselves has to be connected to a 12V power supply (Figure 38).

Pin No Name Function

1 TI0 Test input 0 (Controller)
2 GND Ground
3 VBAT VBAT input
4 TI1 Test input 1 (Controller)
5 LIN/MUST Open (not used)
6 V0 Test Mode enable
7 V2 3.3V output
8 TO Test output (Controller)
9 V1 VS output (supply for the controller)
Shield GND Ground
Table 74 – Pin description 9 pin mini circular connector of the Mini E-Mlx

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24. End of Line Programming

There are two possible ways for end of line programming of the FLASH- and NVRAM-memory:

 Via Melexis Debug Interface

 Via LIN pin

Melexis provides for both options a production tool called PTC-04. For further information please contact your
distributor or the Melexis sales team.

25. Standard information regarding

manufacturability of Melexis products with
different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture sensitivity
level according to following test methods:

Reflow Soldering SMD’s (Surface Mount Devices)

 IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
 EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)

Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)

 EN60749-20
Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat
 EIA/JEDEC JESD22-B106 and EN60749-15
Resistance to soldering temperature for through-hole mounted devices

Iron Soldering THD’s (Through Hole Devices)

 EN60749-15
Resistance to soldering temperature for through-hole mounted devices

Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)

 EIA/JEDEC JESD22-B102 and EN60749-21

Solderability

For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.

The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.

Melexis recommends reviewing on our web site the General Guidelines soldering recommendation
(http://www.melexis.com/Quality_soldering.aspx).

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Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of the
use of certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality.aspx

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26. Disclaimer
The information furnished by Melexis herein (“Information”) is believed to be correct and accurate. Melexis disclaims (i) any and all liability in connection with or
arising out of the furnishing, performance or use of the technical data or use of the product(s) as described herein (“Product”) (ii) any and all liability, including
without limitation, special, consequential or incidental damages, and (iii) any and all warranties, express, statutory, implied, or by description, inc luding
warranties of fitness for particular purpose, non-infringement and merchantability. No obligation or liability shall arise or flow out of Melexis’ rendering of
technical or other services.
The Information is provided "as is” and Melexis reserves the right to change the Information at any time and without notice. Therefore, before placing orders
and/or prior to designing the Product into a system, users or any third party should obtain the latest version of the relevant information to verify that the
information being relied upon is current.
Users or any third party must further determine the suitability of the Product for its application, including the level of reliability required and determine whether
it is fit for a particular purpose.
The Information is proprietary and/or confidential information of Melexis and the use thereof or anything described by the In formation does not grant, explicitly
or implicitly, to any party any patent rights, licenses, or any other intellectual property rights.
This document as well as the Product(s) may be subject to export control regulations. Please be aware that export might require a prior authorization from
competent authorities.
The Product(s) are intended for use in normal commercial applications. Unless otherwise agreed upon in writing, the Product(s) are not designed, authorized or
warranted to be suitable in applications requiring extended temperature range and/or unusual environmental requirements. High reliability applications, such
as medical life-support or life-sustaining equipment are specifically not recommended by Melexis.
The Product(s) may not be used for the following applications subject to export control regulations: the development, production, processing, operation,
maintenance, storage, recognition or proliferation of 1) chemical, biological or nuclear weapons, or for the development, production, maintenance or storage of
missiles for such weapons: 2) civil firearms, including spare parts or ammunition for such arms; 3) defense related products, or other material for military use or
for law enforcement; 4) any applications that, alone or in combination with other goods, substances or organisms could cause serious harm to persons or goods
and that can be used as a means of violence in an armed conflict or any similar violent situation.
The Products sold by Melexis are subject to the terms and conditions as specified in the Terms of Sale, which can be found
at https://www.melexis.com/en/legal/terms-and-conditions.

This document supersedes and replaces all prior information regarding the Product(s) and/or previous versions of this document.

Melexis NV © - No part of this document may be reproduced without the prior written consent of Melexis. (2016)

ISO/TS 16949 and ISO14001 Certified

27. Contact Information

For the latest version of this document, go to our website at www.melexis.com.

For additional information, please contact our Direct Sales team and get help for your specific needs:

Europe, Africa Email : sales_europe@melexis.com

Americas Email : sales_usa@melexis.com

Asia Email : sales_asia@melexis.com

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28. History record

The following listed versions of specification were published to be valid. Always the highest version is valid for
the actual produced version of the IC, any older version may be used in reference to the state of development
of the IC in past. Please refer to column IC revision letter to select the matching spec version.
For deviations of the recent design version regarding this specification please see also the
Errata Sheet of the RGB controller family.

Spec
IC Revision Changes in Specification Date Stamp
Version
MLX81115A Initial revision August 2015 001
Chapter IO Register updated
Chapter IC Marking updated
May 2016 002
Ordering Code updated
Chapter CPU core MULAN3 updated
Order Information updated
Chapter Standard ports updated
Chapter Digital Watchdog – Window mode updated
Chapter Analog Watchdog updated
Chapter NVRAM organization updated
Chapter Absolute maximum rating
Chapter ESD and EMC updated
Chapter Pin out description
Chapter RGB control updated
Chapter Electrical parameter specification May 2017 003
Sleep Current updated
Parameter for RGB leakage compensation resistor
added,
Section LIN AA updated,
Parameter for Shunt differential amplifier updated
Chapter LIN Slave Node Position Detection updated
Chapter External Interrupts
Chapter End of Line Programming added
Chapter Shunt Current Measurement added
Typos corrected
Chapter External Circuitry on Signal Lines; recommended
January 2018 004
values updated
Order Information updated
Chapter Electrical parameter specification
Parameter for Shunt differential amplifier updated April 2018 005
Order Information updated
September
Chapter ESD and EMC updated 006
2018
Chapter External Circuitry on Supply Lines updated
Footnote “50V remark” added
Order Code information updated March 2020 007
Package drawing for DFN12 updated

Table 75 – History record

28.1. Change list for ROM code

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The ROM code Revision is coded in the last 2 characters of the Order Code. Further information can be found in
chapter 1 Features, Ordering Information.

ROM Revision Code Changes

AB First ROM code release
AC Update Mulan3 Software Platform from 1.0 to 1.4
AD Update Mulan3 Software Platform from 1.4 to 1.6

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