Course Prerequisites

EE290C – Spring 2011 • Minimum: EE141, EE240

• EE241 helps too, but not necessarily required

High-Speed Electrical Interface Circuit Design • Assume you are familiar with:
Lecture 1: Introduction • Basic data converters (at level of EE240 project -
EE247 not required)
• Verilog/VHDL
• Basic transmission lines (EE117)

• Exposure to communications & signal

Elad Alon processing helpful
Dept. of EECS • But deep expertise not required – will cover
important points of what we need
EE290C Lecture 1 4

Course Focus Lecture Notes

• Focus: • Based on slide from Prof. Borivoje Nikolic,
• Circuit design for modern electrical interfaces Prof. Vladimir Stojanovic (MIT), Jared Zerbe
(Rambus), and myself
• Interfaces (links) are now complex, mixed-
signal communication systems • Primary source of material for the class
• Will do a lot of transistor-level design • No required text
• But will be tightly coupled to system-level design

• Notes posted on the web at least 1 hour

• Goal: before lecture
• Learn how to design an optimized link given a • Will hand out limited # of hard copies in class
target application
EE290C Lecture 1 2 EE290C Lecture 1 5

Administrative Some References

• Digital Systems Engineering
• Course web page: W.J. Dally, J.W. Poulton, Cambridge University Press, 1998.
http://bwrc.eecs.berkeley.edu/classes/icdesign/ee290c_s11
• Design of High-Performance Microprocessor Circuits
• Webcast link: Edited by A. Chandrakasan, W. J. Bowhill, F. Fox, IEEE Press,
2001
http://webcast.berkeley.edu • Chapter on high-speed signaling and I/O design

• Office hours • Design of Integrated Circuits for Optical Communications

B. Razavi, McGraw-Hill, 2002
• 519 Cory Hall
• Tues. 9-10am, Thurs. 11am-12pm • Papers from:
• IEEE Journal of Solid-State Circuits
• IEEE International Solid-State Circuits Conference
• All announcements made through web page • IEEE Symposium on VLSI Circuits
• Check back often • IEEE Custom Integrated Circuits Conference
• …

EE290C Lecture 1 3 EE290C Lecture 1 6

 Grading Shouldn’t This Be Really Easy?
• Grading:
• HW: 30%
• Will have 3-4 assignments
• Essential for learning the class material
• Project: 60%
• Will design a complete high-speed (>10Gb/s) interface
• Groups of 3-4
• Will want wide range of skills - form your groups now
• Presentations: 10% • This really is a “link“
• Will give two project-related presentations • (Although maybe not the best one)
• First at project “half-way” point
• Seems like it should be really easy to build
• Second at project end
• So why have this class at all?
• No exams
• But don’t take course lightly – will be a lot of work • Look at where/how links are really used
EE290C Lecture 1 7 EE290C Lecture 1 10

Homework Lots of Data on the Move

NSFnet 1992, D. Cox, R. Patterson, NCSA
• Homework:
• Can discuss/work together
Backbone
• But write-up must be individual
Router
• Drop in box outside Elad’s office (519 Cory) Rack
• Generally due 5pm on Thursdays

• No late submissions
• Start early!

PC or
Console
EE290C Lecture 1 8 EE290C Lecture 1 11

Schedule Notes Links Are Everywhere

NSFnet 1992, D. Cox, R. Patterson, NCSA
• ISSCC Week: 2/21 - 2/25 (no lectures)
• Spring break: 3/21 – 3/25
Backbone
• Project: Router
• Will be broken into 3-4 parts Rack

• Check on the website for updates

• First presentations: ~1st week of April
• Final presentations: RRR week

PC or
Console
EE290C Lecture 1 9 EE290C Lecture 1 12
 Inside of a Router (ca. 2006) So What Was Wrong With This?
Line Cards: Passive Switch Cards:
8 to 16 per System Backplane 2 to 4 per System
MEM

MEM
MEM

MEM
MEM

MEM
MEM

MEM
SerDes
SerDes Crossbar
Crossbar

TM/
TM/
Optics
Optics SerDes MAC
MAC NPU
NPU Fabric
Fabric
IF
IF SerDes
SerDes

• In principle, nothing ☺
• As long as the wire is “short enough”
OC-192 4x3.125 Gb/s 3.125-12.5Gb/s • And get the “right” clock at both TX and RX
10Gb/s XAUI Serial Links Backplane Serial Links
Laser driver link (chip-to-chip) • When is a wire “short enough”?
• How to get the “right” clocks?

EE290C Lecture 1 13 EE290C Lecture 1 16

Inside of a Router (ca. 2011) What a Link Needs to Do

Line Cards: Passive Switch Cards:
8 to 16 per System Backplane 2 to 4 per System • Get bits from the TX to the RX (Signaling)
MEM

MEM
MEM

MEM
MEM

MEM
MEM

MEM

SerDes
SerDes Crossbar
Crossbar

TM/
TM/
Optics
Optics SerDes MAC
MAC NPU
NPU Fabric
Fabric
IF
IF SerDes
SerDes

• Determining which bit is which (Timing)

OC-768 4x10 Gb/s 6.25-25Gb/s

40Gb/s Serial Links Backplane Serial Links
Laser driver link (chip-to-chip)

• No extra wires/cables, minimal changes to PCB

• But everything needs to run faster…
EE290C Lecture 1 14 EE290C Lecture 1 17

Not Just Routers… Backplane Signaling At 2-3Gb/s (Past)

• Chip-to-chip signaling Linecard Backplane Linecard
• Computers, games: Serdes Serdes
DDR, DDR2: 100-400Mb/s
RDRAM 800-1600Mb/s 0.0 0.2 0.4 0.6 0.8 1.0
[GHz]
XDR DRAM 3.2-6.4Gb/s 1.0

• Board-to-board signaling:
• Computers, peripherals: 2Gb/s view of the channel Signal at Rx
Signal at Tx
0.1

PCI (66-133-400MHz), PCI Express (2.5Gb/s – 10Gb/s)

USB (10Mb/s – 10Gb/s) • Other than knowing about transmission lines
• “Wire” (channel) wasn’t an issue up to 2-3Gb/s
• Constant desire to signal faster at same or lower power • “Good old days” –on-chip circuits set speed limits
• No matter where the links are
• Lots of publications on how to make them faster
EE290C Lecture 1 15 EE290C Lecture 1 18
 Backplane Signaling At 10+Gb/s (Today) Syllabus
Linecard Backplane Linecard • Link Environment
• Channels: physical components, models
Serdes Serdes
• Link performance evaluation
• Signaling
1.00
0.0 1.0 2.0 3.0 4.0 5.0
[GHz] • Transmitters, receivers
• Equalizer types, circuits
0.10

• Adaptation algorithms and implementations

Signal at Tx
0.01
Signal at Rx • Timing
• Clocking and link types
0.00

• Clock and data recovery (CDR)

10Gb/s view of the channel
• PLLs, DLLs, and phase interpolators
• Channel now degrades the signal significantly • Support functions
• Improvements in channel tend to be costly • Supply regulation
• Short-distance optics vs. electrical debate ~15 years old • Mixed-signal design verification
• Electronics usually bear the burden • Advanced topics (if time permits)
EE290C Lecture 1 19 EE290C Lecture 1 22

To Make Life Even More Fun…

• Need to achieve all of this within tightly limited

power, area budgets
• With lots of noisy digital blocks nearby
• And with transistor scaling running out of steam

EE290C Lecture 1 20

Good News
• Many opportunities for multi-disciplinary
innovation
• Circuits, communications, optimization, E&M, …

• Will learn how to build (one of) most efficient

comm. systems in existence
• Best designs use only ~0.5-2mW per Gb/s of
throughput

• Techniques broadly applicable

• Even if you end up working on RF, biosensors, data-
converters, etc.

EE290C Lecture 1 21