Clocking Types

EE290C – Spring 2011

Lecture 4: Timing Basics

Elad Alon
Dept. of EECS
*Poulton’99
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Why We Need to Talk About Timing “Simple” Synchronous System

• Under what conditions will this work?

• “EE141” answer:

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Clocking Types What You Really Do

• Many different options…

• All boil down to relationship between (or even

existence of) clk1 and clk2

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An Example Source Synchronous Clocking

• tp,data = 2ns, Tbit = ?

• What else do you need to know? • Key idea: match clock and data paths
• Link ideally works from DC up to timing uncertainty-
limited frequency

• What is the “right” tdel?

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An Example Source Synchronous Clocking

• tp,data = 2ns, Tbit = ?

• Want one clock “link” for multiple data links

• Reduce overhead

• What if data lines don’t match each other?

• Or don’t match clock line
• Or tdel isn’t quite right (depends on Tbit, PVT, etc.)

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An Example Realistic Source Synchronous System

tp,data,1
D1 D Q TX RX D Q DRX1

• tp,data = 2ns, tsk+jitt = +/-50ps tdel1

tp,data,0
• Get “bands” of 15 D0 D Q TX RX D Q DRX0
functionality:
# of bits on the line

14
13 tp,data,c
12 TX RX tdel0
11
10 clk
9
8
7
6
100 150 200 250 300 350
T (ps)
bit
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In General: CDR Bang-Bang (Alexander) Phase Detector
• CDR = Clock and Data Recovery
Vin dn
• Recover clock phase and/or frequency based on data
itself
• If phase only, need a frequency reference data Clk

en
• Several advantages vs. fixed timing
edge Clk
• Don’t have to match delays/paths (mesochronous)
• Allows separate crystals (plesiochronous) • Edge clock Tsym/2 away
from data
• But, CDR isn’t free • Derive early/late from data
• And places some requirements on data and edge samples:
• Dn: (dn != en) & (dn-1 != dn)
• Up: (dn == en) & (dn-1 != dn)
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Conceptual CDR Phase Adjustment

• Many possibilities…
• DLL vs. PLL
• VCO vs. VCDL
• Digital vs. analog
• Etc.

• All boil down to adjusting delay, frequency,

or both
• More in a few weeks

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Linear (Hogge) Phase Detector CDR in Plesiochronous System

CHIP 1 CHIP 2
Logic Serializer Tx Rx Deserializer FIFO Logic

Elastic
Buffer

f1 PLL CDR f2 from

other
10 bits 10 bits 10 bits links
@ f1 @ f1 @ f2

• Transmit data @ f1
• Recover clock and data @ f1 on RX
• Elastic buffer (FIFO) transfers data from f1 to f2

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 Implications
CHIP 1 CHIP 2
Logic Serializer Tx Rx Deserializer FIFO Logic

Elastic
Buffer

f1 PLL CDR f2 from

other
10 bits 10 bits 10 bits links
@ f1 @ f1 @ f2

• FIFO must be deep enough

• Set by max. freq. offset, data length

• CDR must be able to track max. freq. offset

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Final Notes: Parallel vs. Serial Links

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Final Notes: Clock Distribution

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