Verilog

Yogesh Tiwari
Assistant Professor
CSPIT , CHARUSAT
Presentation Outline
• Verilog Basics
• Case Sensitive
• Component of Code
• Modelling Styles (Dataflow, Behavioral, Structural) [ Named Association , Positional Association]
• Datatypes
• Operators
• Parameters
• Procedural Constructs
• Control statements
• Loops statements
• Process and sensitivity list
• Initial & Always difference
• Blocking and Non Blocking statements
• Synthesizable Verilog
• Reg & Wire difference
• Latch Generation
• Testbench
• Structure
• Components
• Simulator directives
• Examples – (Combinational , Sequential)
Presentation Outline
• Examples
• Combinational
• Gate level Expression
• Decoder , MUX ( using Dataflow, Behavioral, Structural Modelling Styles) - Active Low
and Active Decoder
• Magnitude Comparator
• Half Adder , Full Adder , Ripple Adder (using Dataflow, Behavioral, Structural Modelling
Styles)
• Sequential
• Latch & Flip Flop
• Counter (Asynchronous & Synchronous Reset).
• Frequency Divide Verilog Code
• Moore – Mealy FSM (Sequence Detector)
1) Write a verilog code to swap contents of two
registers with and without a temporary register?
•
With temp reg ;
always @ (posedge clock)
begin
temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin
a <= b;
b <= a;
end

•
 2) Difference between blocking and non-
blocking?(Verilog interview questions that is most
commonly asked)
The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <=
assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is
done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and
assigns the left-hand sides at the end of the time unit. For example, the following Verilog program
// testing blocking and non-blocking assignment
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Blocking: A= %b B= %b", A, B ); A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule
produces the following output:
Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100
The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the
registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems.
blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential
Clock Generation
• self triggering blocks -
module osc2 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk <= ~clk;
endmodule
After the first @(clk) trigger, the RHS expression of the nonblocking assignment is
evaluated and the LHS value scheduled into the nonblocking assign updates event queue.
Before the nonblocking assign updates event queue is "activated," the @(clk) trigger
statement is encountered and the always block again becomes sensitive to changes on
the clk signal. When the nonblocking LHS value is updated later in the same time step,
the @(clk) is again triggered.
Clock Generation
• module osc1 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk = ~clk;
endmodule
Blocking assignments evaluate their RHS expression and update their LHS
value without interruption. The blocking assignment must complete before
the @(clk) edge-trigger event can be scheduled. By the time the trigger
event has been scheduled, the blocking clk assignment has completed;
therefore, there is no trigger event from within the always block to trigger
the @(clk) trigger.
UP-Down Counter
Up Down Counter
N Bit Counter
Ring Coounter
Ring Counter
Ring Counter (Correct)
Ring Counter (Blocking Assignment)
Reverse order of statements
Shift Register ?
Answer : A & B
Frequency Divide by 2
module clk_div (clk_in, enable,reset, clk_out); //
--------------Port Declaration-----------------------
input clk_in ; input reset ;
input enable ; output clk_out ;
//--------------Port data type declaration-------------
wire clk_in ; wire enable ;
//--------------Internal Registers----------------------
reg clk_out ;
//--------------Code Starts Here-----------------------
always @ (posedge clk_in)
if (reset)
begin
clk_out <= 1'b0;
end
else if (enable)
begin
clk_out <= !clk_out ;
end
endmodule
Frequency Divide by 3
• Assignment
• module divide_by_3 (

• clk_in , //Input Clock

• reset , // Reset Input

• clk_out // Output Clock

• );

• //-----------Input Ports---------------

• input clk_in;

• input reset;

• //-----------Output Ports---------------

• output clk_out;

• //------------Internal Variables--------

• reg [1:0] pos_cnt;

• reg [1:0] neg_cnt;

• //-------------Code Start-----------------

• // Posedge counter

• always @ (posedge clk_in)

• if (reset) begin

• pos_cnt <= 0;

• end else begin

• pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;

• end

• // Neg edge counter

• always @ (negedge clk_in)

• if (reset) begin

• neg_cnt <= 0;

• end else begin

• neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;

• end

• assign clk_out = ((pos_cnt != 2) && (neg_cnt != 2));

• endmodule
FSM
• A sequence detector is a sequential state machine that takes an input
string of bits and generates an output 1 whenever the target sequence has
been detected. In a Mealy machine, output depends on the present state
and the external input (x). Hence, in the diagram, the output is written
outside the states, along with inputs. Sequence detector is of two types:

1. Overlapping
2. Non-Overlapping
• In an overlapping sequence detector, the last bit of one sequence becomes
the first bit of the next sequence. However, in a non-overlapping sequence
detector, the last bit of one sequence does not become the first bit of the
next sequence.
Examples : 101 Sequence Detector

For non overlapping case

For overlapping case

Moore (Non –Overlapping) Moore (Overlapping)

Mealy (Non-Overlapping) Mealy (Overlapping)