TC1044S Charge Pump DC-TO-DC Voltage Converter: Features General Description
TC1044S Charge Pump DC-TO-DC Voltage Converter: Features General Description
KIT
AVAILABLE
TC1044S
7 VOLTAGE–
RC 2 4
OSC OSCILLATOR
LEVEL CAP –
TRANSLATOR
6
LV
5
VOUT
INTERNAL
VOLTAGE
REGULATOR
LOGIC
NETWORK
TC1044S
GND
TC1044S
ELECTRICAL CHARACTERISTICS: TA = +25°C, V+ = 5V, COSC = 0, Test Circuit (Figure 1), unless otherwise
indicated.
Symbol Parameter Test Conditions Min Typ Max Unit
I +
Supply Current RL = ∞ — 80 160 µA
0°C < TA < +70°C — — 180
– 40°C < TA < +85°C — — 180
– 55°C < TA < +125°C — — 200
I+ Supply Current 0°C < TA < +70°C — — 300 µA
(Boost Pin = V+) – 40°C < TA < +85°C — — 350
– 55°C < TA < +125°C — — 400
+
VH2 Supply Voltage Range, High Min ≤ TA ≤ Max, 3 — 12 V
RL = 10 kΩ, LV Open
+
VL2 Supply Voltage Range, Low Min ≤ TA ≤ Max, 1.5 — 3.5 V
RL = 10 kΩ, LV to GND
ROUT Output Source Resistance IOUT = 20mA — 60 100 Ω
IOUT = 20mA, 0°C ≤ TA ≤ +70°C — 70 120
IOUT = 20mA, –40°C ≤ TA ≤ +85°C — 70 120
IOUT = 20mA, –55°C ≤ TA ≤ +125°C — 105 150
V+ = 2V, IOUT = 3 mA, LV to GND
0°C ≤ TA ≤ +70°C — — 250 Ω
– 55°C ≤ TA ≤ +125°C — — 400
FOSC Oscillator Frequency Pin 7 open; Pin 1 open or GND — 10 — kHz
Boost Pin = V+ — 45 —
PEFF Power Efficiency RL = 5 kΩ; Boost Pin Open 96 98 — %
TMIN < TA < TMAX; Boost Pin Open 95 97 —
Boost Pin = V+ — 88 —
VOUT EFF Voltage Conversion Efficiency RL = ∞ 99 99.9 — %
ZOSC Oscillator Impedance V+ = 2V — 1 — MΩ
V+ = 5V — 100 — kΩ
NOTES: 1. Connecting any input terminal to voltages greater than V+ or less than GND may cause destructive latch-up. It is recommended that no
inputs from sources operating from external supplies be applied prior to "power up" of the TC1044S.
2. Derate linearly above 50°C by 5.5mW/°C.
TC1044S
Circuit Description
S1 S2
The TC1044S contains all the necessary circuitry to V+
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF polar- C1
ized electrolytic capacitors. Operation is best understood by
considering Figure 2, which shows an idealized voltage
inverter. Capacitor C1 is charged to a voltage, V+, for the half C2
GND
cycle when switches S1 and S3 are closed. (Note: Switches S3 S4
S2 and S4 are open during this half cycle.) During the second VOUT = – VIN
half cycle of operation, switches S2 and S4 are closed, with
S1 and S3 open, thereby shifting capacitor C1 negatively by
V+ volts. Charge is then transferred from C1 to C2, such that
the voltage on C2 is exactly V+, assuming ideal switches and
no load on C2.
The four switches in Figure 2 are MOS power switches;
Figure 2. Idealized Charge Pump Inverter
S1 is a P-channel device, and S2, S3 and S4 are N-channel
devices. The main difficulty with this approach is that in The voltage regulator portion of the TC1044S is an
integrating the switches, the substrates of S3 and S4 must integral part of the anti-latch-up circuitry. Its inherent voltage
always remain reverse-biased with respect to their sources, drop can, however, degrade operation at low voltages. To
but not so much as to degrade their ON resistances. In improve low-voltage operation, the “LV” pin should be
addition, at circuit start-up, and under output short circuit connected to GND, disabling the regulator. For supply
conditions (VOUT = V+), the output voltage must be sensed voltages greater than 3.5V, the LV terminal must be left
and the substrate bias adjusted accordingly. Failure to open to ensure latch-up-proof operation and prevent device
accomplish this will result in high power losses and probable damage.
device latch-up.
This problem is eliminated in the TC1044S by a logic Theoretical Power Efficiency
network which senses the output voltage (VOUT) together Considerations
with the level translators, and switches the substrates of
S3 and S4 to the correct level to maintain necessary reverse In theory, a capacitive charge pump can approach
bias. 100% efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
V+ IS (3) The impedances of the pump and reservoir
1 8 capacitors are negligible at the pump frequency.
V+
2 7 (+5V) The TC1044S approaches these conditions for nega-
IL
C1 + TC1044S tive voltage multiplication if large values of C1 and C2 are
3 6 COSC*
1µF used. Energy is lost only in the transfer of charge
4 5 RL between capacitors if a change in voltage occurs. The
energy lost is defined by:
VOUT
E = 1/2 C1 (V12 – V22)
C2
V1 and V2 are the voltages on C1 during the pump and
+ 10µF
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of RL, there will be a substantial difference in
NOTE: For large values of COSC (>1000pF), the values
voltages V1 and V2. Therefore, it is desirable not only to
of C1 and C2 should be increased to 100µF.
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
Figure 1. TC1044S Test Circuit C1 in order to achieve maximum efficiency of operation.
© 2001 Microchip Technology Inc. DS21348A TC1044S-12 9/16/96
3
Charge Pump DC-TO-DC Voltage Converter
TC1044S
Dos and Don'ts The output characteristics of the circuit in Figure 3 are
those of a nearly ideal voltage source in series with 70Ω.
• Do not exceed maximum supply voltages. Thus, for a load current of –10mA and a supply voltage of
• Do not connect the LV terminal to GND for supply +5V, the output voltage would be – 4.3V.
voltages greater than 3.5V. The dynamic output impedance of the TC1044S is due,
primarily, to capacitive reactance of the charge transfer
• Do not short circuit the output to V+ supply for voltages capacitor (C1). Since this capacitor is connected to the
above 5.5V for extended periods; however, transient output for only 1/2 of the cycle, the equation is:
conditions including start-up are okay.
2
• When using polarized capacitors in the inverting mode, XC = = 3.18Ω,
2πf C1
the + terminal of C1 must be connected to pin 2 of the
TC1044S and the + terminal of C2 must be connected where f = 10 kHz and C1 = 10µF.
to GND.
Paralleling Devices
Simple Negative Voltage Converter Any number of TC1044S voltage converters may be
Figure 3 shows typical connections to provide a nega- paralleled to reduce output resistance (Figure 4). The reser-
tive supply where a positive supply is available. A similar voir capacitor, C2, serves all devices, while each device
scheme may be employed for supply voltages anywhere in requires its own pump capacitor, C1. The resultant output
the operating range of +1.5V to +12V, keeping in mind that resistance would be approximately:
pin 6 (LV) is tied to the supply negative (GND) only for supply
voltages below 3.5V.
ROUT (of TC1044S)
ROUT =
n (number of devices)
V+
1 8
2 7 VOUT*
C1 + TC1044S C2
10µF 3 6
+ 10µF
4 5
* NOTES:
V+
1 8
2 7 1 8
TC1044S
C1 3 6 RL
2 7
TC1044S
4 "1" 5 C1 3 6
4 "n" 5
C2
+
TC1044S
V+
1 8
2 7 1 8
+ TC1044S
10µF 3 6 2 7
TC1044S
+
4 "1" 5 10µF 3 6
4 "n" 5 VOUT*
10µF
+
* NOTES:
1. VOUT = –n(V+) for 1.5V ≤ V+ ≤ 12V 10µF
+
Cascading Devices situation where the designer has generated the external
clock frequency using TTL logic, the addition of a 10kΩ pull-
The TC1044S may be cascaded as shown (Figure 5) to
up resistor to V+ supply is required. Note that the pump
produce larger negative multiplication of the initial supply
frequency with external clocking, as with internal clocking,
voltage. However, due to the finite efficiency of each device,
will be 1/2 of the clock frequency. Output transitions occur on
the practical limit is 10 devices for light loads. The output
the positive-going edge of the clock.
voltage is defined by:
It is also possible to increase the conversion efficiency
of the TC1044S at low load levels by lowering the oscillator
VOUT = –n(VIN)
frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, COSC, as shown in
where n is an integer representing the number of devices
Figure 7. Lowering the oscillator frequency will cause an
cascaded. The resulting output resistance would be ap-
undesirable increase in the impedance of the pump (C1) and
proximately the weighted sum of the individual TC1044S
the reservoir (C2) capacitors. To overcome this, increase the
ROUT values.
values of C1 and C2 by the same factor that the frequency
has been reduced. For example, the addition of a 100pF
Changing the TC1044S Oscillator Frequency capacitor between pin 7 (OSC) and pin 8 (V+) will lower the
It may be desirable in some applications (due to noise or oscillator frequency to 1kHz from its nominal frequency of
other considerations) to increase the oscillator frequency. 10kHz (a multiple of 10), and necessitate a corresponding
Pin 1, frequency boost pin may be connected to V+ to increase in the values of C1 and C2 (from 10µF to 100µF).
increase oscillator frequency to 45kHz from a nominal of
10kHz for an input supply voltage of 5.0 volts. The oscillator Positive Voltage Multiplication
may also be synchronized to an external clock as shown in
The TC1044S may be employed to achieve positive
Figure 6. In order to prevent possible device latch-up, a 1kΩ
voltage multiplication using the circuit shown in Figure 8. In
resistor must be used in series with the clock output. In a
this application, the pump inverter switches of the TC1044S
are used to charge C1 to a voltage level of V+ – VF (where V+
V+ V+ is the supply voltage and VF is the forward voltage drop of
1 8 diode D1). On the transfer cycle, the voltage on C1 plus the
1kΩ
CMOS supply voltage (V+) is applied through diode D2 to capacitor
2 7
+ TC1044S
GATE C2. The voltage thus created on C2 becomes (2V+) – (2VF),
10µF 3 6 or twice the supply voltage minus the combined forward
4 5 VOUT
voltage drops of diodes D1 and D2.
The source impedance of the output (VOUT) will depend
+
10µF on the output current, but for V+ = 5V and an output current
of 10mA, it will be approximately 60Ω.
Figure 6. External Clocking
© 2001 Microchip Technology Inc. DS21348A TC1044S-12 9/16/96
5
Charge Pump DC-TO-DC Voltage Converter
TC1044S
will bypass the other (D1 and D2 in Figure 9 would never turn
+
V on), or else the diode and resistor shown dotted in Figure 10
1 8 can be used to "force" the internal regulator on.
COSC
2 7
+ Voltage Splitting
C1 3 TC1044S 6
The same bidirectional characteristics used in Figure 10
4 5 VOUT can also be used to split a higher supply in half, as shown in
C2 Figure 11. The combined load will be evenly shared be-
+
tween the two sides. Once again, a high value resistor to the
LV pin ensures start-up. Because the switches share the
Figure 7. Lowering Oscillator Frequency load in parallel, the output impedance is much lower than in
the standard circuits, and higher currents can be drawn from
Combined Negative Voltage Conversion the device. By using this circuit, and then the circuit of Figure
and Positive Supply Multiplication 5, +15V can be converted (via +7.5V and –7.5V) to a nominal
–15V, though with rather high series resistance (~250Ω).
Figure 9 combines the functions shown in Figures 3 and
8 to provide negative voltage conversion and positive volt-
age multiplication simultaneously. This approach would be, V+
for example, suitable for generating +9V and –5V from an VOUT = –V+
existing +5V supply. In this instance, capacitors C1 and C3 1 8
perform the pump and reservoir functions, respectively, for
2 7 C3
the generation of the negative voltage, while capacitors C2 TC1044S D1
+
and C4 are pump and reservoir, respectively, for the multi- 3 6
plied positive voltage. There is a penalty in this configuration VOUT =
4 5
which combines both functions, however, in that the source +
D2 (2 V +) – (2 VF)
C1
impedances of the generated supplies will be somewhat +
higher due to the finite impedance of the common charge +
C2
pump driver at pin 2 of the device. C4
4 5 + +
C1 C2
TC1044S
V+
VOUT = –V–
+
RL1 50 µF
1 8
1 8
+ VOUT = +
2 7
10µF TC1044S 1 MΩ
2 7 V + –V –
50 3 6
+ TC1044S 1 MΩ 2 100
C1 µF
3 6 kΩ 100 4 5
10µF RL2 kΩ
4 5
50 +
V– INPUT µF
V–
Figure 10. Positive Voltage Conversion Figure 11. Splitting a Supply in Half
TYPICAL CHARACTERISTICS
Unloaded Osc Freq vs. Temperature Unloaded Osc Freq vs. Temperature
with Boost Pin = VIN
12 60
OSCILLATOR FREQUENCY (kHz)
10 50
8 40
VIN = 5V
6 VIN = 5V 30
VIN = 12V
4 20
VIN = 12V
2 10
0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)
1000 101.0
100.5
800
Without Load
100.0
600 VIN = 12V
IDD (µA)
99.5
400 10K Load
99.0
200
VIN = 5V 98.5
TA = 25°C
0 98.0
-40 -20 0 20 40 60 80 100 1 2 3 4 5 6 7 8 9 10 11 12
TEMPERATURE (°C) INPUT VOLTAGE VIN (V)
© 2001 Microchip Technology Inc. DS21348A TC1044S-12 9/16/96
7
Charge Pump DC-TO-DC Voltage Converter
TC1044S
Output Source Resistance vs. Supply Voltage Output Source Resistance vs. Temperature
100 100
OUTPUT SOURCE RESISTANCE (Ω)
IOUT = 20mA 20
TA = 25°C
10 0
1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12 -40 -20 0 20 40 60 80 100
SUPPLY VOLTAGE (V) TEMPERATURE (°C)
Output Voltage vs. Output Current Power Conversion Efficiency vs. Load
0 100
90
-2 Boost Pin = Open
OUTPUT VOLTAGE VOUT (V)
80
Boost Pin = V+
POWER EFFICIENCY (%)
70
-4
60
-6 50
40
-8 30
20
-10
10
-12 0
0 10 20 30 40 50 60 70 80 90 100
4.5
15.0
50.0
3.0
10.0
40.0
60.0
2.0
35.0
1.5
9.0
30.0
1.0
7.5
25.0
6.0
20.0
55.0
OUTPUT CURRENT (mA)
LOAD CURRENT (mA)
150
125
100 VIN = 12.5V
75
50
VIN = 5.5V
25
0
-40 -20 0 20 40 60 80 100
TEMPERATURE (°C)
TC1044S
PACKAGE DIMENSIONS
8-Pin Plastic DIP
PIN 1
.260 (6.60)
.240 (6.10)
.200 (5.08)
.140 (3.56) .040 (1.02)
.020 (0.51) .015 (0.38) 3° MIN.
.150 (3.81) .008 (0.20)
.115 (2.92)
.400 (10.16)
.310 (7.87)
.110 (2.79) .022 (0.56)
.090 (2.29) .015 (0.38)
8-Pin CerDIP
.110 (2.79)
.090 (2.29)
PIN 1
.300 (7.62)
.230 (5.84)
.400 (10.16)
.320 (8.13)
.065 (1.65) .020 (0.51)
.045 (1.14) .016 (0.41)
Dimensions: inches (mm)
TC1044S
8-Pin SOIC
.197 (5.00)
.189 (4.80)
.069 (1.75)
.053 (1.35) .010 (0.25)
8° MAX.
.007 (0.18)
.020 (0.51) .010 (0.25)
.013 (0.33) .004 (0.10) .050 (1.27)
.016 (0.40)
TC1044S
01/09/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 1/01 Printed on recycled paper.
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