This document discusses the design of an NMOS inverter with a resistive load. It explains that the inverter consists of an NMOS transistor (MS) and a resistor (R) to pull the output high when MS is off. The size of R and the W/L ratio of MS must be chosen based on the supply voltage (VDD), threshold voltage (VTN), and desired power dissipation. It provides the equations needed to calculate the current (iD) through MS in different operating regions and select R to limit iD when the output is at the high voltage (VDD). Examples are included to demonstrate how to design an NMOS inverter for given VDD, power, and voltage levels
This document discusses the design of an NMOS inverter with a resistive load. It explains that the inverter consists of an NMOS transistor (MS) and a resistor (R) to pull the output high when MS is off. The size of R and the W/L ratio of MS must be chosen based on the supply voltage (VDD), threshold voltage (VTN), and desired power dissipation. It provides the equations needed to calculate the current (iD) through MS in different operating regions and select R to limit iD when the output is at the high voltage (VDD). Examples are included to demonstrate how to design an NMOS inverter for given VDD, power, and voltage levels
This document discusses the design of an NMOS inverter with a resistive load. It explains that the inverter consists of an NMOS transistor (MS) and a resistor (R) to pull the output high when MS is off. The size of R and the W/L ratio of MS must be chosen based on the supply voltage (VDD), threshold voltage (VTN), and desired power dissipation. It provides the equations needed to calculate the current (iD) through MS in different operating regions and select R to limit iD when the output is at the high voltage (VDD). Examples are included to demonstrate how to design an NMOS inverter for given VDD, power, and voltage levels
This document discusses the design of an NMOS inverter with a resistive load. It explains that the inverter consists of an NMOS transistor (MS) and a resistor (R) to pull the output high when MS is off. The size of R and the W/L ratio of MS must be chosen based on the supply voltage (VDD), threshold voltage (VTN), and desired power dissipation. It provides the equations needed to calculate the current (iD) through MS in different operating regions and select R to limit iD when the output is at the high voltage (VDD). Examples are included to demonstrate how to design an NMOS inverter for given VDD, power, and voltage levels
PART 1 650344 Digital Electronics Mones Omari Department of Communications and Electronics Engineering Philadelphia University NMOS Inverter with a Resistive Load
650344 Digital Electronics NMOS Logic Design 2
NMOS Inverter with a Resistive Load • MS is the switching transistor (NMOS)
• The resistor R is used to “pull” the output
high (VO = VH = VDD) when MS is off (VI = VL)
• The size of R and the W/L ratio of MS are
the design factors that need to be chosen
650344 Digital Electronics NMOS Logic Design 3
Design of an NMOS inverter with a Resistive Load • VO = VDS = VDD – RiD • When VI = VL • MS is in cutoff • iD = 0 → VO = VDS = VDD • VL must be less than VTN • As a design rule VL must be 25% to 50% of VTN • Ex. For VTN = 0.6V → VL must be from 0.15V to 0.30V • The dissipated power by the inverter • P = VDD iD → iD = P / VDD • Design W/L to provide iD when VO = VL
650344 Digital Electronics NMOS Logic Design 4
Design of an NMOS inverter with a Resistive Load • To design W/L we need to check the operation region for iD • For VDS > Vsat = VGS – VTN (saturation region) • iD = (KN/2)(VGS – VTN)2 • For VDS < Vsat = VGS – VTN (active region) • iD = (KN/2)[2(VGS – VTN)VDS – VDS2] • where KN = kN’ (W/L) • The load resistor is chosen to limit the current when VO = VL • For VO = VDD – RiD = VL • R = ( VDD – VL ) / iD
650344 Digital Electronics NMOS Logic Design 5
Load-Line Visualization
• For VDS = VDD – R iD, we can
draw a load-line at • VDS = 0 → iD = VDD / R • iD = 0 → VDS = VDD
650344 Digital Electronics NMOS Logic Design 6
Example 1 • Design an NMOS inverter with a resistive load for VDD = 2.5 V and P = 0.2 mW with VL = 0.2 V. Assume kN’ = 100 µA/V2 and VTN = 0.6 V. • Solution:
650344 Digital Electronics NMOS Logic Design 7
Example 1
650344 Digital Electronics NMOS Logic Design 8
Example 2 • Redesign the same logic gate in the previous example to operate at a power of 0.4 mW. • Solution:
650344 Digital Electronics NMOS Logic Design 9
Example 3 • Design an NMOS inverter with a resistive load for VDD = 3.3 V and P = 0.1 mW with VL = 0.2 V. Assume kN’ = 60 µA/V2 and VTN = 0.75 V. • Solution:
