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Tentative Outline CS-353 Computer Architecture CS Dept.

This document provides information about the CS-353 Computer Architecture course offered at the University of Gujrat. The course covers instruction set architecture, processor implementation techniques, memory hierarchy design, and input/output. It will teach students how to design and implement single cycle, multi-cycle, and pipelined processors with an emphasis on control units and functional units like ALUs and memory. The prerequisites are Computer Organization and Assembly Language and Digital Logic Design. The goals are to understand key processor components and how programs are executed, how architecture influences performance, and modern computer design.

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Mirza Abubakr
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290 views3 pages

Tentative Outline CS-353 Computer Architecture CS Dept.

This document provides information about the CS-353 Computer Architecture course offered at the University of Gujrat. The course covers instruction set architecture, processor implementation techniques, memory hierarchy design, and input/output. It will teach students how to design and implement single cycle, multi-cycle, and pipelined processors with an emphasis on control units and functional units like ALUs and memory. The prerequisites are Computer Organization and Assembly Language and Digital Logic Design. The goals are to understand key processor components and how programs are executed, how architecture influences performance, and modern computer design.

Uploaded by

Mirza Abubakr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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UNIVERSITY OF GUJRAT

CS-353: Computer Architecture

Course Code: CS-353 Course Title: Computer Architecture


Year Semester: Fall
Instructor’s Name: Najeeb-Ur-Rehman Office (Room No): 112
E-mail: najeeb.rehman@uog.edu.pk Office Hours:

Course Description Instruction Set Architecture/Design, Processor Implementation


Techniques, Memory Hierarchy Design, Input-Output. Design and
implementation of a single cycle, multi cycle, and pipelined processor
with emphasis on the implementation of control unit and performance of
the main functional units, i.e. ALU, Memory and registers.
Course Type: Core
(Compulsory/Core/
Elective)

Pre-requisites 1. Computer Organization and Assembly Language


2. Digital Logic Design
It is advance course in its nature as well as last course of this domain in this degree
program. As per academic scheme, Computer Organization and Assembly Language &
Digital Logic Design followed by Basic Electronics are mandatory as prerequisites.
Additionally, few concepts from programming subjects (Data Structures and Objected
Oriented Programming) are associated as well. Having interest in computing machines
hardware components makes more learnable.
Goals 1. To understand key components of processor
2. To understand how a high-level language program is actually executed on a
processor
3. To understand architecture could influence program behavior,
4. To grasp factors that could influence the evolution of processors and
computers.
5. To understand how modern computers are built
Books Title: Computer Organization & Design: The Hardware/Software Interface, 5th
Edition
Author: David A. Patterson & John L. Hennessy
Publisher: Morgan Kaufmann Publishers
Additional
1. Computer Organization & Architecture By William Stallings
Readings 2. Computer Organization & Design: A quantitative Approach By David A.
Patterson
3. Structured Computer Organization By Andrew S. Tanenbaum
Lectures 16

Grading Marks in Percentage Letter Grade Numeric Value of Grade


85 and above A+ 4.00
80-84 A 3.70
75-79 B+ 3.40
70-74 B 3.00
65-69 B- 2.50
60-64 C+ 2.00
55-59 C 1.50
50-54 D 1.00
49 and below F 0.0
W
I
Quizzes,
Assignments and
Presentation
Schedule
(tentative)

Session Schedule

Session Topic Readings

Week 1 Class Introduction, Defanging Success


Class Policies & Discipline
Course Learning Objectives and Its Outcomes
Introduction to Computer Architecture
Why to Study Computer Architecture
Week 2 Computer Evolution & History
Generations of Computer

Week 3 General Performance Balance (Memory, I/O Modules)


Evolution of Intel (x86)
Uniprocessor to Multiprocessor
Week 4 Instruction Set Architecture
Technologies for Building Processors and Memory

Week 5 Performance
Evaluating and Measuring Computer Performance
Power Wall : Consumption and Analysis
Week 6 Amdahl's Law
Performance Metrics
MIPS Instructions and its Operands
Week 7 Number System Review (Hexadecimal/Decimal/Binary)
Types of Instructions
Instruction Format
Conversion of Assembly to Machine Instructions
Week 8 Procedure Calling in MIPS & Addressing Modes

Week 9 Midterm Exams

Week 10 Constructing an ALU


Processor Data Path
Week 11 Single Cycle Processor Control
Multi Cycle Processor

Week 12 Cache
Cache introduction
Principle of Locality of reference
Cache organization
cache hit, cache miss, cache hit access time
Write-through, write-back, write-around schemes, dirty bit,
reading/writing cache, cache organization, Fully Associative
scheme, Direct Mapped scheme
Week 13 Cache Performance and Multilevel Caches

Week 14 Multicores, Multiprocessors and Clusters

Week 15 Control Unit Implementation


Concept of Pipelining
Pipeline Throughput Machine Cycles
Week 16 Presentations / Projects
Optional Contents:
Pipelining
Pipeline Hazards
Pipeline Stalls
Structural Data and Control Hazards
Pipelining of Functional Units

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