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Successive Approximation ADC - ECE Tutorials

The document discusses successive approximation analog-to-digital converters (ADCs). It explains that successive approximation ADCs replace the counter of a digital ramp ADC with a successive approximation register to speed up conversions. The successive approximation register tests bit values from most to least significant to iteratively approximate the analog input value. The conversion time of an N-bit successive approximation ADC is 3 clock cycles, making it faster than counter-based ADCs.

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174 views5 pages

Successive Approximation ADC - ECE Tutorials

The document discusses successive approximation analog-to-digital converters (ADCs). It explains that successive approximation ADCs replace the counter of a digital ramp ADC with a successive approximation register to speed up conversions. The successive approximation register tests bit values from most to least significant to iteratively approximate the analog input value. The conversion time of an N-bit successive approximation ADC is 3 clock cycles, making it faster than counter-based ADCs.

Uploaded by

braddlely nyakatangure
Copyright
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We take content rights seriously. If you suspect this is your content, claim it here.
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ECE Tutorials

Electronics and control Systems

Successive Approximation ADC

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Successive Approximation ADC (Analog to Digital Converter)

Successive approximation ADC is the advanced version of


Digital ramp type ADC which is designed to reduce the
conversion and to increase speed of operation. The major draw
of digital ramp ADC is the counter used to produce the digital
output will be reset after every sampling interval. The normal
counter starts counting from 0 and increments by one LSB in
each count, this result in 2N clock pulses to reach its maximum
value.

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In successive approximation ADC the normal counter is replaced


with successive approximation register as shown in below figure.
— Successive Approximation ADC

The successive approximation register counts by changing the


bits from MSB to LSB according to input. The detailed operation
is shown below.

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Operation of 3 bit Successive Approximation ADC

The output of SAR is converted to analog out by the DAC and


this analog output is compared with the input analog sampled
value in the Opamp comparator. This Opamp provides an high
or low clock pulse based on the difference through the logic
circuit. In very first case the 3 bit SAR enables its MSB bit as
high i.e. ‘1’ and the result will be “100”. This digita output is
converted to analog value and compared with input sampled
voltage (Vin). If the deference is positive i.e. if the sampled input
is high then the SAR enables the next bit from MSB and result
will be “110”. Now if the output is negative i.e. if the input
sampled voltage is less than the SAR resets the last set bit and
sets the next bit and resultant output in this case will be “101”
which will definitely approximately equal to the input analog
value. The counting sequence is explained by the following
counter flow chat as shown in below.

— Successive Approximation ADC


Counter Flow chat

— SAR ADC input output flow voltage


graph

Conversion time of Successive Approximation ADC

By observing above 3 bit example it is illustrated for a 3 bit ADC


the conversion time will be 3 clock pulses. Then;

N bit Successive Approximation ADC conversion time = 3T (T-


clock pulse).
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So to avoid aliasing effect the next sample of input signal should


be taken after 3 clock pulses.

Important note on Successive Approximation ADC

In Counter type or digital ramp type ADC the time taken for
conversion depends on the magnitude of the input, but in SAR
the conversion time is independent of the magnitude of the
input sampled value.

Advantages of Successive Approximation ADC

Speed is high compared to counter type ADC.


Good ratio of speed to power.
Compact design compared to Flash Type and it is
inexpensive.

Disadvantages of Successive Approximation ADC

Cost is high because of SAR


Complexity in design.

Applications

The SAR ADC will used widely data acquisition techniques at the
sampling rates higher than 10KHz

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