Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

DESCRIPTION QUICK REFERENCE DATA

Monolithic temperature and SYMBOL PARAMETER MAX. UNIT
overload protected logic level power
MOSFET in a 3 pin plastic VDS Continuous drain source voltage 50 V
envelope, intended as a general ID Continuous drain current 26 A
purpose switch for automotive PD Total power dissipation 75 W
systems and other applications. Tj Continuous junction temperature 150 ˚C
RDS(ON) Drain-source on-state resistance 60 mΩ
APPLICATIONS VIS = 5 V

General controller for driving

lamps
motors
solenoids
heaters

FEATURES FUNCTIONAL BLOCK DIAGRAM

Vertical power DMOS output
stage DRAIN
Low on-state resistance
Overload protection against
over temperature
Overload protection against O/V
short circuit load
Latched overload protection CLAMP
POWER
reset by input INPUT
5 V logic compatible input level RIG MOSFET
Control of power MOSFET
and supply of overload
protection circuits LOGIC AND
derived from input
Low operating input current PROTECTION
ESD protection on input pin
Overvoltage clamping for turn
off of inductive loads
SOURCE

Fig.1. Elements of the TOPFET.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION D
tab
TOPFET
1 input
2 drain I P
3 source

tab drain
1 23 S

January 1993 1 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDSS Continuous off-state drain source VIS = 0 V - 50 V
voltage
VIS Continuous input voltage - 0 6 V
ID Continuous drain current Tmb ≤ 25 ˚C; VIS = 5 V - 26 A
ID Continuous drain current Tmb ≤ 100 ˚C; VIS = 5 V - 16 A
IDRM Repetitive peak on-state drain current Tmb ≤ 25 ˚C; VIS = 5 V - 100 A
PD Total power dissipation Tmb ≤ 25 ˚C - 75 W
Tstg Storage temperature - -55 150 ˚C
Tj Continuous junction temperature1 normal operation - 150 ˚C
Tsold Lead temperature during soldering - 250 ˚C

OVERLOAD PROTECTION LIMITING VALUES

With the protection supply provided via the input pin, TOPFET can protect itself from two types of overload.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
2
VISP Protection supply voltage for valid protection 4 - V
Over temperature protection
VDDP(T) Protected drain source supply voltage VIS = 5 V - 50 V
Short circuit load protection
VDDP(P) Protected drain source supply voltage3 VIS = 5 V - 35 V
PDSM Instantaneous overload dissipation Tmb = 25 ˚C - 1.3 kW

OVERVOLTAGE CLAMPING LIMITING VALUES

At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
IDROM Repetitive peak clamping current VIS = 0 V - 26 A
EDSM Non-repetitive clamping energy Tmb ≤ 25 ˚C; IDM = 26 A; - 625 mJ
VDD ≤ 20 V; inductive load
EDRM Repetitive clamping energy Tmb ≤ 95 ˚C; IDM = 8 A; - 40 mJ
VDD ≤ 20 V; f = 250 Hz

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VC Electrostatic discharge capacitor Human body model; - 2 kV
voltage C = 250 pF; R = 1.5 kΩ

1 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch.
2 The input voltage for which the overload protection circuits are functional.
3 The device is able to self-protect against a short circuit load providing the drain-source supply voltage does not exceed VDDP(P) maximum.
For further information, refer to OVERLOAD PROTECTION CHARACTERISTICS.

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Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Thermal resistance
Rth j-mb Junction to mounting base - - 1.3 1.67 K/W
Rth j-a Junction to ambient in free air - 60 - K/W

STATIC CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(CL)DSS Drain-source clamping voltage VIS = 0 V; ID = 10 mA 50 - - V
V(CL)DSS Drain-source clamping voltage VIS = 0 V; IDM = 2 A; tp ≤ 300 µs; - - 70 V
δ ≤ 0.01
IDSS Zero input voltage drain current VDS = 12 V; VIS = 0 V - 0.5 10 µA
IDSS Zero input voltage drain current VDS = 50 V; VIS = 0 V - 1 20 µA
IDSS Zero input voltage drain current VDS = 40 V; VIS = 0 V; Tj = 125 ˚C - 10 100 µA
RDS(ON) Drain-source on-state VIS = 5 V; IDM = 13 A; tp ≤ 300 µs; - 45 60 mΩ
resistance δ ≤ 0.01

OVERLOAD PROTECTION CHARACTERISTICS

TOPFET switches off when one of the overload thresholds is reached. It remains latched off until reset by the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Short circuit load protection 1
Tmb = 25 ˚C; L ≤ 10 µH
EDS(TO) Overload threshold energy VDD = 13 V; VIS = 5 V - 0.4 - J
td sc Response time VDD = 13 V; VIS = 5 V - 0.8 - ms
Over temperature protection
Tj(TO) Threshold junction temperature VIS = 5 V; from ID ≥ 1 A2 150 - - ˚C

INPUT CHARACTERISTICS
Tmb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VIS(TO) Input threshold voltage VDS = 5 V; ID = 1 mA 1.0 1.5 2.0 V
IIS Input supply current VIS = 5 V; normal operation - 0.2 0.35 mA
VISR Protection reset voltage3 2.0 2.6 3.5 V
VISR Protection reset voltage Tj = 150 ˚C 1.0 - -
IISL Input supply current VIS = 5 V; protection latched 0.5 1.2 2.0 mA
V(BR)IS Input clamp voltage II = 10 mA 6 7 - V
RIG Input series resistance to gate of power MOSFET - 4 - kΩ

1 The short circuit load protection is able to save the device providing the instantaneous on-state dissipation is less than the limiting value for
PDSM, which is always the case when VDS is less than VDSP maximum. Refer to OVERLOAD PROTECTION LIMITING VALUES.
2 The over temperature protection feature requires a minimum on-state drain source voltage for correct operation. The specified minimum ID
ensures this condition.
3 The input voltage below which the overload protection circuits will be reset.

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Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

TRANSFER CHARACTERISTICS
Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 10 V; IDM = 13 A tp ≤ 300 µs; 10 16 - S
δ ≤ 0.01
ID(SC) Drain current1 VDS = 13 V; VIS = 5 V - 40 - A

SWITCHING CHARACTERISTICS
Tmb = 25 ˚C. RI = 50 Ω . Refer to waveform figures and test circuits.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
td on Turn-on delay time VDD = 13 V; VIS = 5 V - 2.5 - µs
tr Rise time resistive load RL = 2.1 Ω - 15 - µs
td off Turn-off delay time VDD = 13 V; VIS = 0 V - 10 - µs
tf Fall time resistive load RL = 2.1 Ω - 7 - µs
td on Turn-on delay time VDD = 10 V; VIS = 5 V - 2 - µs
tr Rise time inductive load IDM = 6 A - 4 - µs
td off Turn-off delay time VDD = 10 V; VIS = 0 V - 15 - µs
tf Fall time inductive load IDM = 6 A - 1 - µs

REVERSE DIODE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
IS Continuous forward current Tmb ≤ 25 ˚C - 26 A

REVERSE DIODE CHARACTERISTICS

Tmb = 25 ˚C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VSDS Forward voltage IS = 26 A; VIS = 0 V; tp = 300 µs - 1.0 1.5 V
trr Reverse recovery time not applicable2 - - - -

ENVELOPE CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ld Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die
Ld Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Ls Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad

1 During overload before short circuit load protection operates.

2 The reverse diode of this type is not intended for applications requiring fast reverse recovery.

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Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

PD% Normalised Power Derating Zth / (K/W) BUK101-50GL

120 10
110
100
90 D=
80 1 0.5
70
60 0.2
50 0.1
40 0.1 0.05
30 PD tp tp
D=
0.02 T
20
10 t
0 T
0 0.01
0 20 40 60 80 100 120 140 1E-07 1E-05 1E-03 1E-01 1E+01
Tmb / C t/s
Fig.2. Normalised power dissipation. Fig.5. Transient thermal impedance.
PD% = 100⋅PD/PD(25 ˚C) = f(Tmb) Zth j-mb = f(t); parameter D = tp/T

ID% Normalised Current Derating ID / A BUK101-50GL

120 80
110
70
100 VIS / V = 6
90 60
80
50
70
5
60 40
50
30 4
40
30 20
20 3
10
10
2
0 0
0 20 40 60 80 100 120 140 0 4 8 12 16 20 24 28
Tmb / C VDS / V
Fig.3. Normalised continuous drain current. Fig.6. Typical output characteristics, Tj = 25 ˚C.
ID% = 100⋅ID/ID(25 ˚C) = f(Tmb); conditions: VIS = 5 V ID = f(VDS); parameter VIS; tp = 250 µs & tp < td sc

ID & IDM / A BUK101-50GL ID / A BUK101-50GL

1000 50
Overload protection characteristics not shown

40
D VIS = 6 V VIS = 5 V
/I
100 DS tp =
) =V
ON 10 us 30
S(
RD
100 us VIS = 4 V
20
10
1 ms
DC 10
10 ms
100 ms
1 0
1 10 100 0 1 2 3 4 5
VDS / V VDS / V

Fig.4. Safe operating area. Tmb = 25 ˚C Fig.7. Typical on-state characteristics, Tj = 25 ˚C.
ID & IDM = f(VDS); IDM single pulse; parameter tp ID = f(VDS); parameter VIS; tp = 250 µs

January 1993 5 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

RDS(ON) / ohm BUK101-50GL a Normalised RDS(ON) = f(Tj)

0.20

(3V)
1.5
0.15

VIS = 4 V 5V 6V 1.0
0.10

0.05 0.5

0 0
0 20 40 60 80 -60 -40 -20 0 20 40 60 80 100 120 140
ID / A Tj / C
Fig.8. Typical on-state resistance, Tj = 25 ˚C. Fig.11. Normalised drain-source on-state resistance.
RDS(ON) = f(ID); parameter VIS; tp = 250 µs a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 13 A; VIS = 5 V

ID / A BUK101-50GL td sc / ms BUK101-50GL
50 100

40
NORMAL
10
30

PDSM
20
1
OVERLOAD
10 RESET
PROTECTION
LATCHED
0 0.1
0 1 2 3 4 5 0.1 1 10
VIS / V PDS / kW
Fig.9. Typical transfer characteristics, Tj = 25 ˚C. Fig.12. Typical overload protection characteristics.
ID = f(VIS) ; conditions: VDS = 10 V; tp = 250 µs td sc = f(PDS); conditions: VIS ≥ 4 V; Tj = 25 ˚C.

gfs / S BUK101-50GL PDSM%

26
24 120
22
20 100
18
16 80
14
12 60
10
8 40
6
4 20
2
0 0
0 10 20 30 40 50 60 -60 -40 -20 0 20 40 60 80 100 120 140
ID / A Tmb / C

Fig.10. Typical transconductance, Tj = 25 ˚C. Fig.13. Normalised limiting overload dissipation.

gfs = f(ID); conditions: VDS = 10 V; tp = 250 µs PDSM% =100⋅PDSM/PDSM(25 ˚C) = f(Tmb)

January 1993 6 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

Energy & Time BUK101-50GL II / uA BUK101-50GL

1 500

400
Time / ms Tj = 25 C
300
0.5
200 150 C
Energy / J
100
Tj(TO)
0 0
-60 -20 20 60 100 140 180 220 0 2 4 6 8 10
Tmb / C VIS / V
Fig.14. Typical overload protection characteristics. Fig.17. Typical DC input characteristics.
Conditions: VDD = 13 V; VIS = 5 V; SC load = 30 mΩ II = f(VIS); normal operation; parameter: Tj

ID / A BUK101-50GL IISL / mA BUK101-50GL

30 3

PROTECTION LATCHED

20 2

typ.
RESET
10 1
NORMAL

0 0
50 60 70 0 2 4 6 8
VIS / V VIS / V
Fig.15. Typical clamping characteristics, 25 ˚C. Fig.18. Typical DC input characteristics, Tj = 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 50 µs IISL = f(VIS); overload protection operated ⇒ ID = 0 A

VIS(TO) / V IS / A BUK101-50GL
100

max.
2

typ.

50
min.
1

0 0
-60 -40 -20 0 20 40 60 80 100 120 140 0 1 2
Tj / C VSD / V

Fig.16. Input threshold voltage. Fig.19. Typical reverse diode current, Tj = 25 ˚C.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V IS = f(VSDS); conditions: VIS = 0 V

January 1993 7 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

VDD VDD = VCL

RL LD
t p : adjust for correct ID

D D
TOPFET TOPFET

I I
P D.U.T. P D.U.T.
RI RI
VIS S VIS S
ID measure ID measure
0V 0V
0R1 0R1
Fig.20. Test circuit for resistive load switching times. Fig.23. Test circuit for inductive load switching times.

RESISTIVE TURN-ON BUK101-50GL INDUCTIVE TURN-ON BUK101-50GL

15 15

VDS / V

10 10
td on
tr
tr
td on
ID / A ID / A
90% 90%
5 5
VIS / V VIS / V

10% 10% VDS / V

0 0

0 10 20 30 40 50 0 10 20 30 40 50
time / us time / us
Fig.21. Typical switching waveforms, resistive load. Fig.24. Typical switching waveforms, inductive load.
VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C.

RESISTIVE TURN-OFF BUK101-50GL INDUCTIVE TURN-OFF BUK101-50GL

15 15

VDS / V
VDS / V
10 10

td off tf td off tf
ID / A

5 90% 5 90%
90% 90%
VIS / V VIS / V ID / A

10% 10%
0 0

0 5 10 15 20 0 5 10 15 20
time / us time / us
Fig.22. Typical switching waveforms, resistive load. Fig.25. Typical switching waveforms, inductive load.
VDD = 13 V; RL = 2.1 Ω; RI = 50 Ω, Tj = 25 ˚C. VDD = 10 V; ID = 6 A; RI = 50 Ω, Tj = 25 ˚C.

January 1993 8 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

EDSM% Iiso normalised to 25 C

120
110
100 1.5
90
80
70
60
50 1
40
30
20
10
0 0.5
0 20 40 60 80 100 120 140 -60 -20 20 60 100 140 180
Tmb / C Tj / C
Fig.26. Normalised clamping energy rating. Fig.29. Normalised input current (normal operation).
EDSM% = f(Tmb); conditions: ID = 26 A; VIS = 5 V IIS/IIS25 ˚C = f(Tj); VIS = 5 V

V(CL)DSS Iisl normalised to 25 C

VDS
VDD VDD
0 + 1.5
L
ID

VDS
0
D
-
VIS
TOPFET
-ID/100 1
0 D.U.T.
I P

Schottky R 01
RIS S shunt

0.5
-60 -20 20 60 100 140 180
Tj / C
Fig.27. Clamping energy test circuit, RIS = 50 Ω.
EDSM = 0.5 ⋅ LID2 ⋅ V(CL)DSS /(V(CL)DSS − VDD ) Fig.30. Normalised input current (protection latched).
IISL/IISL25 ˚C = f(Tj); VIS = 5 V

Idss
1 mA

100 uA

10 uA
typ.

1 uA

100 nA
0 20 40 60 80 100 120 140
Tj / C
Fig.28. Typical off-state leakage current.
IDSS = f(Tj); Conditions: VDS = 40 V; IIS = 0 V.

January 1993 9 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

MECHANICAL DATA

Dimensions in mm
4,5
Net Mass: 2 g max
10,3
max
1,3
3,7

2,8 5,9
min

15,8
max

3,0 max
3,0
not tinned
13,5
min
1,3
max 1 2 3
(2x) 0,9 max (3x)
0,6
2,54 2,54 2,4

Fig.31. TO220AB; pin 2 connected to mounting base.

Notes
1. Refer to mounting instructions for TO220 envelopes.
2. Epoxy meets UL94 V0 at 1/8".

January 1993 10 Rev 2.600

Philips Semiconductors Product specification

PowerMOS transistor BUK101-50GL

Logic level TOPFET

DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

January 1993 11 Rev 2.600