Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope using ’trench’ VDS Drain-source voltage 55 V
technology. The device features very ID Drain current (DC) 19.7 A
low on-state resistance and has Ptot Total power dissipation 61 W
integral zener diodes giving ESD Tj Junction temperature 175 ˚C
protection up to 2kV. It is intended for RDS(ON) Drain-source on-state 75 mΩ
use in automotive and general resistance VGS = 5 V
purpose switching applications.

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION
tab
d
1 gate

2 drain
g
3 source

tab drain 1 23 s

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ - 55 V
±VGS Gate-source voltage - - 10 V
ID Drain current (DC) Tmb = 25 ˚C - 19.7 A
ID Drain current (DC) Tmb = 100 ˚C - 13.9 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 79 A
Ptot Total power dissipation Tmb = 25 ˚C - 61 W
Tstg, Tj Storage & operating temperature - - 55 175 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VC Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-mb Thermal resistance junction to - - 2.46 K/W
mounting base
Rth j-a Thermal resistance junction to in free air 60 - K/W
ambient

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Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3
IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA
Tj = 175˚C - - 500 µA
IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA
Tj = 175˚C - 10 µA
±V(BR)GSS Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
RDS(ON) Drain-source on-state VGS = 5 V; ID = 10 A - 60 75 mΩ
resistance Tj = 175˚C - - 157 mΩ

DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 25 V; ID = 10 A 5 - - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF
Coss Output capacitance - 110 135 pF
Crss Feedback capacitance - 60 85 pF
td on Turn-on delay time VDD = 30 V; ID = 10 A; - 10 15 ns
tr Turn-on rise time VGS = 5 V; RG = 10 Ω - 47 70 ns
td off Turn-off delay time Resistive load - 28 40 ns
tf Turn-off fall time - 33 45 ns
Ld Internal drain inductance Measured from contact screw on - 3.5 - nH
tab to centre of die
Ld Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH
from package to centre of die
Ls Internal source inductance Measured from source lead 6 mm - 7.5 - nH
from package to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - 19.7 A
current
IDRM Pulsed reverse drain current - - 79 A
VSD Diode forward voltage IF = 19.7 A; VGS = 0 V - 0.95 1.2 V
trr Reverse recovery time IF = 19.7 A; -dIF/dt = 100 A/µs; - 32 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.12 - µC

April 1998 2 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS Drain-source non-repetitive ID = 10 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

PD% Normalised Power Derating 100

120
tp =
110
100 ID/A 1 us
RDS(ON) = VDS/ID
90
80 10us
70
60 10

50 100 us
40
30 DC
20 1 ms
10
10ms
0 100ms
0 20 40 60 80 100 120 140 160 180 1
1 10 100
Tmb / C VDS/V

Fig.1. Normalised power dissipation. Fig.3. Safe operating area. Tmb = 25 ˚C

PD% = 100⋅PD/PD 25 ˚C = f(Tmb) ID & IDM = f(VDS); IDM single pulse; parameter tp

ID% Normalised Current Derating Zth/ (K/W)

120 10

110
100
90
0.5
80 1
70 0.2
60
0.1
50 PD tp tp
D=
0.05 T
40 0.1 0.02
30 T t
20 0
10
0
0 20 40 60 80 100 120 140 160 180 0.01
1.0E-06 0.0001 0.01 1 100
Tmb / C t/s

Fig.2. Normalised continuous drain current. Fig.4. Transient thermal impedance.

ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Zth j-mb = f(t); parameter D = tp/T

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Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

50 Transconductance, gfs (S)

10.0 8.0 VGS/V = 15
ID/A 14
6.0
40 5.4 13
5.0
4.8 12
4.6
30 4.4 11
4.2
4.0 10
3.8 9
20
3.6
3.4 8
3.2
7
10 3.0
2.8 6
2.6
2.4 5
0 2.2 0 5 10 15 20 25
0 2 4 VDS/V 6 8 10 2.0 Drain current, ID (A)

Fig.5. Typical output characteristics, Tj = 25 ˚C. Fig.8. Typical transconductance, Tj = 25 ˚C.

ID = f(VDS); parameter VGS gfs = f(ID); conditions: VDS = 25 V

RDS(ON)/mOhm a BUK959-60 Rds(on) normlised to 25degC

90 2.5
VGS/V =
85
4 4.2
4.4 2
80
4.6 5
4.8
75
1.5
70

65 1

60
0.5
55 -100 -50 0 50 100 150 200
5 10 15 ID/A 20 25 Tmb / degC

Fig.6. Typical on-state resistance, Tj = 25 ˚C. Fig.9. Normalised drain-source on-state resistance.
RDS(ON) = f(ID); parameter VGS a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V

25 VGS(TO) / V BUK959-60
2.5
ID/A
max.
20
2

typ.
15 1.5

min.
10 1

5 0.5

Tj/C = 175 25
0 0
0 1 2 3 4 5 -100 -50 0 50 100 150 200
VGS/V Tj / C

Fig.7. Typical transfer characteristics. Fig.10. Gate threshold voltage.

ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

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Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

Sub-Threshold Conduction 100

1E-01
IF/A

80
1E-02

2% typ 98% 60
1E-03
Tj/C = 175 25

40
1E-04

20
1E-05

0
1E-05 0 0.5 1 1.5
0 0.5 1 1.5 2 2.5 3 VSDS/V

Fig.11. Sub-threshold drain current. Fig.14. Typical reverse diode current.

ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

1 WDSS%
120
.9 110
.8 100
90
Thousands pF

.7
80
.6 70
.5 60
Ciss
50
.4
40
.3 30
.2 20
10
.1 Coss
Crss 0
0 20 40 60 80 100 120 140 160 180
0.01 0.1 1 VDS/V 10 100 Tmb / C

Fig.12. Typical capacitances, Ciss, Coss, Crss. Fig.15. Normalised avalanche energy rating.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz WDSS% = f(Tmb); conditions: ID = 17 A

6
VGS/V VDD
5 +
VDS = 14V L

4 VDS
VDS = 44V

3 VGS
-
-ID/100
0 T.U.T.
2

R 01
1 RGS
shunt

0
0 2 4 6 8 10 12
QG/nC
Fig.16. Avalanche energy test circuit.
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 20 A; parameter VDS WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )

April 1998 5 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

VDD
+
RD

VDS

VGS
-
RG
0 T.U.T.

Fig.17. Switching test circuit.

April 1998 6 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

MECHANICAL DATA

Dimensions in mm
4,5
Net Mass: 2 g max
10,3
max
1,3
3,7

2,8 5,9
min

15,8
max

3,0 max
3,0
not tinned
13,5
min
1,3
max 1 2 3
(2x) 0,9 max (3x)
0,6
2,54 2,54 2,4

Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.

Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".

April 1998 7 Rev 1.100

Philips Semiconductors Product specification

TrenchMOS transistor BUK9575-55

Logic level FET

DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

April 1998 8 Rev 1.100