A B C D E

1 1

NSWAA/NTWAA
2
Liverpool 10G 2

Sunderland 10G
LA-5322P REV 1.0 Schematic
3
Intel Arrandale /IBEX PEAK 3

2009-12-22 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 1 of 58
A B C D E
 A B C D E

Compal Confidential Fan Control VGA Thermal Sensor Clock Generator

Intel Arrandale APL5607 ADM1032ARMZ-2 SLG8SP587VTR
Model Name : NSWAA/NTWAA page 6 page 21 page 22

File Name : LA-5322P

1 PCIE-Express 16X 2.5GHz 1

rPGA-988 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2

Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 800/1066 MT/s

VGA (DDR3)
ATI M92XTX,64bit with 256M/512MB USB/B BT conn
DMI X4 USB port 0,1 USB port 5
page 34 page 35
2.5GHz
ATI M96 Pro,128bit with 512MB/1GB
(Reserve) RTS5159E
3G 3IN1 Int. Camera
page 13,14,15,16,17,18,19,20,21 USB port 12 USB port 10 USB port 11
USB page 36 page 40 page 22
5V 480MHz

2 2
LCD Conn. CRT PCIeMini Card
page 22 page 23
WiMax
HDMI Conn. USB
USB port 13
5V 480MHz page 36
PCIe 1x PCIeMini Card
page 24 1.5V 2.5GHz(250MB/s) WLAN
PCIe port 1
page 36
Intel Ibex Peak
SATA port 1 SATA HDD0
Express Card (Reserve) 5V 3GHz(300MB/s) page 34
USB
USB port 8
5V 480MHz
Express Card (Reserve) PCIe 1x SATA port 4
BGA-951 SATA ODD
PCIe port 0 page 36 1.5V 2.5GHz(250MB/s) 5V 3GHz(300MB/s) page 34
3 3
RJ45 RTL8103EL-VB 10/100M PCIe 1x SATA port 5
page 37 PCIe port 2 page 37 1.5V 2.5GHz(250MB/s) 5V 3GHz(300MB/s)
page 25,26,27,28,29,30,31,32,33 eSATA USB
USB port 3 USB port 3
page 34 page 34
5V 480MHz

3.3V 33 MHz
LPC BUS

HD Audio 3.3V/1.5V 24MHz

Power/B RTC CKT. MDC 1.5 Conn HDA Codec AMP.

page 35 ALC272 TPA6017
page 28 SPI ROM Debug Port ENE KB926 D3 page 35 page 38 page 39
page 25 page 42 page 41
USB/B DC/DC Interface CKT.
page 34
page 44
Int.
Touch Pad EC ROM MIC CONN MIC CONN HP CONN SPK CONN
4
ODD/B for 17" Int.KBD page 39 page 39 page 39 page 39
4

page 34 page 35 page 35 page 42

Power Circuit DC/DC
page 45~54 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 2 of 58
A B C D E
 5 4 3 2 1

NSWAA Liverpool Intel Arrandale (Discrete)

NTWAA Sunderland Intel Arrandale (Discrete) B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW

SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
D D

TPS51125RGER
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
SUSP
N-CHANNEL DESIGN CURRENT 5A +3VS
SI4800 VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
C C
PCIE_OK
DESIGN CURRENT 100mA +3VS_DELAY
P-CHANNEL
AO-3413

VR_ON
DESIGN CURRENT 48A +CPU_CORE
ISL62883

SUSP#
DESIGN CURRENT 26A +VGA_CORE
APW7138

VTTP_EN#
Ipeak=18A, Imax=12.6A, Iocp min=20.64 DESIGN CURRENT 18A +VTT
APW7138
B B

SYSON
Ipeak=15A, Imax=10.5A, Iocp min=18.14 DESIGN CURRENT 15A +1.5V
APW7138 SUSP
DESIGN CURRENT 12A +1.5VS
N-CHANNEL
SI4856 SUSP
DESIGN CURRENT 1.5A +0.75VS
PCIE_OK
G2992F1U
DESIGN CURRENT 2A +1.1VS
SUSP# APL5913
Ipeak=4A, Imax=2.8A, Iocp min=4.98 DESIGN CURRENT 8A +1.8VS
TPS51117RGYR

SUSP#

Ipeak=7A, Imax=4.9A, Iocp min=8.54 DESIGN CURRENT 7A +1.05VS

A TPS51117RGYR A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 3 of 58
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails BTO Option Table
Function Bluetooth RJ11 Express Card MIC HDMI Panel M1/M3
+RTCVCC +B +5VALW +1.5V +5VS
+3VALW +3VS description (B) (E) (Y)
+VSB +1.5VS
1 power explain Bluetooth MDC New Card MIC HDMI 16" 17" M1 M3 1

plane +VGA_CORE
+CPU_CORE BTO BT@ MDC@ NEW@ MIC@ HDMI@ 16@ 17@ M1@ M3@
+VTT
+1.05VS
Function Mini Card VRAM GPU
+1.8VS
+1.1VS description
State +0.75VS
explain WIRELESS 256M 512M 1G M92 XTX M96 Pro

BTO WLAN@ 2PCS@ 4PCS@ 8PCS@ M92XTX@ M96PRO@

S0
O O O O O
SIGNAL
2 S1 STATE SLP_S3# SLP_S4# SLP_S5# 2
O O O O O
Full ON HIGH HIGH HIGH
S3
O O O O X S1(Power On Suspend) HIGH HIGH HIGH
S5 S4/AC
O O O X X S3 (Suspend to RAM) LOW HIGH HIGH

S5 S4/ Battery only S4 (Suspend to Disk) LOW LOW HIGH

O O X X X
S5 (Soft OFF) LOW LOW LOW
S5 S4/AC & Battery
don't exist
O X X X X G3 LOW LOW LOW

3 3

EC SM Bus1 address EC SM Bus2 address

Power Device Address Power Device Address
+3VALW EC KB926 D3 +3VS EC KB926 D3
+3VALW Smart Battery 0001 011x b +3VS VGA THM Sensor 1001 110x b
ADM1032ARMZ
+3VS PCH 0100 110x b

PCH SM Bus address

Power Device Address
+3VALW PCH

+3VS Clock Generator 1101 001x b

4 +3VS DDR DIMM0 1001 000x b 4

+3VS DDR DIMM1 1001 010x b

+3VS Express

+3VS WLAN/Wimax/3G
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 4 of 58
A B C D E
 5 4 3 2 1

JCPUB
1 2 H_COMP3 AT23
R1 20_0402_1% COMP3
BCLK A16 CLK_CPU_BCLK 30 2 1

MISC
1 2 H_COMP2 AT24 B16 CLK_CPU_BCLK# 30 R19 0_0402_5%
R2 20_0402_1% COMP2 BCLK#

CLOCKS
1 2 H_COMP1 G16 AR30 CLK_CPU_XDP_R 1 2 CLK_CPU_XDP
R4 49.9_0402_1% COMP1 BCLK_ITP CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP#
BCLK_ITP# AT30

D
1 2 H_COMP0 AT26 R42 @ 0_0402_5% SM_DRAMRST#_CPU 3 1
COMP0 SM_DRAMRST# 11,12
R3 49.9_0402_1% E16 CLK_PEG 26
PEG_CLK

1
D16 CLK_PEG# 26 Q41 @
TP_SKTOCC# PEG_CLK# BSS138_NL_SOT23-3

G
PAD T41 AH24

2
+VTT SKTOCC# @ R123
DPLL_REF_SSCLK A18 Unused by Clarksfield rPGA989
A17 100K_0402_5% RST_GATE 11,30
CATERR# DPLL_REF_SSCLK#
D 1 2 AK14 D

2
+VTT CATERR#

THERMAL
R18 49.9_0402_1%

2
C301 @
F6 SM_DRAMRST#_CPU 0.047U_0402_16V7K
SM_DRAMRST# C301 M96@
30 PECI AT15

1
PECI
2

SM_RCOMP[0] AL1 SM_RCOMP_0 R6 1 2 100_0402_1% 10K_0402_5%

R10 1 2 AM1 SM_RCOMP_1 R7 1 2 24.9_0402_1% DDR3 Compensation Signals
+VTT SM_RCOMP[1] Layout Note:Please these +VTT
68_0402_5% R9 68_0402_5% AN1 SM_RCOMP_2 R8 1 2 130_0402_1% 12/22: Modify for M96 and M96 Pro select
SM_RCOMP[2] resistors near Processor
@ 41,53 H_PROCHOT# 1 2H_PROCHOT#_D AN26 PROCHOT#
R40 0_0402_5% AN15 PM_EXTTS#0

DDR3
MISC
1

PM_EXT_TS#[0]
PM_EXT_TS#[1] AP15 PM_EXTTS#_R 2 1 PM_EXTTS# 11,12 PM_EXTTS#0 R15 2 1 10K_0402_5%
H_CPURST# R12 0_0402_5%
AK15 PM_EXTTS#_R R13 2 1 10K_0402_5%
30 H_THERMTRIP# THERMTRIP#

AT28 XDP_PRDY#
@ PRDY# XDP_PREQ# XDP_TDI_R XDP_TDI
13,29,36,37,41,42 PLT_RST# 2 1 PREQ# AP27 1 2
0_0402_5% R37 R20 0_0402_5%
AN28 XDP_TCK
XDP_RST#_R H_CPURST# TCK XDP_TMS XDP_TDO_M
1 2 AP26 RESET_OBS# TMS AP28 1 @ 2 XDP_TDO

PWR MANAGEMENT
R36 1K_0402_5% AT27 XDP_TRST# Routed as a single daisy chain R21 0_0402_5%
TRST#

1
JTAG & BPM
1 2 H_PMSYNCH AL15 AT29 XDP_TDI_R R23
27 PMSYNCH PM_SYNC TDI
R43 0_0402_5% AR27 XDP_TDO_R 0_0402_5%
TDO XDP_TDI_M
TDI_M AR29 2 1 +3VS
2 1 H_PWRGOOD1_R AN14 AP29 XDP_TDO_M R312 1K_0402_5%

2
+1.5V_CPU 0_0402_5% R25 VCCPWRGOOD_1 TDO_M XDP_TDI_M 1 @ 2
AN25 R26 0_0402_5%
DBR# XDP_DBRESET# 27
H_PWRGOOD 2 1 H_PWRGOOD0_R AN27
30 H_PWRGOOD VCCPWRGOOD_0
C 0_0402_5% R24 XDP_TDO_R 1 2 C
2

AJ22 XDP_BPM#0 R27 0_0402_5%

R28 DRAMPWROK BPM#[0]
27 DRAMPWROK 2 1 DRAMPWROK_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1 XDP_PRDY# 1 2
1.1K_0402_1% 0_0402_5% R69 AK24 XDP_BPM#2 @ C132 0.1U_0402_10V6K
BPM#[2] XDP_BPM#3 XDP_PREQ#
BPM#[3] AJ24 1 2
VTTPWROK_CPU AM15 AJ25 XDP_BPM#4 @ C93 0.1U_0402_10V6K
1

VTTPWRGOOD BPM#[4] XDP_BPM#5 XDP_TCK

BPM#[5] AH22 1 2
DRAMPWROK AK23 XDP_BPM#6 @ C95 0.1U_0402_10V6K
TAPPWRGD BPM#[6] XDP_BPM#7 XDP_TMS
AM26 TAPPWRGOOD BPM#[7] AH23 1 2
@ C96 0.1U_0402_10V6K JTAG MAPPING
2

XDP_TRST# 1 2
R29 @ R29 AL14 @ C130 0.1U_0402_10V6K
29 BUF_PLT_RST# RSTIN#
750_0402_1% 3K_0402_1% 1.5K_0402_1% R30 XDP_TDI 1 2 Scan Chain STUFF -> R20, R23, R27
@ C97 0.1U_0402_10V6K (Default) NO STUFF -> R21, R26
R31 XDP_TDO 1 2
1

750_0402_1% IC,AUB_CFD_rPGA,R0P9 @ C131 0.1U_0402_10V6K

@ XDP_DBRESET# 1 2 CPU Only STUFF -> R20, R21
@ C149 0.1U_0402_10V6K NO STUFF -> R23, R26, R27

GMCH Only STUFF -> R26, R27

EMI reverse, close to JCPU NO STUFF -> R20, R21, R23

Close to JCPU
@
+VTT
XDP Connector
VTTPWROK_CPU 2 1 2 1
C1 0.1U_0402_10V6K JXDP
B @ C384 1000P_0402_50V7K B
1 GND0 GND1 2
XDP_PREQ# 3 4
DRAMPWROK XDP_PRDY# OBSFN_A0 OBSFN_C0
2 1 5 OBSFN_A1 OBSFN_C1 6
7 GND2 GND3 8
+VTT @ C389 1000P_0402_50V7K XDP_BPM#0 9 10
XDP_BPM#1 OBSDATA_A0 OBSDATA_C0
11 OBSDATA_A1 OBSDATA_C1 12
13 GND4 GND5 14
XDP_BPM#2 15 16
OBSDATA_A2 OBSDATA_C2
1

XDP_BPM#3 17 18
R22 @ OBSDATA_A3 OBSDATA_C3
2 1 19 GND6 GND7 20
0_0402_5% R53 1K_0402_5% 21 22
OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
25 26
2

PMEG2010AEH_SOD123 XDP_BPM#4 GND8 GND9

27 OBSDATA_B0 OBSDATA_D0 28
1 2 VTTPWROK_CPU XDP_BPM#5 29 30
@ D54 OBSDATA_B1 OBSDATA_D1
31 GND10 GND11 32
XDP_BPM#6 33 34
XDP_BPM#7 OBSDATA_B2 OBSDATA_D2
35 OBSDATA_B3 OBSDATA_D3 36
@ R32 1K_0402_5% 37 38
+3VALW H_PWRGOOD 1 H_PWRGOOD_R GND12 GND13 CLK_CPU_XDP +VTT
2 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
41 42 CLK_CPU_XDP#
27 PM_PBTN_OUT# HOOK1 ITPCLK#/HOOK5
43 VCC_OBS_AB VCC_OBS_CD 44
TAPPWRGD 1 2 TAPPWRGD_R 45 46 XDP_RST#_R
HOOK2 RESET#/HOOK6
5

U10 @ @ R35 0_0402_5% 47 48 XDP_DBRESET#

VTTPWROK HOOK3 DBR#/HOOK7
44,49 VTTPWROK 1 49 50
P

IN1 @ DRAMPWROK GND14 GND15 XDP_TDO

O 4 PAD T1 51 SDA TD0 52 1 2
2 R33 1.5K_0402_1% PAD T2 53 54 XDP_TRST# R14 51_0402_5% 1
IN2 SCL TRST#

1
G

55 56 XDP_TDI
SN74AHC1G08DCKR_SC70-5 XDP_TCK TCK1 TDI XDP_TMS C2 @
57 58
3

A TCK0 TMS A
59 60 R11 0.1U_0402_10V6K
GND16 GND17 51_0402_5% 2
SAMTE_BSH-030-01-L-D-A @

2
2 @ 1
0_0402_5% R52
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 5 of 58
5 4 3 2 1
 5 4 3 2 1

+5VS
FAN Control Circuit
1SS355_SOD323-2
1A

1
D1
@

2
JFAN
2
+FAN1 1
C3 1
2 2
10U_0805_10V4Z 3 3

1
1
D 2 D
4 GND
U1 D2 C4 5
@ @ 1000P_0402_50V7K GND
1 EN GND 8
1
2 7 ACES_85204-0300N

2
+FAN1 VIN GND @
3 VOUT GND 6
4 5 BAS16_SOT23-3
41 EN_DFAN1 VSET GND
1 R34 10K_0402_5%
10mil APL5607KI-TRG_SO8 2 1 +3VS
C5
10U_0805_10V4Z FAN_SPEED1 41
2
2
C6
JCPUA 0.01U_0402_16V7K
PEG_COMP 1 1 @
PEG_ICOMPI B26 2
A26 R38 49.9_0402_1%
PEG_ICOMPO
27 DMI_PTX_CRX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27
C23 A25 PEG_RBIAS 1 2
27 DMI_PTX_CRX_N1 DMI_RX#[1] PEG_RBIAS
B22 R39 750_0402_1%
27 DMI_PTX_CRX_N2 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] 13
A21 K35 PCIE_GTX_C_CRX_N0
27 DMI_PTX_CRX_N3 DMI_RX#[3] PEG_RX#[0]
J34 PCIE_GTX_C_CRX_N1
PEG_RX#[1] PCIE_GTX_C_CRX_N2
27 DMI_PTX_CRX_P0 B24 DMI_RX[0] PEG_RX#[2] J33
D23 G35 PCIE_GTX_C_CRX_N3
27 DMI_PTX_CRX_P1 DMI_RX[1] PEG_RX#[3]
27
27
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3
B23
A22
DMI_RX[2] DMI PEG_RX#[4] G32
F34
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_N5
DMI_RX[3] PEG_RX#[5] PCIE_GTX_C_CRX_N6
PEG_RX#[6] F31
D24 D35 PCIE_GTX_C_CRX_N7
27 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
G24 E33 PCIE_GTX_C_CRX_N8
27 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
C F23 C33 PCIE_GTX_C_CRX_N9 C
27 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PCIE_GTX_C_CRX_N10
27 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_GTX_C_CRX_N11
PEG_RX#[11] PCIE_GTX_C_CRX_N12
27 DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31
F24 B28 PCIE_GTX_C_CRX_N13
27 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
E23 B30 PCIE_GTX_C_CRX_N14
27 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14]
G23 A31 PCIE_GTX_C_CRX_N15
27 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_GTX_C_CRX_P[0..15] 13
J35 PCIE_GTX_C_CRX_P0
PEG_RX[0] PCIE_GTX_C_CRX_P1
PEG_RX[1] H34
H33 PCIE_GTX_C_CRX_P2
PEG_RX[2] PCIE_GTX_C_CRX_P3
E22 FDI_TX#[0] PEG_RX[3] F35
D21 G33 PCIE_GTX_C_CRX_P4
FDI_TX#[1] PEG_RX[4] PCIE_GTX_C_CRX_P5
D19 FDI_TX#[2] PEG_RX[5] E34
D18 F32 PCIE_GTX_C_CRX_P6
FDI_TX#[3] PEG_RX[6] PCIE_GTX_C_CRX_P7
G21 FDI_TX#[4] PEG_RX[7] D34
PCI EXPRESS -- GRAPHICS

E19 F33 PCIE_GTX_C_CRX_P8

FDI_TX#[5] PEG_RX[8] PCIE_GTX_C_CRX_P9
F21 FDI_TX#[6] PEG_RX[9] B33
Intel(R) FDI

G18 D31 PCIE_GTX_C_CRX_P10

FDI_TX#[7] PEG_RX[10] PCIE_GTX_C_CRX_P11
PEG_RX[11] A32
C30 PCIE_GTX_C_CRX_P12
PEG_RX[12] PCIE_GTX_C_CRX_P13
D22 FDI_TX[0] PEG_RX[13] A28
C21 B29 PCIE_GTX_C_CRX_P14
FDI_TX[1] PEG_RX[14] PCIE_GTX_C_CRX_P15
D20 FDI_TX[2] PEG_RX[15] A30
C18 FDI_TX[3] PCIE_CTX_C_GRX_N[0..15] 13
G22 L33 PCIE_CTX_GRX_N0 C39 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0
FDI_TX[4] PEG_TX#[0] PCIE_CTX_GRX_N1 C40 0.1U_0402_16V7K PCIE_CTX_C_GRX_N1
E20 FDI_TX[5] PEG_TX#[1] M35 1 2
F20 M33 PCIE_CTX_GRX_N2 C41 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N2
FDI_TX[6] PEG_TX#[2] PCIE_CTX_GRX_N3 C42 0.1U_0402_16V7K PCIE_CTX_C_GRX_N3
G19 FDI_TX[7] PEG_TX#[3] M30 1 2
B PCIE_CTX_GRX_N4 C43 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4 B
PEG_TX#[4] L31 1 2
2 1 F17 K32 PCIE_CTX_GRX_N5 C44 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N5
R686 1K_0402_5% FDI_FSYNC[0] PEG_TX#[5] PCIE_CTX_GRX_N6 C45 0.1U_0402_16V7K PCIE_CTX_C_GRX_N6
E17 FDI_FSYNC[1] PEG_TX#[6] M29 1 2
J31 PCIE_CTX_GRX_N7 C46 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N7
PEG_TX#[7] PCIE_CTX_GRX_N8 C47 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8
2 1 C17 FDI_INT PEG_TX#[8] K29 1 2
R688 1K_0402_5% H30 PCIE_CTX_GRX_N9 C48 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9
PEG_TX#[9] PCIE_CTX_GRX_N10 C49 0.1U_0402_16V7K PCIE_CTX_C_GRX_N10
F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2
D17 F29 PCIE_CTX_GRX_N11 C50 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11
FDI_LSYNC[1] PEG_TX#[11] PCIE_CTX_GRX_N12 C51 0.1U_0402_16V7K PCIE_CTX_C_GRX_N12
PEG_TX#[12] E28 1 2
D29 PCIE_CTX_GRX_N13 C52 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
PEG_TX#[13] PCIE_CTX_GRX_N14 C53 0.1U_0402_16V7K PCIE_CTX_C_GRX_N14
PEG_TX#[14] D27 1 2
C26 PCIE_CTX_GRX_N15 C54 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15
PEG_TX#[15]
PCIE_CTX_C_GRX_P[0..15] 13
L34 PCIE_CTX_GRX_P0 C55 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0
PEG_TX[0] PCIE_CTX_GRX_P1 C56 0.1U_0402_16V7K PCIE_CTX_C_GRX_P1
PEG_TX[1] M34 1 2
M32 PCIE_CTX_GRX_P2 C57 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
PEG_TX[2] PCIE_CTX_GRX_P3 C58 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3
PEG_TX[3] L30 1 2
M31 PCIE_CTX_GRX_P4 C59 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4
PEG_TX[4] PCIE_CTX_GRX_P5 C60 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5
PEG_TX[5] K31 1 2
M28 PCIE_CTX_GRX_P6 C61 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P6
PEG_TX[6] PCIE_CTX_GRX_P7 C62 0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
PEG_TX[7] H31 1 2
K28 PCIE_CTX_GRX_P8 C63 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P8
PEG_TX[8] PCIE_CTX_GRX_P9 C64 0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
PEG_TX[9] G30 1 2
G29 PCIE_CTX_GRX_P10 C65 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P10
PEG_TX[10] PCIE_CTX_GRX_P11 C66 0.1U_0402_16V7K PCIE_CTX_C_GRX_P11
PEG_TX[11] F28 1 2
E27 PCIE_CTX_GRX_P12 C67 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P12
PEG_TX[12] PCIE_CTX_GRX_P13 C68 0.1U_0402_16V7K PCIE_CTX_C_GRX_P13
PEG_TX[13] D28 1 2
C27 PCIE_CTX_GRX_P14 C69 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P14
PEG_TX[14] PCIE_CTX_GRX_P15 C70 0.1U_0402_16V7K PCIE_CTX_C_GRX_P15
A PEG_TX[15] C25 1 2 A

IC,AUB_CFD_rPGA,R0P9
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 6 of 58
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD

11 DDR_A_D[0..63] 12 DDR_B_D[0..63]

SA_CK[0] AA6 DDRA_CLK0 11 SB_CK[0] W8 DDRB_CLK0 12

SA_CK#[0] AA7 DDRA_CLK0# 11 SB_CK#[0] W9 DDRB_CLK0# 12
P7 DDR_B_D0 B5 M3
SA_CKE[0] DDRA_CKE0 11 SB_DQ[0] SB_CKE[0] DDRB_CKE0 12
DDR_A_D0 A10 DDR_B_D1 A5
DDR_A_D1 SA_DQ[0] DDR_B_D2 SB_DQ[1]
C10 SA_DQ[1] C3 SB_DQ[2]
D DDR_A_D2 C7 DDR_B_D3 B3 V7 D
SA_DQ[2] SB_DQ[3] SB_CK[1] DDRB_CLK1 12
DDR_A_D3 A7 Y6 DDR_B_D4 E4 V6
SA_DQ[3] SA_CK[1] DDRA_CLK1 11 SB_DQ[4] SB_CK#[1] DDRB_CLK1# 12
DDR_A_D4 B10 Y5 DDR_B_D5 A6 M2
SA_DQ[4] SA_CK#[1] DDRA_CLK1# 11 SB_DQ[5] SB_CKE[1] DDRB_CKE1 12
DDR_A_D5 D10 P6 DDR_B_D6 A4
SA_DQ[5] SA_CKE[1] DDRA_CKE1 11 SB_DQ[6]
DDR_A_D6 E10 DDR_B_D7 C4
DDR_A_D7 SA_DQ[6] DDR_B_D8 SB_DQ[7]
A8 SA_DQ[7] D1 SB_DQ[8]
DDR_A_D8 D8 DDR_B_D9 D2
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F10 SA_DQ[9] SA_CS#[0] AE2 DDRA_SCS0# 11 F2 SB_DQ[10] SB_CS#[0] AB8 DDRB_SCS0# 12
DDR_A_D10 E6 AE8 DDR_B_D11 F1 AD6
SA_DQ[10] SA_CS#[1] DDRA_SCS1# 11 SB_DQ[11] SB_CS#[1] DDRB_SCS1# 12
DDR_A_D11 F7 DDR_B_D12 C2
DDR_A_D12 SA_DQ[11] DDR_B_D13 SB_DQ[12]
E9 SA_DQ[12] F5 SB_DQ[13]
DDR_A_D13 B7 DDR_B_D14 F3
DDR_A_D14 SA_DQ[13] DDR_B_D15 SB_DQ[14]
E7 SA_DQ[14] SA_ODT[0] AD8 DDRA_ODT0 11 G4 SB_DQ[15] SB_ODT[0] AC7 DDRB_ODT0 12
DDR_A_D15 C6 AF9 DDR_B_D16 H6 AD1
SA_DQ[15] SA_ODT[1] DDRA_ODT1 11 SB_DQ[16] SB_ODT[1] DDRB_ODT1 12
DDR_A_D16 H10 DDR_B_D17 G2
DDR_A_D17 SA_DQ[16] DDR_B_D18 SB_DQ[17]
G8 SA_DQ[17] J6 SB_DQ[18]
DDR_A_D18 K7 Unused by Clarksfield rPGA989 DDR_B_D19 J3
DDR_A_D19 SA_DQ[18] DDR_B_D20 SB_DQ[19]
J8 SA_DQ[19] G1 SB_DQ[20] DDR_B_DM[0..7] 12
DDR_A_D20 G7 DDR_B_D21 G5 D4 DDR_B_DM0
SA_DQ[20] DDR_A_DM[0..7] 11 SB_DQ[21] SB_DM[0]
DDR_A_D21 G10 DDR_B_D22 J2 E1 DDR_B_DM1
DDR_A_D22 SA_DQ[21] DDR_A_DM0 DDR_B_D23 SB_DQ[22] SB_DM[1] DDR_B_DM2
J7 SA_DQ[22] SA_DM[0] B9 J1 SB_DQ[23] SB_DM[2] H3
DDR_A_D23 J10 D7 DDR_A_DM1 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D24 SA_DQ[23] SA_DM[1] DDR_A_DM2 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
L7 SA_DQ[24] SA_DM[2] H7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D25 M6 M7 DDR_A_DM3 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D26 SA_DQ[25] SA_DM[3] DDR_A_DM4 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M8 SA_DQ[26] SA_DM[4] AG6 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D27 L9 AM7 DDR_A_DM5 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D28 SA_DQ[27] SA_DM[5] DDR_A_DM6 DDR_B_D29 SB_DQ[28] SB_DM[7]
L6 SA_DQ[28] SA_DM[6] AN10 K4 SB_DQ[29]
DDR_A_D29 K8 AN13 DDR_A_DM7 DDR_B_D30 M4 Unused by Clarksfield rPGA989
DDR_A_D30 SA_DQ[29] SA_DM[7] DDR_B_D31 SB_DQ[30]
N8 SA_DQ[30] N5 SB_DQ[31]
C DDR_A_D31 P9 DDR_B_D32 AF3 C
DDR_A_D32 SA_DQ[31] DDR_B_D33 SB_DQ[32]
AH5 SA_DQ[32] AG1 SB_DQ[33] DDR_B_DQS#[0..7] 12
DDR_A_D33 AF5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
SA_DQ[33] DDR_A_DQS#[0..7] 11 SB_DQ[34] SB_DQS#[0]
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR SYSTEM MEMORY A

DDR_A_D35 SA_DQ[34] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2

AK7 SA_DQ[35] SA_DQS#[1] F8 AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D37 AG3 L4 DDR_B_DQS#3
DDR_A_D37 SA_DQ[36] SA_DQS#[2] SB_DQ[37] SB_DQS#[3]
AG5 N9 DDR_A_DQS#3 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4

DDR SYSTEM MEMORY - B

DDR_A_D38 SA_DQ[37] SA_DQS#[3] SB_DQ[38] SB_DQS#[4]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 DDR_A_DQS#4 DDR_B_D39 AH4 SB_DQ[39] SB_DQS#[5] AL4 DDR_B_DQS#5
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D40 AK3 AR5 DDR_B_DQS#6
DDR_A_D40 SA_DQ[39] SA_DQS#[5] SB_DQ[40] SB_DQS#[6]
AJ10 SA_DQ[40] SA_DQS#[6] AP11 DDR_A_DQS#6 DDR_B_D41 AK4 SB_DQ[41] SB_DQS#[7] AR8 DDR_B_DQS#7
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D42 AM6
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D43 SB_DQ[42]
AL10 SA_DQ[42] AN2 SB_DQ[43]
DDR_A_D43 AK12 DDR_B_D44 AK5
DDR_A_D44 SA_DQ[43] DDR_B_D45 SB_DQ[44]
AK8 SA_DQ[44] AK2 SB_DQ[45]
DDR_A_D45 AL7 DDR_B_D46 AM4
SA_DQ[45] DDR_A_DQS[0..7] 11 SB_DQ[46]
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D47 AM3
SA_DQ[46] SA_DQS[0] SB_DQ[47] DDR_B_DQS[0..7] 12
DDR_A_D47 AL8 F9 DDR_A_DQS1 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D48 SA_DQ[47] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AN8 SA_DQ[48] SA_DQS[2] H9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D49 AM10 M9 DDR_A_DQS3 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D50 SA_DQ[49] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AR11 SA_DQ[50] SA_DQS[4] AH8 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D51 AL11 AK10 DDR_A_DQS5 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D52 SA_DQ[51] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AM9 SA_DQ[52] SA_DQS[6] AN11 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D53 AN9 AR13 DDR_A_DQS7 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D54 SA_DQ[53] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AT11 SA_DQ[54] AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D55 AP12 DDR_B_D56 AN7
DDR_A_D56 SA_DQ[55] DDR_B_D57 SB_DQ[56]
AM12 SA_DQ[56] DDR_A_MA[0..15] 11 AP6 SB_DQ[57]
DDR_A_D57 AN12 DDR_B_D58 AP8
DDR_A_D58 SA_DQ[57] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AM13 SA_DQ[58] SA_MA[0] Y3 AT9 SB_DQ[59]
DDR_A_D59 AT14 W1 DDR_A_MA1 DDR_B_D60 AT7
B DDR_A_D60 SA_DQ[59] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] B
AT12 SA_DQ[60] SA_MA[2] AA8 AP9 SB_DQ[61]
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D62 AR10
SA_DQ[61] SA_MA[3] SB_DQ[62] DDR_B_MA[0..15] 12
DDR_A_D62 AR14 V1 DDR_A_MA4 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D63 SA_DQ[62] SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[0] DDR_B_MA1
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[1] V2
V8 DDR_A_MA6 T5 DDR_B_MA2
SA_MA[6] DDR_A_MA7 SB_MA[2] DDR_B_MA3
SA_MA[7] T1 SB_MA[3] V3
Y9 DDR_A_MA8 R1 DDR_B_MA4
SA_MA[8] DDR_A_MA9 SB_MA[4] DDR_B_MA5
11 DDR_A_BS0 AC3 SA_BS[0] SA_MA[9] U6 12 DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
AB2 AD4 DDR_A_MA10 W5 R2 DDR_B_MA6
11 DDR_A_BS1 SA_BS[1] SA_MA[10] 12 DDR_B_BS1 SB_BS[1] SB_MA[6]
U7 T2 DDR_A_MA11 R7 R6 DDR_B_MA7
11 DDR_A_BS2 SA_BS[2] SA_MA[11] 12 DDR_B_BS2 SB_BS[2] SB_MA[7]
U3 DDR_A_MA12 R4 DDR_B_MA8
SA_MA[12] DDR_A_MA13 SB_MA[8] DDR_B_MA9
SA_MA[13] AG8 SB_MA[9] R5
T3 DDR_A_MA14 AC5 AB5 DDR_B_MA10
SA_MA[14] 12 DDR_B_CAS# SB_CAS# SB_MA[10]
AE1 V9 DDR_A_MA15 Y7 P3 DDR_B_MA11
11 DDR_A_CAS# SA_CAS# SA_MA[15] 12 DDR_B_RAS# SB_RAS# SB_MA[11]
AB3 AC6 R3 DDR_B_MA12
11 DDR_A_RAS# SA_RAS# 12 DDR_B_WE# SB_WE# SB_MA[12]
AE9 AF7 DDR_B_MA13
11 DDR_A_WE# SA_WE# SB_MA[13]
P5 DDR_B_MA14
SB_MA[14] DDR_B_MA15
SB_MA[15] N1

IC,AUB_CFD_rPGA,R0P9
@

A A
IC,AUB_CFD_rPGA,R0P9
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 7 of 58
5 4 3 2 1
 5 4 3 2 1

Material Note (+VTT):

JCPUF 330uF/ 6mohm, number are 3,
power x1, HW x2

+CPU_CORE Clarksfield: 65A Clarksfield: 21A (Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)
+VTT
Auburndale:48A Auburndale:18A +CPU_CORE
AG35 VCC1 VTT0_1 AH14
AG34 AH12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
D VCC2 VTT0_2 D
AG33 VCC3 VTT0_3 AH11
AG32 AH10 @ 1 1 1 1 1 1 1 1 1
VCC4 VTT0_4 C80 1 2 330U_D2E_2.5VM_R6M C81 1 2 10U_0805_10V4K

+
AG31 VCC5 VTT0_5 J14
AG30 J13 @
VCC6 VTT0_6 C82 1 2 330U_D2E_2.5VM_R6M C83 1 2 10U_0805_10V4K C71 C72 C73 C74 C75 C76 C77 C78 C79

+
AG29 VCC7 VTT0_7 H14
@ 2 2 2 2 2 2 2 2 2
AG28 VCC8 VTT0_8 H12
C84 1 2 330U_D2E_2.5VM_R6M C85 1 2 10U_0805_10V4K

+
AG27 VCC9 VTT0_9 G14
AG26 G13 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC10 VTT0_10 C89 1
AF35 VCC11 VTT0_11 G12 2 10U_0805_10V4K
AF34 VCC12 VTT0_12 G11
AF33 F14 C87 1 2 22U_0805_6.3V6M C88 1 2 10U_0805_10V4K
VCC13 VTT0_13
AF32 VCC14 VTT0_14 F13
AF31 F12 C91 1 2 22U_0805_6.3V6M C90 1 2 10U_0805_10V4K
VCC15 VTT0_15
AF30 VCC16 VTT0_16 F11 (Place these capacitors under CPU socket, top layer)
AF29 E14 C92 1 2 10U_0805_10V4K
VCC17 VTT0_17
AF28 VCC18 VTT0_18 E12
AF27 D14 C94 1 2 10U_0805_10V4K@ +CPU_CORE
VCC19 VTT0_19
AF26 VCC20 VTT0_20 D13 Co-layout with C80, C82
1.1V RAIL POWER
AD35 D12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC21 VTT0_21
AD34 VCC22 VTT0_22 D11
AD33 C14 +VTT
VCC23 VTT0_23 1 1 1 1 1 1 1
AD32 VCC24 VTT0_24 C13
AD31 VCC25 VTT0_25 C12
AD30 C11 1 1 C98 C99 C100 C101 C102 C103 C104
VCC26 VTT0_26 2 2 2 2 2 2 2
AD29 VCC27 VTT0_27 B14
AD28 B12 C144 + + C159
VCC28 VTT0_28 390U_2.5V_M_R10 390U_2.5V_M_R10 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AD27 VCC29 VTT0_29 A14
AD26 VCC30 VTT0_30 A13
2 2
AC35 VCC31 VTT0_31 A12
AC34 VCC32 VTT0_32 A11
AC33 VCC33
C
AC32 VCC34 (Place these capacitors on CPU cavity, Bottom Layer) C
AC31 VCC35 5/25: Add for power team request.
AC30 VCC36 VTT0_33 AF10
AC29 AE10 +CPU_CORE
VCC37 VTT0_34 +CPU_CORE
AC28 VCC38 VTT0_35 AC10
CPU CORE SUPPLY

AC27 AB10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 VCC41 VTT0_38 W10 1 1 1 1 1 1
AA34 U10 1 1 1 1 1 1 1 1 1 C105 C106 C107 C108 C109 C110
VCC42 VTT0_39 C158 C150 C128 C127 C120 C118 C119 C117 C129
AA33 VCC43 VTT0_40 T10
AA32 J12 @ @
VCC44 VTT0_41 2 2 2 2 2 2
AA31 VCC45 VTT0_42 J11
2 2 2 2 2 2 2 2 2
AA30 VCC46 VTT0_43 J16
AA29 J15 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC47 VTT0_44 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA28 VCC48
AA27 VCC49
AA26 VCC50
Y35 +CPU_CORE
VCC51
Y34 VCC52
Y33 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC53
Y32 VCC54
Y31 VCC55 1 1 1 1 1 1
Y30 C111 C112 C113 C114 C115 C116
VCC56
Y29 VCC57
Y28 VCC58 2 2 2 2 2 2
Y27 VCC59
Y26 VCC60 CRB default setting:
V35 AN33 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC61 PSI# H_PSI# 53
V34 VID[6:0]=[0100111]
POWER

VCC62
V33 VCC63
V32 VCC64 VID[0] AK35 CPU_VID0 53
V31 VCC65 VID[1] AK33 CPU_VID1 53
V30 VCC66 VID[2] AK34 CPU_VID2 53
B B
V29 VCC67 VID[3] AL35 CPU_VID3 53 VTT Rail
CPU VIDS

V28 VCC68 VID[4] AL33 CPU_VID4 53 TOP side (under inductor)

V27 VCC69 VID[5] AM33 CPU_VID5 53
V26 VCC70 VID[6] AM35 CPU_VID6 53 Auburndale +1.1VS_VTT=1.05V +CPU_CORE +CPU_CORE
U35 AM34 H_DPRSLPVR_R 1 2 H_DPRSLPVR 53
U34
VCC71 PROC_DPRSLPVR R62 0_0402_5% Clarksfield +1.1VS_VTT=1.1V
VCC72 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
U33 VCC73
U32 VCC74 1 1 1 1 1 1 1 1
U31 VCC75 VTT_SELECT G15 H_VTTSELECT 49
U30 H_VTTSELECT = low, 1.1V C148 + C121 + C124 + C122 +
C123 + C125 + C126 + + C218
VCC76 @ @ @ 560U_2.5V_M
U29 VCC77
U28 H_VTTSELECT = high, 1.05V 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M @
VCC78 2 2 2 2 2 2 2 2
U27 VCC79
U26 VCC80
R35 VCC81 Co-layout with C126
R34 VCC82
R33 VCC83
R32 VCC84 ISENSE AN35 IMVP_IMON 53 9/11: Add for power team request.
R31 VCC85
R30 VCC86 1 2 +CPU_CORE
R29 R64 100_0402_1%
VCC87 VCCSENSE_R R65 VCCSENSE
2 0_0402_5%
SENSE LINES

R28 VCC88 VCC_SENSE AJ34 1 VCCSENSE 53

R27 AJ35 VSSSENSE_R R66 1 2 0_0402_5% VSSSENSE
VCC89 VSS_SENSE VSSSENSE 53
R26 VCC90
P35 VCC91 1 2
P34 B15 R67 100_0402_1%
VCC92 VTT_SENSE VTT_SENSE 49
P33 VCC93 VSS_SENSE_VTT A15 VSS_SENSE_VTT 49
P32 VCC94 near CPU
P31 VCC95
P30 VCC96
P29 VCC97
P28 VCC98
A A
P27 VCC99
P26 VCC100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
IC,AUB_CFD_rPGA,R0P9
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 8 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU +1.5V
Q33 @
1 S D 8
2 S D 7

2
1 3 S D 6
@ R424 C179 @ 4 5
470_0805_5% G D
10U_0805_10V4K FDS6676AS_SO8 @
2
1 R418 2 +VSB

3 1
220K_0402_5%
D D

6
@ Q46B 1
@ C472 R417 @ Q46A @
SUSP 5 820K_0402_5%
0.1U_0402_25V6 2 SUSP
2 SUSP 44,52
2N7002DW-T/R7_SOT363-6

2
2N7002DW-T/R7_SOT363-6

1
JCPUG

AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22

SENSE
LINES
AT18 VAXG3 VSSAXG_SENSE AT22
AT16 VAXG4
2

AR21 VAXG5
R86 AR19 VAXG6
0_0402_5% AR18 VAXG7
AR16 VAXG8 GFX_VID[0] AM22
AP21 AP22
1

VAXG9 GFX_VID[1]

GRAPHICS VIDs
AP19 AN22 C205 1 2 0.1U_0402_16V4Z
VAXG10 GFX_VID[2]
AP18 VAXG11 GFX_VID[3] AP23
AP16 AM23 C186 1 2 0.1U_0402_16V4Z
VAXG12 GFX_VID[4]
AN21 VAXG13 GFX_VID[5] AP24

GRAPHICS
AN19 AN24 C185 1 2 0.1U_0402_16V4Z
VAXG14 GFX_VID[6]
AN18 VAXG15
AN16 C180 1 2 0.1U_0402_16V4Z
VAXG16
AM21 VAXG17 GFX_VR_EN AR25
AM19 VAXG18 GFX_DPRSLPVR AT25
AM18 AM24 R687 2 1 1K_0402_5%
C
VAXG19 GFX_IMON PJ30 @ C
AM16 VAXG20
AL21 VAXG21 2 2 1 1
AL19 VAXG22
AL18 +1.5V_CPU JUMP_43X79
VAXG23 PJ31 @
AL16 VAXG24
AK21 AJ1 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M 2 1 +1.5V
VAXG25 VDDQ1 2 1
AK19 VAXG26 VDDQ2 AF1 1
JUMP_43X79

- 1.5V RAILS
AK18 VAXG27 VDDQ3 AE7 1 1 1 1 1 1 1
+ C140
AK16 VAXG28 Clarksfield: 5A VDDQ4 AE4 Reserve for EMI request
AJ21 AC1 C133 C134 C135 C136 C137 C138 C139
VAXG29 VDDQ5 330U_D2E_2.5VM_R9M
AJ19 VAXG30 Auburndale:3A VDDQ6 AB7
2 2 2 2 2 2 2 2 Co-layout with C140 +1.5V_CPU +1.5V
AJ18 VAXG31 VDDQ7 AB4
AJ16 Y1 @
VAXG32 VDDQ8 +1.5V_CPU
AH21 VAXG33 VDDQ9 W7
POWER

AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M

VAXG34 VDDQ10
AH18 VAXG35 VDDQ11 U1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AH16 VAXG36 VDDQ12 T7 1
T4 @ 1 @ 1 @ 1 @ 1
VDDQ13 C216 +
VDDQ14 P1
+VTT

C160

C256

C258

C257
N7 390U_2.5V_M_R10
VDDQ15
VDDQ16 N4
2 2 2 2 2
DDR3

VDDQ17 L1
J24 VTT1_45 VDDQ18 H1
FDI

J23 VTT1_46
H25 +VTT
1 1 VTT1_47
C141 C142
(Place these capacitors under CPU socket Edge, top layer)
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1
2 2 VTT0_59 C143
VTT0_60 N10
B B
VTT0_61 L10
K10 10U_0805_10V4K
VTT0_62 2
Clarksfield: 21A
+VTT
+VTT Auburndale:18A
1.1V

VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 1
PEG & DMI

1 1 J26 H21 C145

C146 C147 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54 (Place these capacitors under CPU socket, top layer)
G26 VTT1_55
F26 +1.8VS
VTT1_56
E26 VTT1_57 VCCPLL1 L26
1.8V

E25 VTT1_58 VCCPLL2 L27

M26 +1.8VS_H_PLL 1U_0402_6.3V4Z 4.7U_0603_6.3V6K 2 1
VCCPLL3 R71 0_0805_5%
1 1 1 1
(Place these capacitors under CPU socket, top layer) Clarksfield: 0.6A C151 C152 C153 C154 C155
Auburndale:0.6A 1U_0402_6.3V4Z
2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R0P9 2.2U_0603_6.3V4Z
@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 9 of 58
5 4 3 2 1
 5 4 3 2 1

JCPUI JCPUH JCPUE

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
K27 VSS161 AR31 VSS3 VSS83 AE32
K9 VSS162 AR28 VSS4 VSS84 AE31 AP25 RSVD1
K6 VSS163 AR26 VSS5 VSS85 AE30 AL25 RSVD2 RSVD34 AH25
D K3 VSS164 AR24 VSS6 VSS86 AE29 AL24 RSVD3 RSVD35 AK26 D
J32 VSS165 AR23 VSS7 VSS87 AE28 AL22 RSVD4
J30 VSS166 AR20 VSS8 VSS88 AE27 AJ33 RSVD5 RSVD36 AL26
J21 VSS167 AR17 VSS9 VSS89 AE26 AG9 RSVD6 RSVD_NCTF_37 AR2
J19 VSS168 AR15 VSS10 VSS90 AE6 M27 RSVD7
H35 VSS169 AR12 VSS11 VSS91 AD10 L28 RSVD8 RSVD38 AJ26
H32 VSS170 AR9 VSS12 VSS92 AC8 +VREF_DQA_M3 J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27
H28 VSS171 AR6 VSS13 VSS93 AC4 +VREF_DQB_M3 H17 RSVD10(SB_DIMM_VREF)
H26 VSS172 AR3 VSS14 VSS94 AC2 G25 RSVD11
H24 VSS173 AP20 VSS15 VSS95 AB35 G17 RSVD12
H22 VSS174 AP17 VSS16 VSS96 AB34 E31 RSVD13 RSVD_NCTF_40 AP1
H18 VSS175 AP13 VSS17 VSS97 AB33 E30 RSVD14 RSVD_NCTF_41 AT2
H15 VSS176 AP10 VSS18 VSS98 AB32
H13 VSS177 AP7 VSS19 VSS99 AB31 RSVD_NCTF_42 AT3
H11 VSS178 AP4 VSS20 VSS100 AB30 RSVD_NCTF_43 AR1
H8 VSS179 AP2 VSS21 VSS101 AB29 WW41 Recommend not pull down
H5 VSS180 AN34 VSS22 VSS102 AB28 PCIE2.0 Jitter is over on ES1
H2 VSS181 AN31 VSS23 VSS103 AB27
G34 VSS182 AN23 VSS24 VSS104 AB26 RSVD45 AL28
G31 AN20 AB6 3.01K_0402_1% 1 @ R74 2 CFG0 AM30 AL29
VSS183 VSS25 VSS105 CFG1 CFG[0] RSVD46
G20 VSS184 AN17 VSS26 VSS106 AA10 AM28 CFG[1] RSVD47 AP30
G9 AM29 Y8 CFG2 AP31 AP32
VSS185 VSS27 VSS107 3.01K_0402_1% 1 @ R75 CFG3 CFG[2] RSVD48
G6 VSS186 AM27 VSS28 VSS108 Y4 2 AL32 CFG[3] RSVD49 AL27
G3 AM25 Y2 3.01K_0402_1% 1 @ R76 2 CFG4 AL30 AT31
VSS187 VSS29 VSS109 CFG5 CFG[4] RSVD50
F30 VSS188 AM20 VSS30 VSS110 W35 AM31 CFG[5] RSVD51 AT32
F27 AM17 W34 CFG6 AN29 AP33
VSS189 VSS31 VSS111 CFG7 CFG[6] RSVD52
F25 VSS190 AM14 VSS32 VSS112 W33 AM32 CFG[7] RSVD53 AR33
F22 AM11 W32 CFG8 AK32 AT33
VSS191 VSS33 VSS113 CFG9 CFG[8] RSVD_NCTF_54
F19 AM8 W31 AK31 AT34

RESERVED
C
VSS192 VSS34 VSS114 CFG10 CFG[9] RSVD_NCTF_55 C
F16 VSS193 AM5 VSS35 VSS115 W30 AK28 CFG[10] RSVD_NCTF_56 AP35
E35 AM2 W29 CFG11 AJ28 AR35
VSS194 VSS36 VSS116 CFG[11] RSVD_NCTF_57
E32 AL34 W28 AN30 AR32
E29
E24
VSS195
VSS196
VSS197
VSS AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
CFG13
CFG14
AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58

E21 AL20 W6 CFG15 AJ29 E15

VSS198 VSS40 VSS120 CFG16 CFG[15] RSVD_TP_59
E18 VSS199 AL17 VSS41 VSS121 V10 AJ30 CFG[16] RSVD_TP_60 F15
E13 AL12 U8 CFG17 AK30 A2
VSS200 VSS42 VSS122 CFG18 CFG[17] KEY @
E11 VSS201 AL9 VSS43 VSS123 U4 H16 RSVD_TP_86 RSVD62 D15
E8 AL6 U2 C15 0_0402_5%
VSS202 VSS44 VSS124 RSVD63
E5 VSS203 AL3 VSS45 VSS125 T35 Reserve via for test RSVD64 AJ15 1 R116 2
E2 AT35 H_NCTF1 PAD T4 AK29 T34 AH15 1 2
VSS204 VSS_NCTF1 H_NCTF2 VSS46 VSS126 RSVD65 R115
D33 VSS205 VSS_NCTF2 AT1 PAD T5 AK27 VSS47 VSS127 T33
D30 AR34 AK25 T32 B19 0_0402_5%
VSS206 VSS_NCTF3 VSS48 VSS128 @ RSVD15 @
D26 VSS207 VSS_NCTF4 B34 AK20 VSS49 VSS129 T31 A19 RSVD16
D9 B2 AK17 T30 0_0402_5%
NCTF

VSS208 VSS_NCTF5 H_NCTF6 VSS50 VSS130

D6 VSS209 VSS_NCTF6 B1 PAD T6 AJ31 VSS51 VSS131 T29 1 R114 2 A20 RSVD17
D3 A35 H_NCTF7 PAD T7 AJ23 T28 1 2 B20
VSS210 VSS_NCTF7 VSS52 VSS132 R111 RSVD18
C34 VSS211 AJ20 VSS53 VSS133 T27 RSVD_TP_66 AA5
C32 AJ17 T26 0_0402_5% U9 AA4
VSS212 VSS54 VSS134 @ RSVD19 RSVD_TP_67
C29 VSS213 AJ14 VSS55 VSS135 T6 T9 RSVD20 RSVD_TP_68 R8
C28 VSS214 AJ11 VSS56 VSS136 R10 RSVD_TP_69 AD3
C24 VSS215 AJ8 VSS57 VSS137 P8 AC9 RSVD21 RSVD_TP_70 AD2
C22 VSS216 AJ5 VSS58 VSS138 P4 AB9 RSVD22 RSVD_TP_71 AA2
C20 VSS217 AJ2 VSS59 VSS139 P2 CFG0 - PCI-Express Configuration Select RSVD_TP_72 AA1
C19 VSS218 AH35 VSS60 VSS140 N35 RSVD_TP_73 R9
C16 VSS219 AH34 VSS61 VSS141 N34 RSVD_TP_74 AG7
B31 VSS220 AH33 VSS62 VSS142 N33 *1:Single PEG C1 RSVD_NCTF_23 RSVD_TP_75 AE3
B25 VSS221 AH32 VSS63 VSS143 N32 0:Bifurcation enabled A3 RSVD_NCTF_24
B B
B21 VSS222 AH31 VSS64 VSS144 N31
B18 VSS223 AH30 VSS65 VSS145 N30 RSVD_TP_76 V4
B17 VSS224 AH29 VSS66 VSS146 N29 RSVD_TP_77 V5
B13 VSS225 AH28 VSS67 VSS147 N28 RSVD_TP_78 N2
B11 VSS226 AH27 VSS68 VSS148 N27 CFG3 - PCI-Express Static Lane Reversal J29 RSVD26 RSVD_TP_79 AD5
B8 VSS227 AH26 VSS69 VSS149 N26 J28 RSVD27 RSVD_TP_80 AD7
B6 VSS228 AH20 VSS70 VSS150 N6 RSVD_TP_81 W3
B4 VSS229 AH17 VSS71 VSS151 M10 *1 :Normal Operation A34 RSVD_NCTF_28 RSVD_TP_82 W2
A29 VSS230 AH13 VSS72 VSS152 L35 0 :Lane Numbers Reversed A33 RSVD_NCTF_29 RSVD_TP_83 N3
A27 VSS231 AH9 VSS73 VSS153 L32 15 -> 0, 14 -> 1, ... RSVD_TP_84 AE5
A23 VSS232 AH6 VSS74 VSS154 L29 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
A9 VSS233 AH3 VSS75 VSS155 L8 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34
AF4 VSS78 VSS158 K34 CFG4 - Display Port Presence
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30
*1:Disabled; No Physical Display Port
attached to Embedded Display Port IC,AUB_CFD_rPGA,R0P9
0:Enabled; An external Display Port @

IC,AUB_CFD_rPGA,R0P9 IC,AUB_CFD_rPGA,R0P9 device is connected to the Embedded

@ @ Display Port

*:Default

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 10 of 58
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

1
JDDRL
2
DDR3 SO-DIMM A
+VREF_DQA
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
Standard Type 7 DDR_A_DQS[0..7]

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
5 DQ0 DQ5 6 7 DDR_A_DQS#[0..7]
1 1 DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 7 DDR_A_D[0..63]
+1.5V
C156

C157
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS VSS 14 7 DDR_A_DM[0..7]
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16

1
DDR_A_D3 17 18 DDR_A_D7 7 DDR_A_MA[0..15]
DQ3 DQ7 R80 @
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1%
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D 23 DQ9 DQ13 24 D
25 26

2
DDR_A_DQS#1 VSS VSS DDR_A_DM1
close to JDDRL.1 27 DQS1# DM1 28
DDR_A_DQS1 29 30
DQS1 RESET# SM_DRAMRST# 5,12
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48
DDR_A_D22 +1.5V
49 VSS DQ22 50
DDR_A_D18 DDR_A_D23 +1.5V
51 DQ18 DQ23 52
DDR_A_D19 53 54 2 M3@ 1
DQ19 VSS

1
55 56 DDR_A_D28 R94 0_0402_5%
VSS DQ28

1
DDR_A_D24 57 58 DDR_A_D29 R82 @
DDR_A_D25 DQ24 DQ29 1K_0402_1% +V_DDR3_DIMM_REF R79
59 DQ25 VSS 60
61 62 DDR_A_DQS#3 Q40 @ +VREF_DQA 1K_0402_1%
DDR_A_DM3 VSS DQS3# DDR_A_DQS3 2N7002_SOT23-3
63 64

2
DM3 DQS3
65 66

2
VSS VSS

D
DDR_A_D26 67 68 DDR_A_D30 +VREF_DQA_M3 3 1 2 M1@ 1
DDR_A_D27 DQ26 DQ30 DDR_A_D31 0_0402_5% R92
69 DQ27 DQ31 70

1
71 VSS VSS 72
M3@ R83 @ R81

G
2
R122 RST_GATE 1K_0402_1% 1K_0402_1%
100K_0402_5% +1.5V
7 DDRA_CKE0 73 CKE0 CKE1 74 DDRA_CKE1 7
75 76 2 M3@ 1

2
C
VDD VDD DDR_A_MA15 R95 0_0402_5% C
77 NC A15 78

1
79 80 DDR_A_MA14
7 DDR_A_BS2 BA2 A14
81 82 @ R84
DDR_A_MA12 VDD VDD DDR_A_MA11 Q39 @ 1K_0402_1% +VREF_DQB
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7 2N7002_SOT23-3
A9 A7
87 88

2
VDD VDD

D
DDR_A_MA8 89 90 DDR_A_MA6 +VREF_DQB_M3 3 1 2 M1@ 1
DDR_A_MA5 A8 A6 DDR_A_MA4 0_0402_5% R93
91 A5 A4 92

1
93 VDD VDD 94
DDR_A_MA3 DDR_A_MA2 M3@ R126 @

G
95 96

2
DDR_A_MA1 A3 A2 DDR_A_MA0 R121 1K_0402_1%
97 A1 A0 98
99 100 100K_0402_5%
VDD VDD RST_GATE 5,30
101 102 DDRA_CLK1 7

2
7 DDRA_CLK0 CK0 CK1
7 DDRA_CLK0# 103 CK0# CK1# 104 DDRA_CLK1# 7
105 VDD VDD 106
DDR_A_MA10 107 108
A10/AP BA1 DDR_A_BS1 7
7 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 7
111 VDD VDD 112
7 DDR_A_WE# 113 WE# S0# 114 DDRA_SCS0# 7
7 DDR_A_CAS# 115 CAS# ODT0 116 DDRA_ODT0 7
117 VDD VDD 118
DDR_A_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRA_ODT1 7
7 DDRA_SCS1# 121 S1# NC 122
123 124 R89
VDD VDD +DDR_VREF_CA_DIMMA
125 TEST VREF_CA 126 1 2
127 128 0_0402_5%
DDR_A_D32 VSS VSS DDR_A_D36
129 DQ32 DQ36 130
DDR_A_D33 DDR_A_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

131 DQ33 DQ37 132

133 VSS VSS 134
B DDR_A_DQS#4 DDR_A_DM4 B
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DQS4 VSS DDR_A_D38
139 VSS DQ38 140
Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
C161

C162

DDR_A_D34 141 142 DDR_A_D39

DDR_A_D35 DQ34 DQ39
143 DQ35 VSS 144
DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45 +1.5V
DDR_A_D41 DQ40 DQ45 @ +1.5V +0.75VS
149 DQ41 VSS 150
DDR_A_DQS#5 C163 1 2 330U_B2_2.5VM_R15M

+
151 VSS DQS5# 152
DDR_A_DM5 153 154 DDR_A_DQS5 close to JDDRL.126
DM5 DQS5 C164 1
155 VSS VSS 156 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M
DDR_A_D42 157 158 DDR_A_D46 C166 1 2 10U_0805_6.3V6M
DDR_A_D43 DQ42 DQ46 DDR_A_D47 C167 1
159 DQ43 DQ47 160 2 0.1U_0402_16V4Z
161 162 Reserve for cost down C168 1 2 10U_0805_6.3V6M C169 2 1 1U_0402_6.3V4Z
DDR_A_D48 VSS VSS DDR_A_D52 C170 1
163 DQ48 DQ52 164 2 0.1U_0402_16V4Z
DDR_A_D49 165 166 DDR_A_D53 C171 1 2 10U_0805_6.3V6M C172 2 1 1U_0402_6.3V4Z
DQ49 DQ53 +1.5V C173 1
167 VSS VSS 168 2 0.1U_0402_16V4Z
DDR_A_DQS#6 169 170 DDR_A_DM6 C174 1 2 10U_0805_6.3V6M C175 2 1 1U_0402_6.3V4Z
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54 1 C176 1 2 10U_0805_6.3V6M C177 2 1 1U_0402_6.3V4Z
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178 C217 + C178 1 2 10U_0805_6.3V6M
DQ51 VSS DDR_A_D60 390U_2.5V_M_R10
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61 2
183 DQ57 VSS 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS DQS7# DDR_A_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62
A DQ58 DQ62 A
DDR_A_D59 193 194 DDR_A_D63
R90 1 DQ59 DQ63
2 195 VSS VSS 196
10K_0402_5% 197 198
SA0 EVENT# PM_EXTTS# 5,12
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 12,22,26,36
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

201 SA1 SCL 202 PM_SMBCLK 12,22,26,36

10K_0402_5%

203 204
1 1 +0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
1

C182
C181 205 206 2009/01/23 2010/01/23 Title
GND1 BOSS1 Issued Date Deciphered Date
R91

207 208
2 2 GND2 BOSS2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

FOX_AS0A626-U2SN-7F_204P Custom D
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 11 of 58
5 4 3 2 1
 A B C D E

+1.5V +1.5V

1
JDDRH
2
Standard Type
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_B_D4
DDR_B_D5
DDR3 SO-DIMM B
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8 7 DDR_B_DQS#[0..7]
DDR_B_DQS#0

0.1U_0402_16V4Z
2.2U_0603_6.3V4Z 9 10
DDR_B_DM0 VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12 7 DDR_B_DQS[0..7]
1 1 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6 7 DDR_B_D[0..63]
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
C183

C184
19 VSS VSS 20 7 DDR_B_DM[0..7]
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
1 DDR_B_D9 23 24 DDR_B_D13 7 DDR_B_MA[0..15] 1
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1
29 DQS1 RESET# 30 SM_DRAMRST# 5,11
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
close to JDDRH.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

7 DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 7

75 VDD VDD 76
2 77 78 DDR_B_MA15 2
NC A15 DDR_B_MA14
7 DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
7 DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 7
7 DDRB_CLK0# 103 CK0# CK1# 104 DDRB_CLK1# 7
105 VDD VDD 106
DDR_B_MA10 107 108
A10/AP BA1 DDR_B_BS1 7
7 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 7
111 VDD VDD 112
7 DDR_B_WE# 113 WE# S0# 114 DDRB_SCS0# 7
7 DDR_B_CAS# 115 CAS# ODT0 116 DDRB_ODT0 7
117 VDD VDD 118
DDR_B_MA13 119 120
A13 ODT1 DDRB_ODT1 7 +V_DDR3_DIMM_REF
7 DDRB_SCS1# 121 S1# NC 122
123 124 R97
VDD VDD +DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2 0_0402_5% Layout Note: Layout Note: Place these 4 Caps near Layout Note:
127 VSS VSS 128
DDR_B_D32 129 130 DDR_B_D36 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
DDR_B_D33 DQ32 DQ36 DDR_B_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

131 DQ33 DQ37 132

133 VSS VSS 134
3 DDR_B_DQS#4 135 136 DDR_B_DM4 +1.5V 3
DQS4# DM4 1 1
DDR_B_DQS4 137 138 @ +1.5V +0.75VS
DQS4 VSS DDR_B_D38 C189 1 2 330U_B2_2.5VM_R15M

+
139 VSS DQ38 140
C187

C188

DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2 C190 1
143 DQ35 VSS 144 2 0.1U_0402_16V4Z C191 1 2 10U_0805_6.3V6M
145 146 DDR_B_D44 C192 1 2 10U_0805_6.3V6M
DDR_B_D40 VSS DQ44 DDR_B_D45 C193 1
147 DQ40 DQ45 148 2 0.1U_0402_16V4Z
DDR_B_D41 149 150 C194 1 2 10U_0805_6.3V6M C195 2 1 1U_0402_6.3V4Z
DQ41 VSS DDR_B_DQS#5 C196 1
151 VSS DQS5# 152 2 0.1U_0402_16V4Z
DDR_B_DM5 153 154 DDR_B_DQS5 C197 1 2 10U_0805_6.3V6M C198 2 1 1U_0402_6.3V4Z
DM5 DQS5 C199 1
155 VSS VSS 156 close to JDDRH.126 2 0.1U_0402_16V4Z
DDR_B_D42 157 158 DDR_B_D46 C200 1 2 10U_0805_6.3V6M C201 2 1 1U_0402_6.3V4Z
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 162 C202 1 2 10U_0805_6.3V6M C203 2 1 1U_0402_6.3V4Z
DDR_B_D48 VSS VSS DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53 C204 1 2 10U_0805_6.3V6M
DQ49 DQ53
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS DDR_B_D60
179 VSS DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
4 DQ58 DQ62 4
DDR_B_D59 193 194 DDR_B_D63
R98 1 DQ59 DQ63
2 195 VSS VSS 196
10K_0402_5% 197 198
SA0 EVENT# PM_EXTTS# 5,11
+3VS 199 VDDSPD SDA 200 PM_SMBDATA 11,22,26,36
201 SA1 SCL 202 PM_SMBCLK 11,22,26,36
2.2U_0603_6.3V4Z 1 R99 2 203 204
1 1
10K_0402_5%
+0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
205 GND1 BOSS1 206 Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
C207 C208 207 208
2 2 GND2 BOSS2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
0.1U_0402_16V4Z AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
FOX_AS0A626-UASN-7F_204P Custom D
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 12 of 58
A B C D E
 5 4 3 2 1

PCIE_GTX_C_CRX_P[0..15]
6 PCIE_GTX_C_CRX_P[0..15]

PCIE_GTX_C_CRX_N[0..15] UV1A
6 PCIE_GTX_C_CRX_N[0..15]
LANE Reversal LANE Reversal
PCIE_CTX_C_GRX_P[0..15]
6 PCIE_CTX_C_GRX_P[0..15]
D D
PCIE_CTX_C_GRX_N[0..15]
6 PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P15 AA38 Y33 PCIE_GTX_CRX_P15 C38 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P15
PCIE_CTX_C_GRX_N15 PCIE_RX0P PCIE_TX0P PCIE_GTX_CRX_N15 C22 0.1U_0402_16V7K PCIE_GTX_C_CRX_N15
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2

PCIE_CTX_C_GRX_P14 Y35 W33 PCIE_GTX_CRX_P14 C37 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P14

PCIE_CTX_C_GRX_N14 PCIE_RX1P PCIE_TX1P PCIE_GTX_CRX_N14 C21 0.1U_0402_16V7K PCIE_GTX_C_CRX_N14
W36 PCIE_RX1N PCIE_TX1N W32 1 2

PCIE_CTX_C_GRX_P13 W38 U33 PCIE_GTX_CRX_P13 C36 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P13

PCIE_CTX_C_GRX_N13 PCIE_RX2P PCIE_TX2P PCIE_GTX_CRX_N13 C20 0.1U_0402_16V7K PCIE_GTX_C_CRX_N13
V37 PCIE_RX2N PCIE_TX2N U32 1 2

PCIE_CTX_C_GRX_P12 V35 U30 PCIE_GTX_CRX_P12 C35 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P12

PCIE_CTX_C_GRX_N12 PCIE_RX3P PCIE_TX3P PCIE_GTX_CRX_N12 C19 0.1U_0402_16V7K PCIE_GTX_C_CRX_N12
U36 PCIE_RX3N PCIE_TX3N U29 1 2

PCIE_CTX_C_GRX_P11 U38 T33 PCIE_GTX_CRX_P11 C34 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P11

PCIE_CTX_C_GRX_N11 PCIE_RX4P PCIE_TX4P PCIE_GTX_CRX_N11 C18 0.1U_0402_16V7K PCIE_GTX_C_CRX_N11
T37 PCIE_RX4N PCIE_TX4N T32 1 2

PCI EXPRESS INTERFACE

PCIE_CTX_C_GRX_P10 T35 T30 PCIE_GTX_CRX_P10 C33 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P10
PCIE_CTX_C_GRX_N10 PCIE_RX5P PCIE_TX5P PCIE_GTX_CRX_N10 C17 0.1U_0402_16V7K PCIE_GTX_C_CRX_N10
R36 PCIE_RX5N PCIE_TX5N T29 1 2

PCIE_CTX_C_GRX_P9 R38 P33 PCIE_GTX_CRX_P9 C32 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P9

PCIE_CTX_C_GRX_N9 PCIE_RX6P PCIE_TX6P PCIE_GTX_CRX_N9 C16 0.1U_0402_16V7K PCIE_GTX_C_CRX_N9
P37 PCIE_RX6N PCIE_TX6N P32 1 2
C C
PCIE_CTX_C_GRX_P8 P35 P30 PCIE_GTX_CRX_P8 C31 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P8
PCIE_CTX_C_GRX_N8 PCIE_RX7P PCIE_TX7P PCIE_GTX_CRX_N8 C15 0.1U_0402_16V7K PCIE_GTX_C_CRX_N8
N36 PCIE_RX7N PCIE_TX7N P29 1 2

PCIE_CTX_C_GRX_P7 N38 N33 PCIE_GTX_CRX_P7 C30 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P7

PCIE_CTX_C_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_GTX_CRX_N7 C14 0.1U_0402_16V7K PCIE_GTX_C_CRX_N7
M37 PCIE_RX8N PCIE_TX8N N32 1 2

PCIE_CTX_C_GRX_P6 M35 N30 PCIE_GTX_CRX_P6 C29 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P6

PCIE_CTX_C_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_GTX_CRX_N6 C13 0.1U_0402_16V7K PCIE_GTX_C_CRX_N6
L36 PCIE_RX9N PCIE_TX9N N29 1 2

PCIE_CTX_C_GRX_P5 L38 L33 PCIE_GTX_CRX_P5 C28 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P5

PCIE_CTX_C_GRX_N5 PCIE_RX10P PCIE_TX10P PCIE_GTX_CRX_N5 C12 0.1U_0402_16V7K PCIE_GTX_C_CRX_N5
K37 PCIE_RX10N PCIE_TX10N L32 1 2

PCIE_CTX_C_GRX_P4 K35 L30 PCIE_GTX_CRX_P4 C27 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P4

PCIE_CTX_C_GRX_N4 PCIE_RX11P PCIE_TX11P PCIE_GTX_CRX_N4 C11 0.1U_0402_16V7K PCIE_GTX_C_CRX_N4
J36 PCIE_RX11N PCIE_TX11N L29 1 2

PCIE_CTX_C_GRX_P3 J38 K33 PCIE_GTX_CRX_P3 C26 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P3

PCIE_CTX_C_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_GTX_CRX_N3 C10 0.1U_0402_16V7K PCIE_GTX_C_CRX_N3
H37 PCIE_RX12N PCIE_TX12N K32 1 2

PCIE_CTX_C_GRX_P2 H35 J33 PCIE_GTX_CRX_P2 C25 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P2

PCIE_CTX_C_GRX_N2 PCIE_RX13P PCIE_TX13P PCIE_GTX_CRX_N2 C9 0.1U_0402_16V7K PCIE_GTX_C_CRX_N2
G36 PCIE_RX13N PCIE_TX13N J32 1 2

B PCIE_CTX_C_GRX_P1 PCIE_GTX_CRX_P1 C24 0.1U_0402_16V7K PCIE_GTX_C_CRX_P1 B

G38 PCIE_RX14P PCIE_TX14P K30 1 2
PCIE_CTX_C_GRX_N1 F37 K29 PCIE_GTX_CRX_N1 C8 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_N1
PCIE_RX14N PCIE_TX14N

PCIE_CTX_C_GRX_P0 F35 H33 PCIE_GTX_CRX_P0 C23 1 2 0.1U_0402_16V7K PCIE_GTX_C_CRX_P0

PCIE_CTX_C_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_GTX_CRX_N0 C7 0.1U_0402_16V7K PCIE_GTX_C_CRX_N0
E37 PCIE_RX15N PCIE_TX15N H32 1 2

CLOCK
26 CLK_PCIE_VGA AB35 PCIE_REFCLKP
26 CLK_PCIE_VGA# AA36 PCIE_REFCLKN

CALIBRATION
Reserve for Park and Madison support. AJ21 Y30 1 2
NC#1 PCIE_CALRP RV1 1.27K_0402_1%
AK21 NC#2
2 @ 1 AH16 Y29 1 2 +1.1VS
RV54 10K_0402_5% NC_PWRGOOD PCIE_CALRN RV2 2K_0402_1%

5,29,36,37,41,42 PLT_RST# AA30 PERSTB

M96PRO@
216-0729002 A12 M96_BGA962

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 13 of 58
5 4 3 2 1
 5 4 3 2 1
UV1B
UV1G

1 @ 2
AU24 RV39 10K_0402_5%
TXCAP_DPA3P LVDS CONTROL
TXCAM_DPA3N AV23 VARY_BL AK27 VGA_PWM 22
DIGON AJ27 VGA_ENVDD 22
TX0P_DPA2P AT25
MUTI GFX AR24
DPA TX0M_DPA2N

TX1P_DPA1P AU26
TX1M_DPA1N AV25 TXCLK_UP_DPF3P AK35 VGA_TZCLK+ 22
TXCLK_UN_DPF3N AL36 VGA_TZCLK- 22
AR8 DVPCNTL_MVP_0 TX2P_DPA0P AT27
AU8 DVPCNTL_MVP_1 TX2M_DPA0N AR26 TXOUT_U0P_DPF2P AJ38 VGA_TZOUT0+ 22
AP8 DVPCNTL_0 TXOUT_U0N_DPF2N AK37 VGA_TZOUT0- 22
AW8 DVPCNTL_1 TXCBP_DPB3P AR30 VGA_HDMI_CLK+ 24
AR3 DVPCNTL_2 TXCBM_DPB3N AT29 VGA_HDMI_CLK- 24 TXOUT_U1P_DPF1P AH35 VGA_TZOUT1+ 22
D
AR1 DVPCLK TXOUT_U1N_DPF1N AJ36 VGA_TZOUT1- 22 D
21 VRAM_DEC AU1 DVPDATA_0 TX3P_DPB2P AV31 VGA_HDMI_TX0+ 24
21 VRAM_ID0 AU3 DVPDATA_1 TX3M_DPB2N AU30 VGA_HDMI_TX0- 24 TXOUT_U2P_DPF0P AG38 VGA_TZOUT2+ 22
AW3 DPB AH37 VGA_TZOUT2- 22
21 VRAM_ID1 DVPDATA_2 TXOUT_U2N_DPF0N
21 VRAM_ID2 AP6 DVPDATA_3 TX4P_DPB1P AR32 VGA_HDMI_TX1+ 24
AW5 DVPDATA_4 TX4M_DPB1N AT31 VGA_HDMI_TX1- 24 TXOUT_U3P AF35
AU5 DVPDATA_5 TXOUT_U3N AG36
AR6 DVPDATA_6 TX5P_DPB0P AT33 VGA_HDMI_TX2+ 24
AW6 DVPDATA_7 TX5M_DPB0N AU32 VGA_HDMI_TX2- 24
AU6 LVTMDP
DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14
AV7 DVPDATA_10 TXCCM_DPC3N AV13 TXCLK_LP_DPE3P AP34 VGA_TXCLK+ 22
AN7 DVPDATA_11 TXCLK_LN_DPE3N AR34 VGA_TXCLK- 22
AV9 DVPDATA_12 TX0P_DPC2P AT15
AT9 DVPDATA_13 TX0M_DPC2N AR14 TXOUT_L0P_DPE2P AW37 VGA_TXOUT0+ 22
AR10 DVPDATA_14 TXOUT_L0N_DPE2N AU35 VGA_TXOUT0- 22
AW10 DPC AU16
DVPDATA_15 TX1P_DPC1P
AU10 DVPDATA_16 TX1M_DPC1N AV15 TXOUT_L1P_DPE1P AR37 VGA_TXOUT1+ 22
AP10 DVPDATA_17 TXOUT_L1N_DPE1N AU39 VGA_TXOUT1- 22
AV11 DVPDATA_18 TX2P_DPC0P AT17
AT11 DVPDATA_19 TX2M_DPC0N AR16 TXOUT_L2P_DPE0P AP35 VGA_TXOUT2+ 22
AR12 DVPDATA_20 TXOUT_L2N_DPE0N AR35 VGA_TXOUT2- 22
AW12 DVPDATA_21 TXCDP_DPD3P AU20
AU12 DVPDATA_22 TXCDM_DPD3N AT19 TXOUT_L3P AN36
AP12 DVPDATA_23 TXOUT_L3N AP37
TX3P_DPD2P AT21
AR20
Single channel
TX3M_DPD2N
DPD AU22
TX4P_DPD1P 216-0729002 A12 M96_BGA962
TX4M_DPD1N AV21
M96PRO@
+VGA_CORE I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22
VGA_EDID_CLK
LVDS 22 VGA_EDID_CLK AK26 SCL
1

@ 22 VGA_EDID_DATA VGA_EDID_DATA AJ26

RV16 SDA VGA_CRT_R 1 2
10K_0402_5% AD39 RV12 150_0402_1%
GENERAL PURPOSE I/O R VGA_CRT_R 23
AD37 VGA_CRT_G 1 2
GPU_GPIO0 RB RV13 150_0402_1%
C
21 GPU_GPIO0 AH20 C
2

BB_EN GPU_GPIO1 GPIO_0 VGA_CRT_B

21 GPU_GPIO1 AH18 GPIO_1 G AE36 VGA_CRT_G 23 1 2
GPU_GPIO2 AN16 AD35 RV14 150_0402_1%
21 GPU_GPIO2 GPIO_2 GB
AH23 GPIO_3_SMBDATA
AJ23 GPIO_4_SMBCLK B AF37 VGA_CRT_B 23
T49 AH17 GPIO_5_AC_BATT BB AE38
RV18 1 2 10K_0402_5% AJ17 DAC1
GPIO_6
41 VGA_ENBKL AK17
AJ13
GPIO_7_BLON HSYNC AC36
AC38
VGA_CRT_HSYNC 21,23 CRT
21 SOUT_GPIO8 GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC 21,23
21 SIN_GPIO9 AH15 GPIO_9_ROMSI
AJ16 GPIO_10_ROMSCK
GPU_GPIO11 AK16 AB34 1 2
21 GPU_GPIO11 GPIO_11 RSET
GPU_GPIO12 AL16 RV19 499_0402_1%
21 GPU_GPIO12 GPIO_12
GPU_GPIO13 AM16 AD34 +A1VDD
21 GPU_GPIO13 GPIO_13 AVDD
24,30 VGA_HDMI_HPD AM14 GPIO_14_HPD2 AVSSQ AE34
VGA_PWRSEL AM13
54 VGA_PWRSEL GPIO_15_PWRCNTL_0
27M_SSC AK14 AC33 +VDD1DI
22 27M_SSC GPIO_16_SSIN VDD1DI
THERM#_VGA AG30 AC34
21 THERM#_VGA GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3
@ 1 RV20 2 10K_0402_5% GPU_CTF AM17
GPIO_19_CTF
T53 AL13 GPIO_20_PWRCNTL_1 R2 AC30
BB_EN AJ14 AC31
GPIO_21_BB_EN R2B
21 ROMSE_GPIO22 AK13 GPIO_22_ROMCSB
GPIO23_CLKREQ# AN13 AD30
GPIO24_TRST# GPIO_23_CLKREQB G2
T47 AM23 JTAG_TRSTB G2B AD31
T30 AN23 JTAG_TDI
T31 AK23 JTAG_TCK B2 AF30
AL24 AF31 BLM18PG121SN1D_0603
T32
AM24
JTAG_TMS B2B +A1VDD 70mA 2 1 +1.8VS
T33 JTAG_TDO
AJ19 1 1 1 LV3
T34 GENERICA
T35 AK19 GENERICB C AC32
BLM18PG121SN1D_0603 AJ20 AD32 CV7 CV8 CV9
150mA T48
AK20
GENERICC Y
AF32 1U_0402_6.3V4Z 10U_0603_6.3V6M
0.1U_0402_16V4Z +DPLL_PVDD GENERICD COMP 2 2 2
+1.8VS 2 1 AJ24 GENERICE_HPD4
LV1 1 1 1 AH26 DAC2 0.1U_0402_16V4Z
CV3 GENERICF
AH24 GENERICG H2SYNC AD29 HSYNC_DAC2 21
CV2 1U_0402_6.3V4Z AC29
V2SYNC VSYNC_DAC2 21
CV1
B 2 2 2 +1.8VS BLM18PG121SN1D_0603 B
T36 AK24 HPD1 45mA
10U_0603_6.3V6M AG31 +VDD1DI +VDD1DI 2 1 +1.8VS
VDD2DI
1

RV21 AG32 1 1 1 LV4

499_0402_1% VSS2DI
CV10 CV11 CV12
AG33 1U_0402_6.3V4Z 10U_0603_6.3V6M
BLM18PG121SN1D_0603 300mA A2VDD +3VS_DELAY 2 2 2
2

+1.1VS 2 1 0.1U_0402_16V4Z +DPLL_VDDC AD33 +1.8VS 0.1U_0402_16V4Z

LV2 +VGA_VREF A2VDDQ
1 1 1 AH13 VREFG
CV4 AF33
A2VSSQ
1

CV5 CV6 1
RV22 CV13
2 2 2 1U_0402_6.3V4Z 249_0402_1%
R2SET AA29 1 2
10U_0603_6.3V6M 0.1U_0402_16V4Z RV23 715_0402_1%
2
2

DDC/AUX AM26
PLL/CLOCK DDC1CLK
DDC1DATA AN26
+DPLL_PVDD AM32 DPLL_PVDD
AN32 DPLL_PVSS AUX1P AM27
AUX1N AL27

+DPLL_VDDC +3VS_DELAY
AN31 DPLL_VDDC DDC2CLK AM19
AL19
VGA_HDMI_CLK 24
VGA_HDMI_DATA 24
HDMI
47.5_0402_1% DDC2DATA
2 1 XTALIN AV33 AN20
22 27M_CLK XTALIN AUX2P
RV26 AU34 AM20 VGA_EDID_DATA 1 2
XTALOUT AUX2N
1

RV27 4.7K_0402_5%
RV28 AL30 +3VS_DELAY VGA_EDID_CLK 1 2
100_0402_1% DDCCLK_AUX3P RV29 4.7K_0402_5%
DDCDATA_AUX3N AM30
CV99 @ 100P_0402_50V8J VGA_PWRSEL 1 2
1 2 2 1 XTALIN AL29 VGA_CRT_DATA 1 2 RV30 @ 10K_0402_5%
2

RV52 @ 100_0402_5% DDCCLK_AUX4P RV31 4.7K_0402_5%

21 GPU_THERMAL_D+ AF29 DPLUS DDCDATA_AUX4N AM29
AG29 THERMAL VGA_CRT_CLK 1 2
21 GPU_THERMAL_D- DMINUS
AN21 RV32 4.7K_0402_5% THERM#_VGA 1 2
DDCCLK_AUX5P RV33 10K_0402_5%
DDCDATA_AUX5N AM21
BLM18PG121SN1D_0603 AK32 GPIO23_CLKREQ# 1 2
A +1.8VS 2 1 0.1U_0402_16V4Z 20mA +TSVDD AJ32
TS_FDO
AJ30 VGA_CRT_CLK 23 VGA_HDMI_DATA 1 2 RV34 10K_0402_5% A
LV7 TSVDD DDC6CLK RV35 4.7K_0402_5%
1 1 1 AJ33 TSVSS DDC6DATA AJ31 VGA_CRT_DATA 23 CRT
CV22 VGA_HDMI_CLK 1 2
CV21 1U_0402_6.3V4Z AK30 RV37 4.7K_0402_5%
CV20 NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N AK29
2 2 2
10U_0603_6.3V6M

216-0729002 A12 M96_BGA962 M96PRO@

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 14 of 58
5 4 3 2 1
 5 4 3 2 1

Reserve for Park and Madison support.

20mA
UV1H

DP C/D POWER DP A/B POWER

+1.8VS 1 @ 2 AP20 AN24 1 @ 2 +1.8VS

RV137 0_0603_5% NC_DPC_VDD18#1 NC_DPA_VDD18#1 RV139 0_0603_5%
AP21 NC_DPC_VDD18#2 NC_DPA_VDD18#2 AP24
BLM18PG121SN1D_0603
D
+DPB_VDD18 20mA 2 1 +1.8VS
D

+1.1VS AP13 AP31 +1.1VS 2 2 2 LV31 @

DPC_VDD10#1 DPA_VDD10#1 @ @ @
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
10U_0603_6.3V6M CV253 CV236 CV270
0.1U_0402_16V4Z
1 1 1
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27
AP16 AP27 1U_0402_6.3V4Z
DPC_VSSR#2 DPA_VSSR#2
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26

+1.8VS 1 @ 2 AP22 AP25 +DPB_VDD18

RV138 0_0603_5% NC_DPD_VDD18#1 NC_DPB_VDD18#1
AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26

+1.1VS AP14 AN33 +DPB_VDD10 20mABLM18PG121SN1D_0603

2 1 +1.1VS
DPD_VDD10#1 DPB_VDD10#1 LV11
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33 2 2 2
CV28 CV27 CV26
0.1U_0402_16V4Z 10U_0603_6.3V6M
1 1 1
AN19 DPD_VSSR#1 DPB_VSSR#1 AN29
AP18 AP29 1U_0402_6.3V4Z
DPD_VSSR#2 DPB_VSSR#2
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
C C

RV40 150_0402_1%
200mA 2 1 AW18 AW28 1 2
BLM18PG121SN1D_0603 DPCD_CALR DPAB_CALR RV41 150_0402_1%
+1.8VS 2 1 +DPE_VDD18
LV12 2 2 2 DP E/F POWER DP PLL POWER
+DPE_VDD18 AH34 AU28 +DPA_PVDD BLM18PG121SN1D_0603
10U_0603_6.3V6M CV29 CV30 CV31 AJ34
DPE_VDD18#1 DPA_PVDD
AV27 +DPA_PVDD 20mA 2 1 +1.8VS
0.1U_0402_16V4Z DPE_VDD18#2 DPA_PVSS LV13
1 1 1 2 2 2
1U_0402_6.3V4Z 10U_0603_6.3V6M CV32 CV33 CV34
+DPE_VDD10 AL33 AV29 +DPB_PVDD 0.1U_0402_16V4Z
DPE_VDD10#1 DPB_PVDD 1 1 1
AM33 DPE_VDD10#2 DPB_PVSS AR28
1U_0402_6.3V4Z

AN34 AU18 +DPC_PVDD

BLM18PG121SN1D_0603 100mA AP39
DPE_VSSR#1 DPC_PVDD
AV17
+DPE_VDD10 DPE_VSSR#2 DPC_PVSS
+1.1VS 2 1 AR39 DPE_VSSR#3
LV15 AU37 BLM18PG121SN1D_0603
2 2 2
AW35
DPE_VSSR#4 +DPB_PVDD 20mA 2 1 +1.8VS
10U_0603_6.3V6M CV35 CV36 CV38 DPE_VSSR#5 +DPD_PVDD LV14
DPD_PVDD AV19 2 2 2
0.1U_0402_16V4Z AR18
1 1 1 DPD_PVSS 10U_0603_6.3V6M CV37 CV39 CV40
1U_0402_6.3V4Z +DPF_VDD18 AF34 0.1U_0402_16V4Z
DPF_VDD18#1 1 1 1
AG34 DPF_VDD18#2
AM37 +DPE_PVDD 1U_0402_6.3V4Z
DPE_PVDD
DPE_PVSS AN38
B B
200mA +DPF_VDD10 AK33
BLM18PG121SN1D_0603 DPF_VDD10#1 BLM18PG121SN1D_0603
AK34 DPF_VDD10#2 20mA
+1.8VS 2 1 +DPF_VDD18 AL38 +DPC_PVDD 2 1 +1.8VS
LV17 NC_DPF_PVDD LV16
2 2 2 NC_DPF_PVSS AM35 2 2 2
10U_0603_6.3V6M CV44 CV45 CV46 AF39 10U_0603_6.3V6M CV41 CV42 CV43
0.1U_0402_16V4Z DPF_VSSR#1 0.1U_0402_16V4Z
AH39 DPF_VSSR#2
1 1 1 1 1 1
AK39 DPF_VSSR#3
1U_0402_6.3V4Z AL34 1U_0402_6.3V4Z
DPF_VSSR#4
AM34 DPF_VSSR#5

BLM18PG121SN1D_0603
2 1 AM39 +DPD_PVDD 20mA 2 1
BLM18PG121SN1D_0603 100mA RV42 150_0402_1% DPEF_CALR
1 2 1 LV18
+1.8VS

+1.1VS 2 1 +DPF_VDD10
LV19 2 2 2 216-0729002 A12 M96_BGA962 1U_0402_6.3V4Z CV47 CV48 CV49
10U_0603_6.3V6M
10U_0603_6.3V6M CV50 CV51 CV52 2 1 2
M96PRO@
0.1U_0402_16V4Z
1 1 1 0.1U_0402_16V4Z
1U_0402_6.3V4Z

BLM18PG121SN1D_0603
+DPE_PVDD 20mA 2 1 +1.8VS
1 1 1 LV20

0.1U_0402_16V4Z CV53 CV54 CV55

A A
10U_0603_6.3V6M
2 2 2
1U_0402_6.3V4Z

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 15 of 58
5 4 3 2 1
 5 4 3 2 1

UV1E

+VRAM_1.5VS MEM I/O

PCIE 500mA
4A AC7 AA31 +PCIE_VDDR 1 2 +1.8VS
VDDR1#1 PCIE_VDDR#1 LV21 BLM18PG121SN1D_0603
AD11 VDDR1#2 PCIE_VDDR#2 AA32
1 1 2 1 2 1 2 AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 2
CV86 10U_0603_6.3V6M CV56 1U_0402_6.3V4Z CV57 1U_0402_6.3V4Z AG10 AA34 CV87 10U_0603_6.3V6M
+ CV58 VDDR1#4 PCIE_VDDR#4
1 2 1 2 1 2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1 2
330U_X_2VM_R6M CV59 10U_0603_6.3V6M CV60 1U_0402_6.3V4Z CV61 1U_0402_6.3V4Z AK8 W29 CV62 1U_0402_6.3V4Z
@ VDDR1#6 PCIE_VDDR#6
1 2 1 2 1 2 AL9 VDDR1#7 PCIE_VDDR#7 W30 1 2
2 CV63 10U_0603_6.3V6M CV64 1U_0402_6.3V4Z CV65 1U_0402_6.3V4Z CV66 1U_0402_6.3V4Z
G11 VDDR1#8 PCIE_VDDR#8 Y31
1 2 1 2 1 2 G14 VDDR1#9 1 2
D CV67 10U_0603_6.3V6M CV68 1U_0402_6.3V4Z CV88 1U_0402_6.3V4Z G17 CV69 1U_0402_6.3V4Z D
VDDR1#10
1 2 1 2 1 2 G20 VDDR1#11 PCIE_VDDC#1 G30 1 2
Co-layout with CV58 CV89 10U_0603_6.3V6M CV70 1U_0402_6.3V4Z CV71 1U_0402_6.3V4Z G23 G31 CV72 1U_0402_6.3V4Z
1 2 1 2 G26
VDDR1#12 PCIE_VDDC#2
H29
2A +1.1VS 1 2
+VRAM_1.5VS CV73 1U_0402_6.3V4Z CV74 1U_0402_6.3V4Z VDDR1#13 PCIE_VDDC#3 CV75 1U_0402_6.3V4Z
G29 VDDR1#14 PCIE_VDDC#4 H30
1 2 1 2 H10 VDDR1#15 PCIE_VDDC#5 J29 1 2 1 2
CV90 1U_0402_6.3V4Z CV76 1U_0402_6.3V4Z J7 J30 CV91 10U_0603_6.3V6M CV77 0.1U_0402_16V4Z
VDDR1#16 PCIE_VDDC#6
1 1 2 1 2 J9 VDDR1#17 PCIE_VDDC#7 L28 1 2 1 2
CV78 1U_0402_6.3V4Z CV79 1U_0402_6.3V4Z K11 M28 CV92 1U_0402_6.3V4Z CV80 0.1U_0402_16V4Z
CV309 + VDDR1#18 PCIE_VDDC#8
1 2 1 2 K13 VDDR1#19 PCIE_VDDC#9 N28 1 2
390U_2.5V_M_R10 CV81 1U_0402_6.3V4Z CV82 1U_0402_6.3V4Z K8 R28 CV83 1U_0402_6.3V4Z
VDDR1#20 PCIE_VDDC#10
1 2 1 2 L12 VDDR1#21 PCIE_VDDC#11 T28 1 2
2 CV84 1U_0402_6.3V4Z CV85 1U_0402_6.3V4Z CV93 1U_0402_6.3V4Z
L16 VDDR1#22 PCIE_VDDC#12 U28
+1.5VS +VRAM_1.5VS L21 VDDR1#23 1 2 Co-layout with CV96, CV98
PJ28 L23 CV94 1U_0402_6.3V4Z
VDDR1#24
2 2 1 1 L26 VDDR1#25 VDDC#1 AA15 1 2
L7 CORE AA17 CV95 1U_0402_6.3V4Z +VGA_CORE
@ JUMP_43X79 VDDR1#26 VDDC#2
M11 VDDR1#27 VDDC#3 AA20 1 2
N11 AA22 CV97 1U_0402_6.3V4Z
PJ29 BLM18PG121SN1D_0603 VDDR1#28 VDDC#4
136mA P7 VDDR1#29 VDDC#5 AA24 1 2 1 1
2 1 R11 AA27 CV100 1U_0402_6.3V4Z
2 1 +VDD_CT VDDR1#30 VDDC#6 CV310 + + CV311
+1.8VS 2 1 U11 VDDR1#31 VDDC#7 AB13
@ JUMP_43X79 LV22 U7 AB16 390U_2.5V_M_R10 390U_2.5V_M_R10
VDDR1#32 VDDC#8
1 2 Y11 VDDR1#33 VDDC#9 AB18
CV101 10U_0603_6.3V6M 2 2
Y7 VDDR1#34 VDDC#10 AB21
1 2 AB23 +VGA_CORE
BLM18PG121SN1D_0603 170mA CV105 1U_0402_6.3V4Z VDDC#11
AB26
+1.8VS 2 1 0.1U_0402_16V4Z +VDDR5 1 2
VDDC#12
AB28
25A
LV23 CV109 1U_0402_6.3V4Z VDDC#13
1 1 VDDC#14 AC12 1 1
CV140 CV141 2 1 LEVEL AC15
CV113 0.1U_0402_16V4Z TRANSLATION VDDC#15 + CV98 + CV96
VDDC#16 AC17

POWER
C 1U_0402_6.3V4Z 1 2 +VDD_CT AF26 AC20 330U_X_2VM_R6M 330U_X_2VM_R6M C
2 2 CV117 1U_0402_6.3V4Z VDD_CT#1 VDDC#17 @ @
AF27 VDD_CT#2 VDDC#18 AC22
2 2
AG26 VDD_CT#3 VDDC#19 AC24
170mA AG27 VDD_CT#4 VDDC#20 AC27
BLM18PG121SN1D_0603 AD13
+VDDR4 VDDC#21
+1.8VS 2 1 0.1U_0402_16V4Z VDDC#22 AD16
LV24 I/O AD18 1 2 1 2 1 2
1
CV156
1
CV157 +3VS_DELAY
60mA AF23
VDDC#23
AD21 CV102 10U_0603_6.3V6M CV103 1U_0402_6.3V4Z CV104 1U_0402_6.3V4Z
VDDR3#1 VDDC#24
1 2 AF24 VDDR3#2 VDDC#25 AD23 1 2 1 2 1 2
1U_0402_6.3V4Z CV130 10U_0603_6.3V6M AG23 AD26 CV106 10U_0603_6.3V6M CV107 1U_0402_6.3V4Z CV108 1U_0402_6.3V4Z
2 2 VDDR3#3 VDDC#26
1 2 AG24 VDDR3#4 VDDC#27 AF17 1 2 1 2 1 2
CV134 1U_0402_6.3V4Z AF20 CV110 10U_0603_6.3V6M CV111 1U_0402_6.3V4Z CV112 1U_0402_6.3V4Z
VDDC#28
1 2 VDDC#29 AF22 1 2 1 2 1 2
CV138 1U_0402_6.3V4Z AF13 AG16 CV114 10U_0603_6.3V6M CV115 1U_0402_6.3V4Z CV116 1U_0402_6.3V4Z
VDDR5#1 VDDC#30
1 2 AF15 VDDR5#2 VDDC#31 AG18 1 2 1 2 1 2
BLM18PG121SN1D_0603 CV144 1U_0402_6.3V4Z +VDDR5 AG13 AG21 CV118 10U_0603_6.3V6M CV119 1U_0402_6.3V4Z CV120 1U_0402_6.3V4Z
0.1U_0402_16V4Z +MPV18 VDDR5#3 VDDC#32
+1.8VS 2 1 AG15 VDDR5#4 VDDC#33 AH22 1 2 1 2 1 2
LV35 1 1 1 M16 CV121 10U_0603_6.3V6M CV122 1U_0402_6.3V4Z CV123 1U_0402_6.3V4Z
@ CV305 CV304 CV303 VDDC#34
VDDC#35 M18 1 2 1 2 1 2
@ @ @ AD12 M23 CV124 10U_0603_6.3V6M CV125 1U_0402_6.3V4Z CV126 1U_0402_6.3V4Z
10U_0603_6.3V6M 1U_0402_6.3V4Z +VDDR4 VDDR4#1 VDDC#36
AF11 VDDR4#2 VDDC#37 M26 1 2 1 2 1 2
2 2 2 CV127 1U_0402_6.3V4Z CV128 1U_0402_6.3V4Z CV129 1U_0402_6.3V4Z
AF12 VDDR4#3 VDDC#38 N15
NC for Park and Madison support. AG11 VDDR4#4 VDDC#39 N17 1 2 1 2 1 2
N20 CV131 1U_0402_6.3V4Z CV132 1U_0402_6.3V4Z CV133 1U_0402_6.3V4Z
BLM18PG121SN1D_0603 BLM18PG121SN1D_0603 VDDC#40
1A VDDC#41 N22 1 2 1 2 1 2
+1.8VS 2 1 0.1U_0402_16V4Z +SPV18 +VRAM_1.5VS 2 1 N24 CV135 1U_0402_6.3V4Z CV136 1U_0402_6.3V4Z CV137 1U_0402_6.3V4Z
LV36 LV25 MEM CLK VDDC#42
1 1 1 VDDC#43 N27 1 2 1 2
@ CV308 CV307 CV306 2 1 +VDDRHA M20 R13 CV142 1U_0402_6.3V4Z CV143 1U_0402_6.3V4Z
@ @ @ CV162 1U_0402_6.3V4Z VDDRHA VDDC#44
M21 VSSRHA VDDC#45 R16 1 2 1 2
10U_0603_6.3V6M 1U_0402_6.3V4Z R18 CV145 1U_0402_6.3V4Z CV146 1U_0402_6.3V4Z
2 2 2 BLM18PG121SN1D_0603 VDDC#46
VDDC#47 R21 1 2 1 2
B +VDDRHB CV147 1U_0402_6.3V4Z CV148 1U_0402_6.3V4Z B
2 1 V12 VDDRHB VDDC#48 R23
LV26 2 1 U12 R26 1 2 1 2
CV167 VSSRHB VDDC#49 CV149 1U_0402_6.3V4Z CV150 1U_0402_6.3V4Z
VDDC#50 T15
1U_0402_6.3V4Z T17 1 2 1 2
Reserve for Park and Madison support. VDDC#51
T20 CV151 1U_0402_6.3V4Z CV152 1U_0402_6.3V4Z
VDDC#52
VDDC#53 T22 1 2 1 2
BLM18PG121SN1D_0603 PLL T24 CV153 1U_0402_6.3V4Z CV154 1U_0402_6.3V4Z
+1.8VS 2 1 0.1U_0402_16V4Z 68mA +PCIE_PVDD AB37
VDDC#54
T27 1 2 1 2
LV27 PCIE_PVDD VDDC#55 CV158 1U_0402_6.3V4Z CV159 1U_0402_6.3V4Z
1 1 1 VDDC#56 U16
CV168 CV169 CV170 +MPV18 H7 U18 1 2 1 2
NC_MPV18#1 VDDC#57 CV160 1U_0402_6.3V4Z CV161 1U_0402_6.3V4Z
H8 NC_MPV18#2 VDDC#58 U21
10U_0603_6.3V6M 1U_0402_6.3V4Z U23 1 2 1 2
2 2 2 VDDC#59 CV163 1U_0402_6.3V4Z CV164 1U_0402_6.3V4Z
VDDC#60 U26
+SPV18 AM10 V15 1 2 1 2
BLM18PG121SN1D_0603 1U_0402_6.3V4Z NC_SPV18 VDDC#61 CV165 1U_0402_6.3V4Z CV166 1U_0402_6.3V4Z
QV1 414mA +SPV10 VDDC#62 V17
+VGA_CORE 2 1 AN9 SPV10 VDDC#63 V20
AO3413_SOT23 LV28 1 1 2 V22
BLM18PG121SN1D_0603 CV171 CV172 CV173 VDDC#64
100mA AN10 SPVSS VDDC#65 V24
S

+3VS 3 1 +3VS_DELAY +1.1VS 2 1 VDDC#66 V27

LV34 10U_0603_6.3V6M Y16
@ 2 2 1 VDDC#67
2 1 VDDC#68 Y18
CV217 CV211 0.1U_0402_16V4Z
G

Y21
2

0.1U_0402_16V7K 0.01U_0402_25V7K BACK BIAS VDDC#69

VDDC#70 Y23
1 2 Preserve for Park and Madison support. VDDC#71 Y26
+VGA_CORE AA13 BBP#1 VDDC#72 Y28
Y13 BBP#2 VDDC#73 AH27
2 1 VDDC#74 AH28 2A
2

CV174 CV175 BLM18PG121SN1D_0603

RV53 M15 +VDDCI 1U_0402_6.3V4Z 2 1 +VGA_CORE
47K_0402_5% +3VS 0.1U_0402_16V4Z ISOLATED VDDCI#1 N13 1 1 1 1 LV29
1 2 CORE I/O VDDCI#2 R12 CV176 CV177 CV178
A VDDCI#3 A
1U_0402_6.3V4Z T12 CV179
1

VDDCI#4 10U_0603_6.3V6M
1 2
RV136 100K_0402_5% 2 2 2 2
1

D 1U_0402_6.3V4Z 1U_0402_6.3V4Z
QV2 2 2 1 216-0729002 A12 M96_BGA962 M96PRO@
PCIE_OK 52
2N7002_SOT23-3 G 0_0402_5% RV44
S 1 Security Classification Compal Secret Data Compal Electronics, Inc.
3

From 1.5VP<-->1.1VSP Chip

CV180 2009/01/23 2010/01/23 Title
0.1U_0402_16V4Z
Issued Date Deciphered Date
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 16 of 58
5 4 3 2 1
 5 4 3 2 1

UV1F

AB39 PCIE_VSS#1 GND#1 A3

E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 PCIE_VSS#9 GND#9 AA28
J31 PCIE_VSS#10 GND#10 AA6
D D
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
K34 PCIE_VSS#13 GND#13 AB17
K39 PCIE_VSS#14 GND#14 AB20
L31 PCIE_VSS#15 GND#15 AB22
L34 PCIE_VSS#16 GND#16 AB24
M34 PCIE_VSS#17 GND#17 AB27
M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18
P34 PCIE_VSS#22 GND#22 AC2
P39 PCIE_VSS#23 GND#23 AC21
R34 PCIE_VSS#24 GND#24 AC23
T31 PCIE_VSS#25 GND#25 AC26
T34 PCIE_VSS#26 GND#26 AC28
T39 PCIE_VSS#27 GND#27 AC6
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17
V34 PCIE_VSS#30 GND#30 AD20
V39 PCIE_VSS#31 GND#31 AD22
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 PCIE_VSS#34 GND#34 AD9
Y39 PCIE_VSS#35 GND#35 AE2
GND#36 AE6
GND#37 AF10
GND#38 AF16
GND#39 AF18 Reserve for Park and Madison support.
AF21

F15 GND#101
GND GND#40
GND#41
GND#42
AG17
AG2

2
C C
F17 GND#102 GND#43 AG20
F19 AG22 RV157
GND#103 GND#44
F21 GND#104 GND#45 AG6 0_0402_5%
F23 GND#105 GND#46 AG9
F25 AH21

1
GND#106 GND#47
F27 GND#107 GND#48 AH29 T52
F29 GND#108 GND#49 AJ10
F31 GND#109 GND#50 AJ11
F33 GND#110 GND#51 AJ2
F7 GND#111 GND#52 AJ28
F9 GND#112 GND#53 AJ6
G2 GND#113 GND#54 AK11
G6 GND#114 GND#55 AK31
H9 GND#115 GND#56 AK7

2
J2 GND#116 GND#57 AL11
J27 AL14 RV156
GND#117 GND#58
J6 GND#118 GND#59 AL17 0_0402_5%
J8 GND#119 GND#60 AL2
K14 AL20

1
GND#120 GND#61
K7 GND#121 GND#62 AL21 T46
L11 GND#122 GND#63 AL23
L17 GND#123 GND#64 AL26

1
L2 GND#124 GND#65 AL32
L22 AL6 @
GND#125 GND#66 RV24
L24 GND#126 GND#67 AL8
L6 GND#127 GND#68 AM11 10K_0402_5%
M17 AM31

2
GND#128 GND#69
M22 GND#129 GND#70 AM9
M24 GND#130 GND#71 AN11
N16 GND#131 GND#72 AN2
N18 GND#132 GND#73 AN30
N2 GND#133 GND#74 AN6
B B
N21 GND#134 GND#75 AN8
N23 AP11
N26
GND#135 GND#76
AP7
Reserve for Park and Madison support.
GND#136 GND#77
N6 GND#137 GND#78 AP9
R15 GND#138 GND#79 AR5
R17 GND#139 GND#80 AW34
R2 GND#140 GND#81 B11
R20 GND#141 GND#82 B13
R22 GND#142 GND#83 B15
R24 GND#143 GND#84 B17
R27 GND#144 GND#85 B19
R6 GND#145 GND#86 B21
T11 GND#146 GND#87 B23
T13 GND#147 GND#88 B25
T16 GND#148 GND#89 B27
T18 GND#149 GND#90 B29
T21 GND#150 GND#91 B31
T23 GND#151 GND#92 B33
T26 GND#152 GND#93 B7
U15 GND#153 GND#94 B9
U17 GND#154 GND#95 C1
U2 GND#155 GND#96 C39
U20 GND#156 GND#97 E35
U22 GND#157 GND#98 E5
U24 GND#158 GND#99 F11
U27 GND#159 GND#100 F13
U6 GND#160
V11 GND#161
V16 GND#162
V18 GND#163
V21 GND#164
V23 GND#165
A A
V26 GND#166
W2 GND#167
W6 GND#168
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24 AW1
Y27
GND#173
GND#174
VSS_MECH#2
VSS_MECH#3 AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13 GND#175 Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
V13 GND#176
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
216-0729002 A12 M96_BGA962 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
M96PRO@ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 17 of 58
5 4 3 2 1
 5 4 3 2 1

M92-M2 uses memory group B only

D D
UV1C
UV1D

MDA[0..63] MDA0 C37 G24 MAA0 MAA[12..0]

19 MDA[0..63] DQA_0 MAA_0 MAA[12..0] 19 MDB[0..63] MAB[12..0]
MDA1 C35 J23 MAA1 MDB0 C5 P8 MAB0
DQA_1 MAA_1 20 MDB[0..63] DQB_0 MAB_0 MAB[12..0] 20

MEMORY INTERFACE A
MDA2 A35 H24 MAA2 MDB1 C3 T9 MAB1
DQA_2 MAA_2 DQB_1 MAB_1

MEMORY INTERFACE B
MDA3 E34 J24 MAA3 MDB2 E3 P9 MAB2
MDA4 DQA_3 MAA_3 MAA4 MDB3 DQB_2 MAB_2 MAB3
G32 DQA_4 MAA_4 H26 E1 DQB_3 MAB_3 N7
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
MDA6 DQA_5 MAA_5 MAA6 MDB5 DQB_4 MAB_4 MAB5
F32 DQA_6 MAA_6 H21 F3 DQB_5 MAB_5 N9
MDA7 E32 G21 MAA7 MDB6 F5 U9 MAB6
MDA8 DQA_7 MAA_7 MAA8 MDB7 DQB_6 MAB_6 MAB7
D31 DQA_8 MAA_8 H19 G4 DQB_7 MAB_7 U8
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 DQA_9 MAA_9 MAA10 MDB9 DQB_8 MAB_8 MAB9
C30 DQA_10 MAA_10 L13 H6 DQB_9 MAB_9 W9
MDA11 A30 G16 MAA11 A_BA[2..0] MDB10 J4 AC8 MAB10
DQA_11 MAA_11 A_BA[2..0] 19 DQB_10 MAB_10
MDA12 F28 J16 MAA12 MDB11 K6 AC9 MAB11
MDA13 DQA_12 MAA_12 A_BA2 MDB12 DQB_11 MAB_11 MAB12
C28 DQA_13 MAA_13/BA2 H16 K5 DQB_12 MAB_12 AA7
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2 B_BA[2..0]
DQA_14 MAA_14/BA0 DQB_13 MAB_13/BA2 B_BA[2..0] 20
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
MDA16 DQA_15 MAA_15/BA1 MDB15 DQB_14 MAB_14/BA0 B_BA1
D27 DQA_16 M1 DQB_15 MAB_15/BA1 AA9
MDA17 F26 A32 DQMA#0 MDB16 M3
DQA_17 DQMA_0 DQMA#[7..0] 19 DQB_16
MDA18 C26 C32 DQMA#1 MDB17 M5 H3 DQMB#0
DQA_18 DQMA_1 DQB_17 DQMB_0 DQMB#[7..0] 20
MDA19 A26 D23 DQMA#2 MDB18 N4 H1 DQMB#1
MDA20 DQA_19 DQMA_2 DQMA#3 MDB19 DQB_18 DQMB_1 DQMB#2
F24 DQA_20 DQMA_3 E22 P6 DQB_19 DQMB_2 T3
MDA21 C24 C14 DQMA#4 MDB20 P5 T5 DQMB#3
MDA22 DQA_21 DQMA_4 DQMA#5 MDB21 DQB_20 DQMB_3 DQMB#4
A24 DQA_22 DQMA_5 A14 R4 DQB_21 DQMB_4 AE4
MDA23 E24 E10 DQMA#6 MDB22 T6 AF5 DQMB#5
C MDA24 DQA_23 DQMA_6 DQMA#7 MDB23 DQB_22 DQMB_5 DQMB#6 C
C22 DQA_24 DQMA_7 D9 T1 DQB_23 DQMB_6 AK6
MDA25 A22 MDB24 U4 AK5 DQMB#7
MDA26 DQA_25 QSA0 MDB25 DQB_24 DQMB_7
F22 DQA_26 QSA_0/RDQSA_0 C34 QSA[7..0] 19 V6 DQB_25
MDA27 D21 D29 QSA1 MDB26 V1 F6 QSB0
DQA_27 QSA_1/RDQSA_1 DQB_26 QSB_0/RDQSB_0 QSB[7..0] 20
MDA28 A20 D25 QSA2 MDB27 V3 K3 QSB1
MDA29 DQA_28 QSA_2/RDQSA_2 QSA3 MDB28 DQB_27 QSB_1/RDQSB_1 QSB2
F20 DQA_29 QSA_3/RDQSA_3 E20 Y6 DQB_28 QSB_2/RDQSB_2 P3
MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
MDA31 DQA_30 QSA_4/RDQSA_4 QSA5 MDB30 DQB_29 QSB_3/RDQSB_3 QSB4
E18 DQA_31 QSA_5/RDQSA_5 E12 Y3 DQB_30 QSB_4/RDQSB_4 AB5
Close to pin L18 MDA32 C18 J10 QSA6 MDB31 Y5 AH1 QSB5
MDA33 DQA_32 QSA_6/RDQSA_6 QSA7 MDB32 DQB_31 QSB_5/RDQSB_5 QSB6
A18 DQA_33 QSA_7/RDQSA_7 D7 AA4 DQB_32 QSB_6/RDQSB_6 AJ9
+VRAM_1.5VS MDA34 MDB33 QSB7
F18 DQA_34 Close to pin Y12 AB6 DQB_33 QSB_7/RDQSB_7 AM5
MDA35 D17 A34 QSA#0 MDB34 AB1
DQA_35 QSA_0B/WDQSA_0 QSA#[7..0] 19 +VRAM_1.5VS DQB_34
MDA36 A16 E30 QSA#1 MDB35 AB3 G7 QSB#0
DQA_36 QSA_1B/WDQSA_1 DQB_35 QSB_0B/WDQSB_0 QSB#[7..0] 20
1

MDA37 F16 E26 QSA#2 MDB36 AD6 K1 QSB#1

RV45 MDA38 DQA_37 QSA_2B/WDQSA_2 QSA#3 MDB37 DQB_36 QSB_1B/WDQSB_1 QSB#2
D15 DQA_38 QSA_3B/WDQSA_3 C20 AD1 DQB_37 QSB_2B/WDQSB_2 P1

1
100_0402_1% MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3
MDA40 DQA_39 QSA_4B/WDQSA_4 QSA#5 RV46 MDB39 DQB_38 QSB_3B/WDQSB_3 QSB#4
F14 DQA_40 QSA_5B/WDQSA_5 C12 AD5 DQB_39 QSB_4B/WDQSB_4 AC4
MDA41 D13 J11 QSA#6 100_0402_1% MDB40 AF1 AH3 QSB#5
2

MDA42 DQA_41 QSA_6B/WDQSA_6 QSA#7 MDB41 DQB_40 QSB_5B/WDQSB_5 QSB#6

F12 DQA_42 QSA_7B/WDQSA_7 F8 AF3 DQB_41 QSB_6B/WDQSB_6 AJ8
+MVREFDA MDA43 A12 MDB42 AF6 AM3 QSB#7

2
MDA44 DQA_43 ODTA0 MDB43 DQB_42 QSB_7B/WDQSB_7
D11 DQA_44 ODTA0 J21 ODTA0 19 AG4 DQB_43
1 MDA45 F10 G19 ODTA1 +MVREFDB MDB44 AH5 T7 ODTB0
DQA_45 ODTA1 ODTA1 19 DQB_44 ODTB0 ODTB0 20
1

CV181 MDA46 A10 MDB45 AH6 W7 ODTB1

DQA_46 DQB_45 ODTB1 ODTB1 20
RV47 MDA47 C10 H27 CLKA0 1 MDB46 AJ4
DQA_47 CLKA0 CLKA0 19 DQB_46

1
100_0402_1% 0.1U_0402_16V4Z MDA48 G13 G27 CLKA0# CV182 MDB47 AK3 L9 CLKB0
2 DQA_48 CLKA0B CLKA0# 19 DQB_47 CLKB0 CLKB0 20
MDA49 H13 RV48 0.1U_0402_16V4Z MDB48 AF8 L8 CLKB0#
DQA_49 DQB_48 CLKB0B CLKB0# 20
MDA50 J13 J14 CLKA1 100_0402_1% MDB49 AF9
CLKA1 19
2

MDA51 DQA_50 CLKA1 CLKA1# 2 MDB50 DQB_49 CLKB1

H11 DQA_51 CLKA1B H14 CLKA1# 19 AG8 DQB_50 CLKB1 AD8 CLKB1 20
MDA52 G10 MDB51 AG7 AD7 CLKB1#
CLKB1# 20

2
B MDA53 DQA_52 RASA0# MDB52 DQB_51 CLKB1B B
G8 DQA_53 RASA0B K23 RASA0# 19 AK9 DQB_52
MDA54 K9 K19 RASA1# MDB53 AL7 T10 RASB0#
DQA_54 RASA1B RASA1# 19 DQB_53 RASB0B RASB0# 20
MDA55 K10 MDB54 AM8 Y10 RASB1#
DQA_55 DQB_54 RASB1B RASB1# 20
Close to pin L20 MDA56 G9 K20 CASA0# MDB55 AM7
DQA_56 CASA0B CASA0# 19 DQB_55
MDA57 A8 K17 CASA1# MDB56 AK1 W10 CASB0#
+VRAM_1.5VS DQA_57 CASA1B CASA1# 19 DQB_56 CASB0B CASB0# 20
MDA58 C8 Close to pin AA12 MDB57 AL4 AA10 CASB1#
DQA_58 DQB_57 CASB1B CASB1# 20
MDA59 E8 K24 CSA0#_0 MDB58 AM6
DQA_59 CSA0B_0 CSA0#_0 19 +VRAM_1.5VS DQB_58
MDA60 A6 K27 MDB59 AM1 P10 CSB0#_0
DQA_60 CSA0B_1 DQB_59 CSB0B_0 CSB0#_0 20
1

MDA61 C6 MDB60 AN4 L10

RV49 MDA62 DQA_61 CSA1#_0 MDB61 DQB_60 CSB0B_1
E6 DQA_62 CSA1B_0 M13 CSA1#_0 19 AP3 DQB_61

1
100_0402_1% MDA63 A5 K16 MDB62 AP1 AD10 CSB1#_0
DQA_63 CSA1B_1 DQB_62 CSB1B_0 CSB1#_0 20
RV50 MDB63 AP5 AC10
+MVREFDA CKEA0 100_0402_1% DQB_63 CSB1B_1
L18 K21 CKEA0 19
2

+MVREFSA MVREFDA CKEA0 CKEA1 CKEB0

L20 MVREFSA CKEA1 J20 CKEA1 19 CKEB0 U10 CKEB0 20
+VRAM_1.5VS Y12 AA11 CKEB1
CKEB1 20

2
@ WEA0# +MVREFSB MVREFDB CKEB1
1 2 L27 NC_MEM_CALRN0 WEA0B K26 WEA0# 19 AA12 MVREFSB
1

1 RV561 @ 2243_0402_1%N12 L15 WEA1# N10 WEB0#

NC_MEM_CALRN1 WEA1B WEA1# 19 WEB0B WEB0# 20
RV51 CV183 RV591 @ 2243_0402_1%
AG12 AB11 WEB1#
NC_MEM_CALRN2 WEB1B WEB1# 20

1
100_0402_1% RV60 243_0402_1% AF28 1
RSVD#1 T50
0.1U_0402_16V4Z 1 2 M12 AG28 RV57 CV184 RV58 4.7K_0402_5%
2 MEM_CALRP1 RSVD#2 T51
RV55
1 @ 2243_0402_1%M27 AL31 100_0402_1% TESTEN AD28 2 1 +VRAM_1.5VS
2

RV126 @ NC_MEM_CALRP0 RSVD#3 TESTEN

1 2243_0402_1%
AH12 NC_MEM_CALRP2 Reserve for Park and Madison support. 0.1U_0402_16V4Z
RV127 243_0402_1% 2
H23 AK10
2

RSVD#5 CLKTESTA
RSVD#6 J19 AL10 CLKTESTB DRAM_RST AH11 DRAM_RST# 19,20
1

2
RSVD#9 T8
W8 RV64 RV61 RV62 @ RV63 CV185
RSVD#11 4.7K_0402_5% 4.7K_0402_5% 0.01U_0402_16V7K
1K_0402_5% 2
A Reserve for Park and Madison support. 4.7K_0402_5%
A

1
216-0729002 A12 M96_BGA962 216-0729002 A12 M96_BGA962

M96PRO@ M96PRO@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 18 of 58
5 4 3 2 1
 5 4 3 2 1

UV3 UV4 UV5 UV6

+VREFC_A1 M8 E3 MDA22 +VREFC_A2 M8 E3 MDA25 +VREFC_A3 M8 E3 MDA35 +VREFC_A4 M8 E3 MDA48

+VREFD_A1 H1 VREFCA DQL0 MDA19 +VREFD_A2 VREFCA DQL0 MDA30 +VREFD_A3 VREFCA DQL0 MDA32 +VREFD_A4 VREFCA DQL0 MDA51
VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDA21 F2 MDA24 F2 MDA38 F2 MDA55
MDA[0..63] MAA0 DQL2 MDA18 MAA0 DQL2 MDA29 MAA0 DQL2 MDA34 MAA0 DQL2 MDA54
18 MDA[0..63] N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAA1 P7 H3 MDA23 Group2 MAA1 P7 H3 MDA26 Group3 MAA1 P7 H3 MDA37 Group4 MAA1 P7 H3 MDA50 Group6
MAA2 A1 DQL4 MDA16 MAA2 A1 DQL4 MDA31 MAA2 A1 DQL4 MDA36 MAA2 A1 DQL4 MDA52
18 MAA[12..0] P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA20 MAA3 N2 G2 MDA27 MAA3 N2 G2 MDA39 MAA3 N2 G2 MDA49
MAA4 A3 DQL6 MDA17 MAA4 A3 DQL6 MDA28 MAA4 A3 DQL6 MDA33 MAA4 A3 DQL6 MDA53
18 DQMA#[7..0] P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2 MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5 MAA6 A5 MAA6 A5
18 QSA[7..0] R8 A6 R8 A6 R8 A6 R8 A6
MAA7 R2 D7 MDA0 MAA7 R2 D7 MDA15 MAA7 R2 D7 MDA43 MAA7 R2 D7 MDA63
MAA8 A7 DQU0 MDA5 MAA8 A7 DQU0 MDA11 MAA8 A7 DQU0 MDA44 MAA8 A7 DQU0 MDA58
18 QSA#[7..0] T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
D MAA9 MDA1 MAA9 MDA14 MAA9 MDA40 MAA9 MDA60 D
R3 A9 DQU2 C8 R3 A9 DQU2 C8 R3 A9 DQU2 C8 R3 A9 DQU2 C8
MAA10 L7 C2 MDA7 MAA10 L7 C2 MDA10 MAA10 L7 C2 MDA45 MAA10 L7 C2 MDA59
MAA11 A10/AP DQU3 MDA3 MAA11 A10/AP DQU3 MDA13 MAA11 A10/AP DQU3 MDA42 MAA11 A10/AP DQU3 MDA61
R7 A11 DQU4 A7 Group0 R7 A11 DQU4 A7 Group1 R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group7
MAA12 N7 A2 MDA4 MAA12 N7 A2 MDA9 MAA12 N7 A2 MDA46 MAA12 N7 A2 MDA56
A12 DQU5 MDA2 A12 DQU5 MDA12 A12 DQU5 MDA41 A12 DQU5 MDA62
T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8 T3 A13 DQU6 B8
T7 A3 MDA6 T7 A3 MDA8 T7 A3 MDA47 T7 A3 MDA57
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

18 A_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 A_BA1 N8 D9 A_BA1 N8 D9 A_BA1 N8 D9
18 A_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 A_BA2 M3 G7 A_BA2 M3 G7 A_BA2 M3 G7
18 A_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKA0 J7 N9 J7 N9 CLKA1 J7 N9
18 CLKA0 CK VDD CK VDD 18 CLKA1 CK VDD CK VDD
K7 R1 CLKA0# K7 R1 K7 R1 CLKA1# K7 R1
18 CLKA0# CK VDD CK VDD 18 CLKA1# CK VDD CK VDD
K9 R9 CKEA0 K9 R9 K9 R9 CKEA1 K9 R9
18 CKEA0 CKE/CKE0 VDD CKE/CKE0 VDD 18 CKEA1 CKE/CKE0 VDD CKE/CKE0 VDD

K1 A1 ODTA0 K1 A1 K1 A1 ODTA1 K1 A1
18 ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 18 ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSA0#_0 L2 A8 L2 A8 CSA1#_0 L2 A8
18 CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ 18 CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
18 RASA0# RAS VDDQ RAS VDDQ 18 RASA1# RAS VDDQ RAS VDDQ
K3 C9 CASA0# K3 C9 K3 C9 CASA1# K3 C9
18 CASA0# CAS VDDQ CAS VDDQ 18 CASA1# CAS VDDQ CAS VDDQ
L3 D2 WEA0# L3 D2 L3 D2 WEA1# L3 D2
18 WEA0# WE VDDQ WE VDDQ 18 WEA1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 H2 QSA3 F3 H2 QSA4 F3 H2 QSA6 F3 H2
QSA0 DQSL VDDQ QSA1 DQSL VDDQ QSA5 DQSL VDDQ QSA7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9

C DQMA#0 DML VSS DQMA#1 DML VSS DQMA#5 DML VSS DQMA#7 DML VSS C
D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 J2 QSA#3 G3 J2 QSA#4 G3 J2 QSA#6 G3 J2
QSA#0 DQSL VSS QSA#1 DQSL VSS QSA#5 DQSL VSS QSA#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
18,20 DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV65 L1 B9 RV66 L1 B9 RV67 L1 B9 RV68 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
8PCS@ E2 8PCS@ E2 8PCS@ E2 8PCS@ E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
8PCS@ G1 G1 G1 G1
CLKA0 VSSQ VSSQ VSSQ VSSQ
1 2 VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
RV85 56_0402_1%
96-BALL 96-BALL 96-BALL 96-BALL
8PCS@ SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
CLKA0# 1 2 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
RV86 56_0402_1% @ @ @ @
1 +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS
CV201
0.1U_0402_16V4Z

1
8PCS@ +VRAM_1.5VS +VRAM_1.5VS
2 +VRAM_1.5VS +VRAM_1.5VS RV73 8PCS@ RV74 8PCS@ RV75 8PCS@ RV76 8PCS@
B 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% B
1

1
8PCS@

2
CLKA1 1 2 RV69 RV70 RV71 RV72 +VREFC_A3 +VREFD_A3 +VREFC_A4 +VREFD_A4
RV87 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%

1
8PCS@ 8PCS@ 8PCS@ 8PCS@ 1 1 1 1
8PCS@ RV82 CV188 RV78 CV189 RV83 CV190 RV84 CV193
2

CLKA1# 1 2 +VREFC_A1 +VREFD_A1 +VREFC_A2 +VREFD_A2 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%

RV88 56_0402_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1

2 2 2 2
1 1 1 1 1

2
CV237 RV77 CV186 RV79 CV191 RV80 CV192 RV81 CV187
0.1U_0402_16V4Z 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
8PCS@ 8PCS@ 0.1U_0402_16V4Z 8PCS@ 0.1U_0402_16V4Z 8PCS@ 0.1U_0402_16V4Z 8PCS@ 0.1U_0402_16V4Z
2 2 8PCS@ 2 8PCS@ 2 8PCS@ 2 8PCS@
2

+VRAM_1.5VS +VRAM_1.5VS

+VRAM_1.5VS 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

+VRAM_1.5VS
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z CV212 CV213 CV197 CV214 CV226 CV215 CV216 CV198 CV199 CV218 CV200 CV219 CV220 CV221
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV194 CV202 CV223 CV195 CV224 CV203 CV204 CV206 CV225 CV196 CV207 CV208 CV209 CV210
8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 8PCS@ 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
+VRAM_1.5VS 10U_0603_6.3V
1 1 1 1
A A
CV233 CV234 CV227 CV235
+VRAM_1.5VS 10U_0603_6.3V 8PCS@ 8PCS@ 8PCS@
8PCS@ 2 2 2 2
10U_0603_6.3V 10U_0603_6.3V 10U_0603_6.3V
1 1 1 1
CV228 CV229 CV230 CV231
10U_0603_6.3V
8PCS@ 2
8PCS@
2
8PCS@
2
8PCS@
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
10U_0603_6.3V 10U_0603_6.3V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 19 of 58
5 4 3 2 1
 5 4 3 2 1

UV7 UV8 UV9 UV10

MDB[0..63]
18 MDB[0..63]
+VREFC_B1 M8 E3 MDB26 +VREFC_B2 M8 E3 MDB22 +VREFC_B3 M8 E3 MDB34 +VREFC_B4 M8 E3 MDB52
+VREFD_B1 VREFCA DQL0 MDB28 +VREFD_B2 VREFCA DQL0 MDB20 +VREFD_B3 VREFCA DQL0 MDB37 +VREFD_B4 VREFCA DQL0 MDB51
18 MAB[12..0] H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7
F2 MDB27 F2 MDB21 F2 MDB32 F2 MDB55
MAB0 DQL2 MDB31 MAB0 DQL2 MDB18 MAB0 DQL2 MDB39 MAB0 DQL2 MDB48
18 DQMB#[7..0] N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8 N3 A0 DQL3 F8
MAB1 P7 H3 MDB25 Group3 MAB1 P7 H3 MDB19 Group2 MAB1 P7 H3 MDB35 Group4 MAB1 P7 H3 MDB53 Group6
MAB2 A1 DQL4 MDB30 MAB2 A1 DQL4 MDB17 MAB2 A1 DQL4 MDB38 MAB2 A1 DQL4 MDB49
18 QSB[7..0] P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB24 MAB3 N2 G2 MDB23 MAB3 N2 G2 MDB33 MAB3 N2 G2 MDB54
MAB4 A3 DQL6 MDB29 MAB4 A3 DQL6 MDB16 MAB4 A3 DQL6 MDB36 MAB4 A3 DQL6 MDB50
18 QSB#[7..0] P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2 MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5 MAB6 A5 MAB6 A5
R8 A6 R8 A6 R8 A6 R8 A6
MAB7 R2 D7 MDB15 MAB7 R2 D7 MDB1 MAB7 R2 D7 MDB44 MAB7 R2 D7 MDB56
D MAB8 A7 DQU0 MDB10 MAB8 A7 DQU0 MDB6 MAB8 A7 DQU0 MDB43 MAB8 A7 DQU0 MDB59 D
T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAB9 R3 C8 MDB12 MAB9 R3 C8 MDB0 MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB63
MAB10 A9 DQU2 MDB11 MAB10 A9 DQU2 MDB4 MAB10 A9 DQU2 MDB41 MAB10 A9 DQU2 MDB62
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAB11 R7 A7 MDB13 Group1 MAB11 R7 A7 MDB3 Group0 MAB11 R7 A7 MDB45 Group5 MAB11 R7 A7 MDB57 Group7
MAB12 A11 DQU4 MDB9 MAB12 A11 DQU4 MDB7 MAB12 A11 DQU4 MDB40 MAB12 A11 DQU4 MDB61
N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2 N7 A12 DQU5 A2
T3 B8 MDB14 T3 B8 MDB2 T3 B8 MDB46 T3 B8 MDB58
A13 DQU6 MDB8 A13 DQU6 MDB5 A13 DQU6 MDB42 A13 DQU6 MDB60
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3 M7 A15/BA3 M7 A15/BA3
+VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

18 B_BA0 BA0 VDD BA0 VDD BA0 VDD BA0 VDD
N8 D9 B_BA1 N8 D9 B_BA1 N8 D9 B_BA1 N8 D9
18 B_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M3 G7 B_BA2 M3 G7 B_BA2 M3 G7 B_BA2 M3 G7
18 B_BA2 BA2 VDD BA2 VDD BA2 VDD BA2 VDD
VDD K2 VDD K2 VDD K2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
J7 N9 CLKB0 J7 N9 J7 N9 CLKB1 J7 N9
18 CLKB0 CK VDD CK VDD 18 CLKB1 CK VDD CK VDD
K7 R1 CLKB0# K7 R1 K7 R1 CLKB1# K7 R1
18 CLKB0# CK VDD CK VDD 18 CLKB1# CK VDD CK VDD
K9 R9 CKEB0 K9 R9 K9 R9 CKEB1 K9 R9
18 CKEB0 CKE/CKE0 VDD CKE/CKE0 VDD 18 CKEB1 CKE/CKE0 VDD CKE/CKE0 VDD

K1 A1 ODTB0 K1 A1 K1 A1 ODTB1 K1 A1
18 ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ 18 ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
L2 A8 CSB0#_0 L2 A8 L2 A8 CSB1#_0 L2 A8
18 CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ 18 CSB1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1 J3 C1 RASB1# J3 C1
18 RASB0# RAS VDDQ RAS VDDQ 18 RASB1# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9 K3 C9 CASB1# K3 C9
18 CASB0# CAS VDDQ CAS VDDQ 18 CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB0# L3 D2 L3 D2 WEB1# L3 D2
18 WEB0# WE VDDQ WE VDDQ 18 WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 H2 QSB2 F3 H2 QSB4 F3 H2 QSB6 F3 H2
QSB1 DQSL VDDQ QSB0 DQSL VDDQ QSB5 DQSL VDDQ QSB7 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

C DQMB#3 DQMB#2 DQMB#4 DQMB#6 C

E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9 E7 DML VSS A9
DQMB#1 D3 B3 DQMB#0 D3 B3 DQMB#5 D3 B3 DQMB#7 D3 B3
DMU VSS DMU VSS DMU VSS DMU VSS
VSS E1 VSS E1 VSS E1 VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 J2 QSB#2 G3 J2 QSB#4 G3 J2 QSB#6 G3 J2
QSB#1 DQSL VSS QSB#0 DQSL VSS QSB#5 DQSL VSS QSB#7 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 VSS M1 VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9 DRAM_RST# T2 P9
18,19 DRAM_RST# RESET VSS RESET VSS RESET VSS RESET VSS
VSS T1 VSS T1 VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV89 L1 B9 RV90 L1 B9 RV91 L1 B9 RV92 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
2PCS@ L9 D8 2PCS@ L9 D8 4PCS@ L9 D8 4PCS@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2

2
VSSQ VSSQ VSSQ VSSQ
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
2PCS@ G1 G1 G1 G1
CLKB0 VSSQ VSSQ VSSQ VSSQ
1 2 VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
RV109 56_0402_1%
96-BALL 96-BALL 96-BALL 96-BALL
2PCS@ SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
CLKB0# 1 2 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
RV110 56_0402_1% 1 @ @ @ @

CV278 +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS +VRAM_1.5VS

0.1U_0402_16V4Z +VRAM_1.5VS +VRAM_1.5VS
2PCS@ 2
1

1
B B
1

1
RV93 RV95 RV97 RV98 4PCS@ RV99 RV100
4PCS@ 4.99K_0402_1% RV94 4.99K_0402_1% RV96 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
CLKB1 1 2 2PCS@ 4.99K_0402_1% 2PCS@ 4.99K_0402_1% 4PCS@ 4PCS@ 4PCS@
RV111 56_0402_1% 2PCS@ 2PCS@
2

2
+VREFC_B1 +VREFC_B2 +VREFC_B3 +VREFD_B3 +VREFC_B4 +VREFD_B4
2

4PCS@ +VREFD_B1 +VREFD_B2

1

1
CLKB1# 1 2 1 1 1 1 1 1
1

RV112 56_0402_1% 1 RV101 CV238 1 RV103 CV240 1 RV105 CV242 RV106 CV243 RV107 CV244 RV108 CV245
4.99K_0402_1% RV102 CV239 4.99K_0402_1% RV104 CV241 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
CV290 2PCS@ 0.1U_0402_16V4Z 4.99K_0402_1% 2PCS@ 0.1U_0402_16V4Z 4.99K_0402_1% 4PCS@ 0.1U_0402_16V4Z 4PCS@ 0.1U_0402_16V4Z 4PCS@ 0.1U_0402_16V4Z 4PCS@ 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2 2PCS@ 2PCS@ 0.1U_0402_16V4Z 2 2PCS@ 2PCS@ 0.1U_0402_16V4Z 2 4PCS@ 2 4PCS@ 2 4PCS@ 2 4PCS@
2

2
4PCS@ 2 2 2PCS@ 2 2PCS@
2

+VRAM_1.5VS
+VRAM_1.5VS
+VRAM_1.5VS +VRAM_1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CV271 CV259 CV260 CV261 CV272 CV273 CV262 CV275 CV263 CV264 CV265 CV276 CV266 CV267
1 1 1 1 1 1 1 1 1 1 1 1 1 1 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@ 4PCS@
CV246 CV247 CV248 CV249 CV250 CV251 CV252 CV268 CV269 CV254 CV255 CV256 CV257 CV258
2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2PCS@ 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z +VRAM_1.5VS

10U_0603_6.3V
1 1 1 1
A A
+VRAM_1.5VS
Co-layout with CV279
CV285 CV286 CV287 CV288
10U_0603_6.3V 4PCS@ 4PCS@ 4PCS@
10U_0603_6.3V 4PCS@ 2 2 2 2
1 1 1 1 +VRAM_1.5VS +VRAM_1.5VS 10U_0603_6.3V 10U_0603_6.3V

CV280 CV281 CV282 CV283 1 1

10U_0603_6.3V 2PCS@ 2PCS@ 2PCS@
2PCS@ 2 2
10U_0603_6.3V
2 2
10U_0603_6.3V
CV312
390U_2.5V_M_R10
+ + CV279
330U_X_2VM_R6M
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
@
2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 20 of 58
5 4 3 2 1
 5 4 3 2 1

CONFIGURATION STRAPS
STRAPS +3VS_DELAY
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
14 GPU_GPIO0 GPU_GPIO0 @ RV113
@RV113 2 1 10K_0402_5%
GPU by the system BIOS GPU by VBIOS 14 GPU_GPIO1 GPU_GPIO1 @RV114
@ RV114 2 1 10K_0402_5% STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS
14 GPU_GPIO2 GPU_GPIO2 RV115 2 1 10K_0402_5%
14 SOUT_GPIO8 SOUT_GPIO8 @RV116
@ RV116 2 1 10K_0402_5%
GPIO22 = 0 (BIOS_ROM_EN = 0) GPIO22 = 1 (BIOS_ROM_EN = 1) 14 SIN_GPIO9 SIN_GPIO9 @RV117
@ RV117 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING 0
14 ROMSE_GPIO22 @RV118
@ RV118 2 1 10K_0402_5%

GPIO[13:11] MEMORY SIZE GPIO[13:11] 14 GPU_GPIO11 GPU_GPIO11 RV119 2 1 10K_0402_5% TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0
14 GPU_GPIO12 GPU_GPIO12 @ RV120
@RV120 2 1 10K_0402_5%
D GPU_GPIO13 @RV121
@ RV121 D
128MB 2 1 10K_0402_5%
0 0 0 14 GPU_GPIO13
BIF_GEN2_EN_A GPIO2 PCIE GNE2 ENABLED 1
256MB
1 0 0
0 0 1
64MB
(M25P05A) HDMI@ RV122 10K_0402_5% BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
0 1 0 14,23 VGA_CRT_VSYNC
14,23 VGA_CRT_HSYNC HDMI@ RV123
2
2
1
1 10K_0402_5%
14 HSYNC_DAC2 @RV124
@ RV124 2 1 10K_0402_5%
14 VSYNC_DAC2 @RV125
@ RV125 2 1 10K_0402_5% BIF_VGA DIS GPIO9 VGA Controller ENABLED 0 (Enable)

BIOS_ROM_EN GPIO_22_ROMCSB Enable Extermal BIOS device 0

ROMIDCFG(2:0) GPIO[13:11] ROM Configurations 0 0 1

VIP_DEVICE_STRAP_ENA VSYNC_DAC2 IGNORE VIP DEVICE STRAPS 0

AUD[1] AUD[0]
AUD[1] HSYNC 0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected 11
AUD[0] VSYNC 1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

RSVD HSYNC_DAC2 0

RSVD GENERICC 0
C C

AMD RESERVED CONFIGURATION STRAPS

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

HSYNC_DAC2 GENERICC

PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
+1.8VS
GPIO_28_TDO GPIO21_BB_EN
1

RV128 RV129 RV130 RV131

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @
STRAPS PIN GPU VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 2,1,0
2

VRAM_ID0 14
B VRAM_ID1 14 B
VRAM_ID2 14 M92-M2 XT 512M 64Mx16 (x4) HYN H5TQ1G63BFR-12C SA000032400 000
VRAM_DEC 14
1

RV132 RV133 RV134 RV135 DDR3 M96-M2 1G 64Mx16 (x8) HYN H5TQ1G63BFR-12C SA000032400 001
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @
VRAM_DEC 1
2

M92-M2 XT 256M 64Mx16 (x2) HYN H5TQ1G63BFR-12C SA000032400 010

VRAM_ID[2:0] DVPDATA
(3,2,1)
M96-M2 1G 64Mx16 (x8) SAM K4W1G1646E-HC12 SA000035700 011

M92-M2 XT 512M 64Mx16 (x4) SAM K4W1G1646E-HC12 SA000035700 100

M92-M2 XT 256M 64Mx16 (x2) SAM K4W1G1646E-HC12 SA000035700 101

External VGA Thermal Sensor

+3VS

1
A CV291 A
0.1U_0402_16V4Z
2 UV12
1 VDD SCLK 8 EC_SMB_CK2 26,41

14 GPU_THERMAL_D+ 2 D+ SDATA 7 EC_SMB_DA2 26,41

1 2 3 6

CV292 2200P_0402_50V7K
D- ALERT# THERM#_VGA 14 Security Classification Compal Secret Data Compal Electronics, Inc.
4 THERM# GND 5 Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
14 GPU_THERMAL_D-
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
ADM1032ARMZ-2REEL_MSOP8 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 21 of 58
5 4 3 2 1
 A B C D E F G H

Clock Generator For SED +3VS_CK505

For SED

1
FBMH1608HM601-T_0603 For SED
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505 R110
R100 1 1 1 1 For SED 10K_0402_5%

1
FBMH1608HM601-T_0603

2
C209 C210 C211 C212 C251 +1.05VS 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z +1.05VS_CK505

2
R401 47P_0402_50V8J R101 1 1 1 1 CK_PWRGD

1
0_0603_5% 2 2 2 2 C252
10U_0805_10V4Z 0.1U_0402_16V4Z C219 C220 C221 C222 47P_0402_50V8J

3
1

2
2 2 2 2 Q35B
1 1
FBMH1608HM601-T_0603 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2N7002DW-T/R7_SOT363-6
+1.5VS 1 2 +1.5VS_CK505 5
@ R120 CLK_ENABLE# 53
1 1 1

4
For SED
C213 C214 C215
2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505
Silego Have Internal Pull-Up
+1.05VS_CK505
H_STP_CPU# 10K_0402_5% 2 1 R105
+1.05VS_CK505 +3VS_CK505

+1.5VS_CK505
SA00002XY00
U5
+3VS_CK505
1 VDD_USB_48 SCL 32 PM_SMBCLK 11,12,26,36
2 VSS_48M SDA 31 PM_SMBDATA 11,12,26,36
26 CLK_DOT 1 R145 2 0_0402_5% CLK_DOT_R 3 DOT_96 REF_0/CPU_SEL 30 CPU_SEL 1 2 CLK_14M_PCH 26
26 CLK_DOT# 1 R148 2 0_0402_5% CLK_DOT#_R 4 DOT_96# VDD_REF 29 33_0402_5% R102 10K_0402_5% 2 @ 1 R119 +1.05VS
5 28 CLK_XTAL_IN
VDD_27 XTAL_IN
14 27M_CLK 1 R391 2 33_0402_5% 27M_CLK_R 6 27MHZ XTAL_OUT 27 CLK_XTAL_OUT
14 27M_SSC 1 R143 2 33_0402_5% 27M_SSC_R 7 27MHZ_SS VSS_REF 26
1 2 CLK_48M_CR_R 8 25 CK_PWRGD CPU_SEL 10K_0402_5% 2 1 R106
40 CLK_48M_CR USB_48 CKPWRGD/PD#
R390 33_0402_5%
9 VSS_27M VDD_CPU 24 IDT Have Internal Pull-Down
2
26 CLK_SATA 1 R149 2 0_0402_5% CLK_SATA_R 10 SATA CPU_0 23 CLK_BCLK_R 1 R103 2 0_0402_5%
CLK_BCLK 26
2

26 CLK_SATA# 1 R150 2 0_0402_5% CLK_SATA#_R 11 SATA# CPU_0# 22 CLK_BCLK_R# 1 R104 2 0_0402_5%

CLK_BCLK# 26
12 VSS_SRC VSS_CPU 21
26 PCH_CLK_DMI 1 R151 2 0_0402_5% PCH_CLK_DMI_R 13 SRC_1 CPU_1 20 CPU_SEL CPU_0/0# CPU_1/1#
26 PCH_CLK_DMI# 1 R152 2 0_0402_5% PCH_CLK_DMI#_R 14 SRC_1# CPU_1# 19
15 VDD_SRC_IO VDD_CPU_IO 18
H_STP_CPU# 16 17 +1.5VS_CK505 CLK_XTAL_OUT 0 (Default) 133MHz 133MHz
CPU_STOP# VDD_SRC
Y1 Routing the
33 TGND CLK_XTAL_IN 1 2 trace at 1 100MHz 100MHz
RTM890N-631-GRT_QFN_32P _5X5 2
14.31818MHZ_20P_6X1430004201
2 least 10mil
C223 C224
22P_0402_50V8J 22P_0402_50V8J
1 1

1.5A
LCD/PANEL BD. Conn. +LCDVDD_R 2 L1
0_0805_5%
1 +LCD_VDD
+5VS_LVDS_CAM
1 1
0.1U_0402_16V4Z C226 C227
+LCD_VDD +3VS 0.1U_0402_16V4Z 4.7U_0805_10V4Z
1 2
C225 2 2
1

0_0603_5% W=20mils JLVDS

3 R107 +3VS R388 1 3
+5VS 2 2 2 1 1
150_0603_5% R108 W=60mils USB20_P11_R 4 3
4 3 VGA_TXCLK+ 14
100K_0402_5% USB20_N11_R 6 5
6 5 VGA_TXCLK- 14
8 7 INVT_PWM_R 1 2 INVT_PWM 41
6 2

8 7 R159 0_0402_5%
2 39 INT_MIC_R 10 10 9 9 DAC_BRIG 41
C228 12 11 INVT_PWM_R
14 VGA_TXOUT0+ 12 11
0.1U_0402_16V7K 14 13 1 @ 2
14 VGA_TXOUT0- 14 13 VGA_PWM 14
3

S
Q1A 16 15 R160 0_0402_5%
1 G 14 VGA_TXOUT1+ 16 15 VGA_TZCLK+ 14
2N7002DW-T/R7_SOT363-6 2 1 2 2 Q17 18 17
14 VGA_TXOUT1- 18 17 VGA_TZCLK- 14
R109 47K_0402_5% 1 AO3413_SOT23 20 19
14 VGA_TXOUT2+ 20 19
3

C229 D 22 21 VGA_EDID_CLK 14
14 VGA_TXOUT2-
1

0.01U_0402_25V7K +LCD_VDD 22 21
24 24 23 23 VGA_EDID_DATA 14 +3VS
2 W=60mils 14 VGA_TZOUT0+ 26 26 25 25
+LCDVDD_R
14 VGA_ENVDD 5 14 VGA_TZOUT0- 28 28 27 27
Q1B 30 29
14 VGA_TZOUT1+ 30 29
2N7002DW-T/R7_SOT363-6 1 32 31 1 R154 2 0_0402_5% 1 1
14 VGA_TZOUT1- LVDS_SEL 30
4

32 31
2

14 VGA_TZOUT2+ 34 34 33 33 +LCD_INV
C233 36 35 C231 C232
14 VGA_TZOUT2- 36 35 B+
R112 0.1U_0402_16V4Z 38 37 680P_0402_50V7K 0.1U_0402_16V4Z
10K_0402_5% 2 38 37 @ 2 2
41 BKOFF# 40 40 39 39 Rated Current MAX:3000mA
42 41 L2 2 1
1

GND GMD FBMA-L11-201209-221LMA30T_0805 For EMI request

1

ACES_87242-4001-09 1 1 1
Reserve for EMI request R113 @ C236
10K_0402_5% C234 C235 680P_0402_50V7K
R78 0_0402_5% 68P_0402_50V8J 0.1U_0402_25V6 @
2 2 2
1 2
2

L55 @
4 4

29 USB20_N11 1 2 USB20_N11_R
1 2

29 USB20_P11 4 3 USB20_P11_R
4 3
WCM-2012-900T_0805 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
R96 0_0402_5%
1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 22 of 58
A B C D E F G H
 A B C D E

CRT CONNECTOR

1
D3 D4 D5

+3VS
1 DAN217_SC59 DAN217_SC59 DAN217_SC59 1

3
@ @ @

L3
1 2 CRT_R_L
14 VGA_CRT_R
NBQ100505T-800Y_0402

L4
1 2 CRT_G_L
14 VGA_CRT_G
NBQ100505T-800Y_0402

L5
1 2 CRT_B_L
14 VGA_CRT_B

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
NBQ100505T-800Y_0402
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1
1

1
R138 R139 R140 C238 C239 C240 C241 C242 C243
2 2 2 2 2 2 +5VS
D6 +CRT_VCC_R +CRT_VCC
2

2
2 F1 30mil
1 1 2
3 RB491D_SOT23-3 1
1.1A_6V_MINISMDC110F-2
If=1A C237
@ 0.1U_0402_16V4Z
2 2 2

+CRT_VCC

1 2 2 1 JCRT
C244 0.1U_0402_16V4Z R141 10K_0402_5% 6 6
5
1

11 11
CRT_R_L 1
P
OE#

D_CRT_HSYNC HSYNC 1
14,21 VGA_CRT_HSYNC 2 A Y 4 1 2 7 7
L6 10_0402_5% CRT_DDC_DAT 12 12
G

U6 CRT_G_L 2
SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC VSYNC 2
1 2 8
3

L7 10_0402_5% HSYNC 8
13 13

10P_0402_50V8J

10P_0402_50V8J
CRT_B_L 3
+CRT_VCC 3
1 1 +CRT_VCC 9 9
VSYNC 14 16
C245 C246 14 G
4 4 G 17
5
1

@ @ 10
2 2 CRT_DDC_CLK 10
15
P
OE#

15
14,21 VGA_CRT_VSYNC 2 A Y 4 5 5
G

U7 ALLTO_C10532-11505-L_15P-T
SN74AHCT1G125GW_SOT353-5 @
3

3 3

+3VS
1

R144 R142 +CRT_VCC

0_0402_5% 0_0402_5%
2

R146 R147
4.7K_0402_5% 4.7K_0402_5%
2

Q2A
1

14 VGA_CRT_DATA 1 6 CRT_DDC_DAT
5

Q2B 2N7002DW-T/R7_SOT363-6

14 VGA_CRT_CLK 4 3 CRT_DDC_CLK
1 1
1 1 2N7002DW-T/R7_SOT363-6
C249 C250
C247 C248 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
Schematic, LA5322P M/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 23 of 58
A B C D E
 5 4 3 2 1

+5VS
D D
HDMI_HPD
2
C264 2

2
HDMI@ 2 1 +3VS R186 C265

1
0.1U_0402_16V4Z U9 R172 HDMI@ 100K_0402_5% 0.1U_0402_16V4Z
1 2.2K_0402_5% HDMI@ HDMI@

OE#
PMEG2010AEH_SOD123 HDMI@ F2 HDMI@ 1
2 A Y 4 VGA_HDMI_HPD 14,30
+5VS 2 1 2 1 +HDMI_5V_OUT

1
G

1
D53 1.1A_6V_MINISMDC110F-2 1
C259 HDMI@

3
HDMI@ R177
0.1U_0402_16V4Z 74AHCT1G125GW_SOT353-5 100K_0402_5%
2

2
VGA_DVI_TXC- 1 2 R157 HDMI_R_CK- +HDMI_5V_OUT
@ 0_0402_5%
C L8 1 2 +3VS C
1 2 R155 0_0402_5%
1 2

1
HDMI@
R185 R184
4 3 2.2K_0402_5% 2.2K_0402_5%
4 3 HDMI@ HDMI@

2
CV293 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC- HDMI@ OCE2012120YZF_0805 VGA_HDMI_CLK 14
14 VGA_HDMI_CLK-

2
CV297 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0- VGA_DVI_TXC+ 2 R173 HDMI_R_CK+

G
14 VGA_HDMI_TX0- 1 2 1
CV298 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1- @ 0_0402_5%
14 VGA_HDMI_TX1-
CV300 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2- HDMI_SCLK 1 3
14 VGA_HDMI_TX2-

2
Q19
VGA_DVI_TXD0+ 2 R175 HDMI_R_D0+ Q18 BSH111_SOT23-3

G
1
CV296 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ @ 0_0402_5% BSH111_SOT23-3 HDMI@
14 VGA_HDMI_CLK+
CV294 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ L9 HDMI_SDATA HDMI@ 1 3 VGA_HDMI_DATA 14
14 VGA_HDMI_TX0+
CV299 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ 1 2
14 VGA_HDMI_TX1+ 1 2
CV295 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+

S
14 VGA_HDMI_TX2+ 1 2

4 4 3 3
HDMI@ OCE2012120YZF_0805
VGA_DVI_TXD0- 1 2 R180 HDMI_R_D0-
@ 0_0402_5%

VGA_DVI_TXD1- 1 2 R182 HDMI_R_D1-

2 HDMI@ 1 HDMI_R_CK+ @ 0_0402_5%
499_0402_1% R195 L10
2 HDMI@ 1 HDMI_R_CK- 1 1 2 2
B 499_0402_1% R197 B

2 HDMI@ 1 HDMI_R_D1-
499_0402_1% R198 4 4 3 3
HDMI Connector
2 HDMI@ 1 HDMI_R_D1+
499_0402_1% R202 HDMI@ OCE2012120YZF_0805 JHDMI
2 HDMI@ 1 HDMI_R_D0+ VGA_DVI_TXD1+ 1 2 R183 HDMI_R_D1+ HDMI_HPD 19 HP_DET
499_0402_1% R201 @ 0_0402_5% +HDMI_5V_OUT 18 +5V
2 HDMI@ 1 HDMI_R_D0- 17 DDC/CEC_GND
499_0402_1% R203 HDMI_SDATA 16 SDA
2 HDMI@ 1 HDMI_R_D2- VGA_DVI_TXD2+ 1 2 R187 HDMI_R_D2+ HDMI_SCLK 15 SCL
499_0402_1% R205 @ 0_0402_5% 14 Reserved
2 HDMI@ 1 HDMI_R_D2+ L11 13 CEC
499_0402_1% R206 1 2 HDMI_R_CK- 12 20
1 2 CK- GND
1

D
11 CK_shield GND 21
Q24 2 +5VS HDMI_R_CK+ 10 22
2N7002_SOT23-3 G HDMI_R_D0- CK+ GND
4 4 3 3 9 D0- GND 23
HDMI@ S 8
3

@ 1 HDMI@ OCE2012120YZF_0805 HDMI_R_D0+ D0_shield

2 7 D0+
100K_0402_5% R207 VGA_DVI_TXD2- 1 2 R188 HDMI_R_D2- HDMI_R_D1- 6
@ 0_0402_5% D1-
5 D1_shield
HDMI_R_D1+ 4
HDMI_R_D2- D1+
3 D2-
2 D2_shield
HDMI_R_D2+ 1 D2+
@ TYCO_1939864-1_19P

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 24 of 58
5 4 3 2 1
 5 4 3 2 1

C287
CMOS Setting, near DDR Door 15P_0402_50V8J
JCMOS 2 1
+RTCVCC 1 2PCH_RTCRST# 1 2

10M_0402_5%
R282 20K_0402_1% Y3

1
1 2 3 NC OSC 4

R283
C288 1U_0402_6.3V4Z
iME Setting. J2
2 NC OSC 1 U11A
1 2PCH_SRTCRST# 1 2 32.768KHZ_12.5PF_Q13MC14610002

2
R284 20K_0402_1% PCH_RTCX1 B13 D33
RTCX1 FWH0 / LAD0 LPC_AD0 41,42
1 2 2 1 PCH_RTCX2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 41,42
C289 1U_0402_6.3V4Z C290 15P_0402_50V8J C32
FWH2 / LAD2 LPC_AD2 41,42
D
FWH3 / LAD3 A32 LPC_AD3 41,42 D
PCH_RTCRST# C14 RTCRST#
FWH4 / LFRAME# C34 LPC_FRAME# 41,42
+RTCVCC PCH_SRTCRST# D17 SRTCRST#
A34 1 2

RTC

LPC
LDRQ0# +3VS
Integrated SUS 1.05V VRM Enable 1 2 SM_INTRUDER# A16 F34 R286 10K_0402_5%
R285 1M_0402_5% INTRUDER# LDRQ1# / GPIO23
High - Enable Internal VRs 1 2 PCH_INTVRMEN A14 AB9 SERIRQ
INTVRMEN SERIRQ SERIRQ 41,42
PCH_INTVRMEN (must be always pulled high) R275 330K_0402_5%

AZ_BITCLK A30 HDA_BCLK

SATA0RXN AK7
AZ_SYNC D29 AK6
HDA_SYNC HDA_SYNC SATA0RXP
AK11
PCH_SPKR SATA0TXN
This signal has a weak internal pull down. 28,38 PCH_SPKR P1 SPKR SATA0TXP AK9
H=>On Die PLL is supplied by 1.5V
AZ_RST#
*L=>On Die PLL is supplied by 1.8V C30 HDA_RST#
SATA1RXN AH6 SATA_PRX_C_DTX_N1 34
SATA1RXP AH5 SATA_PRX_C_DTX_P1 34
HDA_SDO 38 AZ_SDIN0_HD G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 34 1ST HDD
SATA1TXP AH8 SATA_PTX_DRX_P1 34
This signal has a weak internal pull down. 35 AZ_SDIN1_MD F30 HDA_SDIN1
This signal can't PU SATA2RXN AF11
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
Flash Descriptor Security Overide Desktop Only
SATA3RXN AH3
C Low = Enabled AZ_SDOUT B29 AH1 C
HDA_SDO SATA3RXP
HDA_DOCK_EN# High = Disabled * SATA3TXN AF3
SATA3TXP AF1
41 PWRME_CTRL H32

SATA
HDA_DOCK_EN# / GPIO33
SATA4RXN AD9 SATA_PRX_C_DTX_N4 34

2
J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_PRX_C_DTX_P4 34
35 AZ_BITCLK_MD R287 1 MDC@ 2 33_0402_5% R118 AD6 SATA ODD
SATA4TXN SATA_PTX_DRX_N4 34
38 AZ_BITCLK_HD R288 1 2 33_0402_5% AZ_BITCLK 1K_0402_5% AD5
SATA4TXP SATA_PTX_DRX_P4 34
@
35 AZ_SYNC_MD R289 1 MDC@ 2 33_0402_5% PCH_JTAG_TCK M3 AD3 SATA_PRX_C_DTX_N5 34
1

R290 1 JTAG_TCK SATA5RXN

38 AZ_SYNC_HD 2 33_0402_5% AZ_SYNC
SATA5RXP AD1 SATA_PRX_C_DTX_P5 34
PCH_JTAG_TMS K3 AB3 eSATA
JTAG_TMS SATA5TXN SATA_PTX_DRX_N5 34
35 AZ_RST_MD# R291 1 MDC@ 2 33_0402_5% AB1
SATA5TXP SATA_PTX_DRX_P5 34
38 AZ_RST_HD# R292 1 2 33_0402_5% AZ_RST# PCH_JTAG_TDI K1 JTAG_TDI

JTAG
R293 1 MDC@ 2 33_0402_5% PCH_JTAG_TDO J2 AF16 +3VS
35 AZ_SDOUT_MD JTAG_TDO SATAICOMPO
38 AZ_SDOUT_HD R294 1 2 33_0402_5% AZ_SDOUT
PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2 PCH_GPIO19 R306 1 2 10K_0402_5%
TRST# SATAICOMPI +1.05VS
R295 37.4_0402_1%
SATA_LED# R301 2 1 10K_0402_5%

PCH_SPI_CLK BA2 SPK_SEL R303 1 2 10K_0402_5%

SPI_CLK
PCH_SPI_CS0# AV3 SPI_CS0#
ITPM Enabled Internal: Pull down 20k AY3 T3 SATA_LED#
+3VS SPI_CS1# SATALED# SATA_LED# 43

High = Enabled
SPI_MOSI 2 @ 1PCH_SPI_MOSI AY1 Y9 SPK_SEL
B Low = Disabled (Default) R273 1K_0402_5% SPI_MOSI SATA0GP / GPIO21 SPK_SEL 38 B

SPI
PCH_SPI_MISO AV1 V1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19

IBEXPEAK-M QV20 A0_FCBGA1071

HM55R3@
+3VALW +3VALW +3VALW +3VALW
1

@ @ @ +3VS
R386 R363 @ R643
200_0402_5% 200_0402_5% R536 20K_0402_5% 4MB
200_0402_5% +RTCBATT
1
2

1
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST# U13
C293 8 4 for EMI request
VCC VSS
1

@ @ @ 0.1U_0402_16V4Z D13
R355 R535 @ R364 2 PCH_SPI_CLK BAS40-04_SOT23-3
3 W
100_0402_5% 100_0402_5% R537 10K_0402_5% +RTCVCC

1
100_0402_5% 7

2
HOLD R385
+CHGRTC
2

PCH_SPI_CS0# 1 10_0402_5% 1
S
PCH_SPI_CLK 6 C291

2
C 0.1U_0402_16V4Z
1 2
PCH_SPI_MOSI 5 2 PCH_SPI_MISO C86
D Q 33P_0402_50V8J
1 2 PCH_JTAG_TCK MX25L3205DM2I-12G SO8
R156 51_0402_5% 2
A A
06/01 change R156 from 4.7K to 51 ohm
PCH JTAG Enable PCH JTAG Disable (Default)
PCH Pin RefDes ES1 ES2 ES1 ES2
PCH_JTAG_TDO R358 No Install 200ohm No Install No Install
R535 No Install 100ohm No Install No Install
PCH_JTAG_TMS R355 200ohm 200ohm No Install No Install Security Classification Compal Secret Data Compal Electronics, Inc.
R354 100ohm 100ohm No Install No Install 2009/01/23 2010/01/23 Title
PCH_JTAG_TDI R536 200ohm 200ohm 20Kohm No Install Issued Date Deciphered Date
R537 100ohm 100ohm 10Kohm No Install
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
PCH_JTAG_TCK R156 51ohm 51ohm 51ohm 51ohm Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCH_JTAG_RST# R643 20Kohm 20Kohm No Install No Install B D
R353 10Kohm 10Kohm No Install No Install
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 25 of 58
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VALW 2 R229 1 2.2K_0402_5%
2 R230 1 2.2K_0402_5% R231 4.7K_0402_5%

5
Q3B R232 4.7K_0402_5%

PCH_SMBDATA 3 4 PM_SMBDATA 11,12,22,36

2
Q3A 2N7002DW-T/R7_SOT363-6

PCH_SMBCLK 6 1 PM_SMBCLK 11,12,22,36

2N7002DW-T/R7_SOT363-6

D U11B D

BG30 B9 EC_LID_OUT# EC_LID_OUT# 41

36 PCIE_PRX_NEWTX_N1 PERN1 SMBALERT# / GPIO11
For NewCard 36 PCIE_PRX_NEWTX_P1
C269 2
BJ30 PERP1
36 PCIE_PTX_C_NEWRX_N1 1 0.1U_0402_16V7K NEW@ PCIE_PTX_NEWRX_N1 BF29 PETN1 SMBCLK H14 PCH_SMBCLK
36 PCIE_PTX_C_NEWRX_P1 C270 2 1 0.1U_0402_16V7K NEW@ PCIE_PTX_NEWRX_P1 BH29 PETP1 PCH_SMBDATA
SMBDATA C8
36 PCIE_PRX_WLANTX_N2 AW30 PERN2
For WLAN 36 PCIE_PRX_WLANTX_P2
C274 2
BA30 PERP2 +3VS
36 PCIE_PTX_C_WLANRX_N2 1 0.1U_0402_16V7K WLAN@ PCIE_PTX_WLANRX_N2 BC30
PETN2 SML0ALERT# / GPIO60 J14 PCH_GPIO60 +3VALW 2 R233 1 2.2K_0402_5%
36 PCIE_PTX_C_WLANRX_P2 C275 2 1 0.1U_0402_16V7K WLAN@ PCIE_PTX_WLANRX_P2 BD30 2 R234 1 2.2K_0402_5% R235 @ 4.7K_0402_5%
PETP2

5
C6 PCH_SMLCLK0 Q4B R236 @ 4.7K_0402_5%
SML0CLK
AU30

SMBus
37 PCIE_PRX_C_LANTX_N3 PERN3
For LAN AT30 G8 PCH_SMLDATA0 PCH_SMLDATA1 3 4
37 PCIE_PRX_C_LANTX_P3 PERP3 SML0DATA EC_SMB_DA2 21,41
37 PCIE_PTX_C_LANRX_N3 C276 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N3 AU32
PETN3

2
37 PCIE_PTX_C_LANRX_P3 C273 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P3 AV32 Q4A 2N7002DW-T/R7_SOT363-6
PETP3 PCH_GPIO74
SML1ALERT# / GPIO74 M14
BA32 PCH_SMLCLK1 6 1
PERN4 EC_SMB_CK2 21,41
BB32 E10 PCH_SMLCLK1
PERP4 SML1CLK / GPIO58 2N7002DW-T/R7_SOT363-6
BD32 PETN4
BE32 G12 PCH_SMLDATA1 +3VALW
PETP4 SML1DATA / GPIO75

PCI-E*
BF33 PCH_SMLCLK0 4.7K_0402_5% 2 1 R237
PERN5 PCH_SMLDATA0 4.7K_0402_5% R238
BH33 PERP5 CL_CLK1 T13 2 1

Controller
BG32 PCH_GPIO60 10K_0402_5% 2 1 R239
PETN5 PCH_GPIO74 10K_0402_5% R240
BJ32 PETP5 CL_DATA1 T11 2 1
EC_LID_OUT# 10K_0402_5% 2 1 R241

Link
BA34 T9 1 @ 2 +3VALW
C
PERN6 CL_RST1# R260 10K_0402_5% C
AW34 PERP6
BC34 PETN6
BD34 PETP6
H1 CLKREQ_PEG# 1 2
PEG_A_CLKRQ# / GPIO47 R243 10K_0402_5%
AT34 PERN7
AU34 PERP7
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PCIE_VGA# 13
AV36 PETP7 CLKOUT_PEG_A_P AD45 CLK_PCIE_VGA 13 VGA
NC BG34 AN4 CLK_PEG# 5
PERN8 CLKOUT_DMI_N

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PEG 5
BG36 PETN8
BJ36 PETP8
NEW@ AT1
R44 0_0402_5% CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
1 2 CLK_NEW#_R AK48
36 CLK_NEW# CLKOUT_PCIE0N
NewCard 1 2 CLK_NEW_R AK47
36 CLK_NEW CLKOUT_PCIE0P

From CLK BUFFER

R45 0_0402_5% AW24 PCH_CLK_DMI# 22
NEW@ CLKREQ_NEW# CLKIN_DMI_N
36 CLKREQ_NEW# P9 PCIECLKRQ0# / GPIO73 CLKIN_DMI_P BA24 PCH_CLK_DMI 22
R46 0_0402_5%
+3VS 1 2 CLK_WLAN#_R AM43 AP3
36 CLK_WLAN# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BCLK# 22
WLAN 1 2 CLK_WLAN_R AM45 AP1 CLK_BCLK 22 FROM CLK GEN FOR: 133/100/96/14.318 MHZ
36 CLK_WLAN CLKOUT_PCIE1P CLKIN_BCLK_P
1 2 CLKREQ_LAN# R47 0_0402_5%
10K_0402_5% R246 CLKREQ_WLAN# U4
36 CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
CLKIN_DOT_96N F18 CLK_DOT# 22
1 2 CLKREQ_WLAN# R48 0_0402_5% E18 CLK_DOT 22
10K_0402_5% R248 CLK_LAN#_R CLKIN_DOT_96P
37 CLK_LAN# 1 2 AM47 CLKOUT_PCIE2N
LAN 1 2 CLK_LAN_R AM48
B 37 CLK_LAN CLKOUT_PCIE2P B
R49 0_0402_5% AH13 CLK_SATA# 22
CLKREQ_LAN# CLKIN_SATA_N / CKSSCD_N @ R247 1M_0402_5%
37 CLKREQ_LAN# N4 PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P AH12 CLK_SATA 22
+3VALW 2 1

1 2 CLKREQ_NEW# AH42 P41 CLK_14M_PCH 22 Y2 @

10K_0402_5% R244 CLKOUT_PCIE3N REFCLK14IN PCH_X1 PCH_X2
AH41 CLKOUT_PCIE3P 2 1

1 2 PCH_GPIO25 PCH_GPIO25 A8 J42 @ 1 25MHz_20pF_6X250000171 @

PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCILOOP 29
10K_0402_5% R245 C277 C278

1 2 PCH_GPIO26 AM51 AH51 PCH_X1 27P_0402_50V8J 27P_0402_50V8J

10K_0402_5% R249 CLKOUT_PCIE4N XTAL25_IN PCH_X2 2 2
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53

1 2 PCH_GPIO44 PCH_GPIO26 M9 AF38 XCLK_RCOMP 1 2 +1.05VS

10K_0402_5% R250 PCIECLKRQ4# / GPIO26 XCLK_RCOMP R252 90.9_0402_1%

PCH_GPIO56
1
10K_0402_5% R251
2 AJ50
AJ52
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 T45
C277
Note: Stuff 0 ohm if
CLKOUT_PCIE5P 0_0402_5% 25MHz crystal un-stuff
PCH_GPIO44 H6 P43
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42

AK51 CLKOUT_PEG_B_P
PCH_GPIO56 P13 N50
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67

IBEXPEAK-M QV20 A0_FCBGA1071 @

A A
HM55R3@ CLK_14M_PCH 1 @ 2 2 1
R70 100_0402_5%
C206 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 26 of 58
5 4 3 2 1
 5 4 3 2 1

D D

U11C
FDI_RXN0 BA18
6 DMI_CTX_PRX_N0 BC24 DMI0RXN FDI_RXN1 BH17
6 DMI_CTX_PRX_N1 BJ22 DMI1RXN FDI_RXN2 BD16
6 DMI_CTX_PRX_N2 AW20 DMI2RXN FDI_RXN3 BJ16
6 DMI_CTX_PRX_N3 BJ20 DMI3RXN FDI_RXN4 BA16
FDI_RXN5 BE14
6 DMI_CTX_PRX_P0 BD24 DMI0RXP FDI_RXN6 BA14
6 DMI_CTX_PRX_P1 BG22 DMI1RXP FDI_RXN7 BC12
6 DMI_CTX_PRX_P2 BA20 DMI2RXP
6 DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18
FDI_RXP1 BF17
6 DMI_PTX_CRX_N0 BE22 DMI0TXN FDI_RXP2 BC16
6 DMI_PTX_CRX_N1 BF21 DMI1TXN FDI_RXP3 BG16
+3VALW BD20 AW16
6 DMI_PTX_CRX_N2 DMI2TXN FDI_RXP4
6 DMI_PTX_CRX_N3 BE18 DMI3TXN FDI_RXP5 BD14
FDI_RXP6 BB14
1 2 PCH_SUSPWRDN BD22 BD12
6 DMI_PTX_CRX_P0 DMI0TXP FDI_RXP7
R316 10K_0402_5% BH21
6 DMI_PTX_CRX_P1 DMI1TXP
1 2 PCH_LOW_BAT# BC20
6 DMI_PTX_CRX_P2 DMI2TXP
R318 10K_0402_5% BD18 BJ14 1 2
6 DMI_PTX_CRX_P3 DMI3TXP FDI_INT
1 2 IBEX_RI# R689 1K_0402_5%

DMI
FDI
R320 10K_0402_5% BF13 1 2
DMI_COMP FDI_FSYNC0 R690 1K_0402_5%
+1.05VS 1 2 BH25 DMI_ZCOMP
R311 49.9_0402_1% BH13
PM_PWROK FDI_FSYNC1
2 1 BF25 DMI_IRCOMP
R329 10K_0402_5% BJ12
C 2 1 PWROK Close to PCH FDI_LSYNC0 C
R322 10K_0402_5% BG14
LAN_RST# FDI_LSYNC1
2 1
R323 10K_0402_5%

2 @ 1
0_0402_5% R256

+3VS XDP_DBRESET# T6 J12 EC_SWI# EC_SWI# 2 1

5 XDP_DBRESET# SYS_RESET# WAKE# EC_SWI# 36,37 +3VALW
0.1U_0402_16V4Z R313 10K_0402_5%
1 2
C230 M6 Y1 PM_CLKRUN# 2 1 +3VS
41,53 VGATE SYS_PWROK CLKRUN# / GPIO32
5

U12 R319 8.2K_0402_5%

1
P

41 PM_PWROK IN1

System Power Management

4 PWROK B17
VGATE O PWROK
2 IN2
G

1 2 K5 P8 SUS_STAT# PADT38
PADT38
3

SN74AHC1G08DCKR_SC70-5 R321 0_0402_5% MEPWROK SUS_STAT# / GPIO61

LAN_RST# A10 F3 SUS_CLK PADT39

PADT39
LAN_RST# SUSCLK / GPIO62

5 DRAMPWROK D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# 41

PCH_RSMRST# C16 H7
RSMRST# SLP_S4# PM_SLP_S4# 41
B B
PCH_SUSPWRDN M1 P12
41 PCH_SUSPWRDN SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# 41
5 PM_PBTN_OUT# 1 @ 2
R330 0_0402_5%
41 PBTN_OUT# P5 PWRBTN# SLP_M# K8

+3VALW 1 2 PCH_ACIN P7 N2
R324 330K_0402_5% ACPRESENT / GPIO31 TP23

D26 PCH_LOW_BAT# A6 BJ10

BATLOW# / GPIO72 PMSYNCH PMSYNCH 5
41,43,45 ACIN 1 2

CH751H-40PT_SOD323-2 IBEX_RI# F14 F6

RI# SLP_LAN# / GPIO29

IBEXPEAK-M QV20 A0_FCBGA1071

+3VALW HM55R3@

1 2
R691 1K_0402_5% 0_0402_5% @1 2 R325

Q26 1 PCH_RSMRST#
C

41 EC_RSMRST# 3
E

2 1
MMBT3906_SOT23-3 R326
10K_0402_5%
B
2

+3VALW 2 1
R327
A A
1

4.7K_0402_5%
D15A D15B
BAV99DW-7_SOT363 BAV99DW-7_SOT363

Security Classification Compal Secret Data Compal Electronics, Inc.

6

1 2
RSMRST# circuit R328
2.2K_0402_5%
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 27 of 58
5 4 3 2 1
 5 4 3 2 1

U11D
T48 L_BKLTEN SDVO_TVCLKINN BJ46
T47 L_VDD_EN SDVO_TVCLKINP BG46

Y48 L_BKLTCTL SDVO_STALLN BJ48

SDVO_STALLP BG48
AB48 L_DDC_CLK
Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
AB46 L_CTRL_CLK
V48 L_CTRL_DATA
AP39 LVD_IBG SDVO_CTRLCLK T51
D AP41 LVD_VBG SDVO_CTRLDATA T53 D

AT43 LVD_VREFH
AT42 LVD_VREFL DDPB_AUXN BG44
DDPB_AUXP BJ44
DDPB_HPD AU38

LVDS
AV53 LVDSA_CLK#
AV51 LVDSA_CLK DDPB_0N BD42
DDPB_0P BC42
BB47 LVDSA_DATA#0 DDPB_1N BJ42

Digital Display Interface

BA52 LVDSA_DATA#1 DDPB_1P BG42
AY48 LVDSA_DATA#2 DDPB_2N BB40
AV47 LVDSA_DATA#3 DDPB_2P BA40
DDPB_3N AW38
BB48 LVDSA_DATA0 DDPB_3P BA38
BA50 LVDSA_DATA1
AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
DDPC_CTRLDATA AB49

AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
C AT48 BD38 C
LVDSB_DATA1 DDPC_2N
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

AA52 CRT_BLUE DDPD_CTRLCLK U50

AB53 CRT_GREEN DDPD_CTRLDATA U52
AD53 CRT_RED

DDPD_AUXN BC46
V51 CRT_DDC_CLK DDPD_AUXP BD46
V53 CRT_DDC_DATA DDPD_HPD AT38

DDPD_0N BJ40
Y53 CRT_HSYNC DDPD_0P BG40
Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
2 R266 1CRT_IREF AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
1K_0402_1% BD36
DDPD_3P

PCH Strap Pin IBEXPEAK-M QV20 A0_FCBGA1071

HM55R3@

Internal: Pull down 20k

+3VS
+1.8VS_PCH_NAND During Reset: Low Danbury Technology Enabled
Internal: Pull down 20k NO REBOOT Strap
B Check list: 8.2k PU Initial: Low High = Enabled B
Check list: 10k PU During Reset: HZ
PCH_SPKR Low= Disable NV_ALE Low = Disabled (Default)
Initial: Low 2 @ 1 NV_ALE
@ PCH_SPKR
High= Enable R267 1K_0402_5%
NV_ALE 29
1 2 PCH_SPKR 25,38
R269 1K_0402_5%
Internal: Pull up 20k 2 @ 1 NV_CLE NV_CLE 29
Boot BIOS Strap R268 1K_0402_5% DMI Termination Voltage
During Reset: High
Initial: High PCI_GNT#1 PCI_GNT#0 Boot BIOS Loaction Internal: Pull down 20k Low= Set to Vss (Default)
During Reset: Low NV_CLE High= Set to Vcc
1K_0402_5% 2 @ 1 R270 PCI_GNT#0
PCI_GNT#0 29 0 0 LPC (Default) Initial: Low
1K_0402_5% 2 @ 1 R271 PCI_GNT#1
PCI_GNT#1 29 0 1 Reserved (NAND)
Internal: Pull up 20k 1 0 PCI
During Reset: High
Check list: 4.7k PD Initial: High 1 1 SPI
2 @ 1 PCI_GNT#3
PCI_GNT#3 29
R272 1K_0402_5% A16 Swap Override Strap
Internal: Pull up 20k
During Reset: High Low= A16 swap override Enable
Initial: High PCI_GNT#3 High= A16 swap override Disable

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 28 of 58
5 4 3 2 1
 5 4 3 2 1

U11E
H40 AD0 NV_CE#0 AY9
N34 AD1 NV_CE#1 BD1
D C44 AD2 NV_CE#2 AP15 D
A38 AD3 NV_CE#3 BD8
C36 AD4
J34 AD5 NV_DQS0 AV9
A40 AD6 NV_DQS1 BG8
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6
C40 AD11 NV_DQ3 / NV_IO3 AT9
M48 AD12 NV_DQ4 / NV_IO4 BB1
M45 AD13 NV_DQ5 / NV_IO5 AV6
F53 AD14 NV_DQ6 / NV_IO6 BB3
M40 AD15 NV_DQ7 / NV_IO7 BA4

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4
J36 AD17 NV_DQ9 / NV_IO9 BB6
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 AD19 NV_DQ11 / NV_IO11 BB7
+3VS C42 BC8
RP1 AD20 NV_DQ12 / NV_IO12
K46 AD21 NV_DQ13 / NV_IO13 BJ8
1 8 PCI_REQ#1 M51 BJ6
PCI_REQ#2 AD22 NV_DQ14 / NV_IO14
2 7 J52 AD23 NV_DQ15 / NV_IO15 BG6
3 6 PCI_PIRQD# K51
PCI_IRDY# AD24 NV_ALE @
4 5 L34 AD25 NV_ALE BD3 NV_ALE 28 1 2
F42 AY6 NV_CLE NV_CLE 28 R253 0_0402_5%
8.2K_0804_8P4R_5% AD26 NV_CLE
J40 AD27
G46 +3VS
RP2 AD28 @
F44 AD29 NV_RCOMP AU2 1 2
1 8 PCI_PIRQH# M47 R276 32.4_0402_1%
AD30

PCI
C 2 7 PCI_TRDY# H36 AV7 C
AD31 NV_RB#

5
3 6 PCI_FRAME# U8
4 5 PCI_PIRQA# J50 AY8 1 PLT_RST#

P
C/BE0# NV_WR#0_RE# IN1
G42 C/BE1# NV_WR#1_RE# AY5 5 BUF_PLT_RST# 4 O
8.2K_0804_8P4R_5% H47 2
C/BE2# IN2

G
G34 C/BE3# NV_WE#_CK0 AV11

1
RP3 BF5 SN74AHC1G08DCKR_SC70-5

3
PCI_STOP# PCI_PIRQA# NV_WE#_CK1
1 8 G38 PIRQA#
2 7 PCI_PIRQE# PCI_PIRQB# H51 R129
PCI_PIRQC# PCI_PIRQC# PIRQB# 100K_0402_5%
3 6 B37 PIRQC# USBP0N H18 USB20_N0 34
4 5 PCI_PIRQG# PCI_PIRQD# A44 J18 USB-RIGHT1 @
USB20_P0 34

2
PIRQD# USBP0P
USBP1N A18 USB20_N1 34
8.2K_0804_8P4R_5% PCI_REQ#0 F51 C18 USB-RIGHT2
REQ0# USBP1P USB20_P1 34
PCI_REQ#1 A46 N20
PCI_REQ#2 REQ1# / GPIO50 USBP2N
B45 REQ2# / GPIO52 USBP2P P20
PCI_REQ#3 M53 J20
REQ3# / GPIO54 USBP3N USB20_N3 34
USBP3P L20 USB20_P3 34 eSATA-USB
28 PCI_GNT#0 F48 GNT0# USBP4N F20
28 PCI_GNT#1 K45 GNT1# / GPIO51 USBP4P G20
GNT2#: Not pull low, internal pull up 20K F36 GNT2# / GPIO53 USBP5N A20 USB20_N5 35
28 PCI_GNT#3 H53 GNT3# / GPIO55 USBP5P C20 USB20_P5 35 BT
USBP6N M22
PCI_PIRQE# B41 N22
PCI_PIRQF# PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21
PCI_PIRQG# A36 D21
PCI_PIRQH# PIRQG# / GPIO4 USBP7P
A48 PIRQH# / GPIO5 USBP8N H22 USB20_N8 36
+3VS
USBP8P J22 USB20_P8 36 NewCard

USB
RP4 TP_PCI_RST# K6 E22
T37 PAD PCIRST# USBP9N
1 8 PCI_REQ#3 F22
B PCI_PIRQF# PCI_SERR# USBP9P B
2 7 E44 SERR# USBP10N A22 USB20_N10 40
3 6 PCI_PIRQB# PCI_PERR# E50 C22 Card reader(3 in 1)
PERR# USBP10P USB20_P10 40
4 5 PCI_REQ#0 G24
USBP11N USB20_N11 22
8.2K_0804_8P4R_5% PCI_IRDY# USBP11P H24 USB20_P11 22 Int. Camera
A42 IRDY# USBP12N L24 USB20_N12 36
PCI_DEVSEL#
H44 PAR USBP12P M24 USB20_P12 36 3G
F46 DEVSEL# USBP13N A24 USB20_N13 36
PCI_FRAME# C46 C24 WiMax(WLAN)
FRAME# USBP13P USB20_P13 36 +3VALW
+3VS PCI_PLOCK# D49
RP5 PLOCK#
USBRBIAS# B25
1 8 PCI_DEVSEL# PCI_STOP# D41
PCI_PERR# PCI_TRDY# STOP# USBBIAS USB_OC#5
2 7
PCI_SERR#
C48 TRDY# USBRBIAS D25 2
R278
1
22.6_0402_1%
Within 500 mils 2
10K_0402_5%
1
RN1
3 6
4 5 PCI_PLOCK# M7 USB_OC#6 2 1
PME# USB_OC#0 10K_0402_5% RN2
OC0# / GPIO59 N16 USB_OC#0 34,41
8.2K_0804_8P4R_5% D5 J16
5,13,36,37,41,42 PLT_RST# PLTRST# OC1# / GPIO40 RP6
F16 USB_OC#2
OC2# / GPIO41 USB_OC#3 USB_OC#0
N52 CLKOUT_PCI0 OC3# / GPIO42 L16 USB_OC#3 34,41 4 5
P53 E14 USB_OC#4 USB_OC#2 3 6
CLKOUT_PCI1 OC4# / GPIO43
2 1 CLK_SIO P46 CLKOUT_PCI2 OC5# / GPIO9 G16 USB_OC#5 USB_OC#3 2 7
42 CLK_PCI_DDR 22_0402_5% R280
2 1 CLK_EC P51 CLKOUT_PCI3 OC6# / GPIO10 F12 USB_OC#6 USB_OC#4 1 8
41 CLK_PCI_EC 22_0402_5% R281
26 CLK_PCILOOP 2 1 CLK_PCH P48 CLKOUT_PCI4 OC7# / GPIO14 T15 EXP_CPPE#
EXP_CPPE# 36
22_0402_5% R279 10K_0804_8P4R_5%

IBEXPEAK-M QV20 A0_FCBGA1071

HM55R3@
Change to 47 ohm?
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 29 of 58
5 4 3 2 1
 5 4 3 2 1

U11F

14,24 VGA_HDMI_HPD Y3 BMBUSY# / GPIO0 CLKOUT_PCIE6N AH45

AH46 +3VS
PCH_GPIO1 CLKOUT_PCIE6P KB_RST# @
D GPIO8 C38 TACH1 / GPIO1 2 1 +3VS D
Not pull down R209 10K_0402_5%
PCH_GPIO6 D37 TACH2 / GPIO6

1
Internal: Pull up 20k CLKOUT_PCIE7N AF48

MISC
EC_SCI# J32 AF47 R208
During Reset: High 41 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
10K_0402_5%
Initial: High EC_SMI# F10
41 EC_SMI# GPIO8

2
GPIO15 PCH_GPIO12 K9 U2 GATEA20
LAN_PHY_PWR_CTRL / GPIO12 A20GATE GATEA20 41
a Strong pull up may be needed
PCH_GPIO15 T7
for GPIO Functionality GPIO15
Internal: Pull down 20k PCH_GPIO16 AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
During Reset: Low PCH_GPIO17 F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK 5
Initial: Low
BT_DET# Y7 BG10 PCH_PECI 1 2
35 BT_DET# SCLOCK / GPIO22 PECI PECI 5

GPIO
R117 0_0402_5%
H10 T1 KB_RST#
GPIO24 RCIN# KB_RST# 41
On-Die PLL VR @ PCH_GPIO27
2 1 AB12 GPIO27 PROCPWRGD BE10 H_PWRGOOD 5

CPU
High = Enabled (Default) R274 1K_0402_5%
PCH_GPIO27 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 1 2
Low = Disabled GPIO28 THRMTRIP# R212 56_0402_1%
H_THERMTRIP# 5

35 BT_PWR# M11 STP_PCI# / GPIO34

35 BT_RST# V6 SATACLKREQ# / GPIO35

1 2 +VTT
PCH_GPIO36 AB7 BA22 R210 56_0402_1%
C
SATA2GP / GPIO36 TP1 C
PCH_GPIO37 AB13 AW22
SATA3GP / GPIO37 TP2
+3VS PCH_GPIO38 V3 BB22
SLOAD / GPIO38 TP3
1 2 PCH_GPIO1 PCH_GPIO39 P3 SDATAOUT0 / GPIO39 TP4 AY45
10K_0402_5% R214
1 2 BT_DET# LVDS_SEL H3 AY46
22 LVDS_SEL PCIECLKRQ6# / GPIO45 TP5
8.2K_0402_5% R215
1 2 PCH_GPIO36 5,11 RST_GATE
RST_GATE F1 PCIECLKRQ7# / GPIO46 TP6 AV43
10K_0402_5% R217
1 2 PCH_GPIO6 PCH_GPIO48 AB6 SDATAOUT1 / GPIO48 TP7 AV45
10K_0402_5% R218
1 2 PCH_GPIO17 41 THM_ALT#
THM_ALT# AA4 SATA5GP / GPIO49 TP8 AF13
10K_0402_5% R220
1 2 PCH_GPIO16 PCH_GPIO57 F8 GPIO57 TP9 M18
10K_0402_5% R221
1 2 PCH_GPIO37 TP10 N18
10K_0402_5% R254
1 2 PCH_GPIO38 A4 VSS_NCTF_1 TP11 AJ24
10K_0402_5% R255 A49

NCTF
VSS_NCTF_2

RSVD
1 2 THM_ALT# A5 VSS_NCTF_3 TP12 AK41
10K_0402_5% R259 A50
PCH_GPIO48 VSS_NCTF_4
1 2 A52 VSS_NCTF_5 TP13 AK42
10K_0402_5% R257 A53 VSS_NCTF_6
1 2 PCH_GPIO39 B2 VSS_NCTF_7 TP14 M32
10K_0402_5% R216 B4
EC_SCI# VSS_NCTF_8
1 2 B52 VSS_NCTF_9 TP15 N32
10K_0402_5% R224 B53
B VSS_NCTF_10 B
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53 VSS_NCTF_14
+3VALW BH1 H12
VSS_NCTF_15 TP18
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
1 2 EC_SMI# BH53
R225 10K_0402_5% VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
1 2 PCH_GPIO57 BJ2 VSS_NCTF_20
R226 10K_0402_5% BJ4 AB38
VSS_NCTF_21 NC_2
1 2 PCH_GPIO15 BJ49 VSS_NCTF_22
R227 1K_0402_5% BJ5 AB42
VSS_NCTF_23 NC_3
1 2 PCH_GPIO28 BJ50 VSS_NCTF_24
R242 10K_0402_5% BJ52 AB41
VSS_NCTF_25 NC_4
1 2 LVDS_SEL BJ53 VSS_NCTF_26
R222 10K_0402_5% D1 T39
VSS_NCTF_27 NC_5
1 2 RST_GATE 12/22: Modify for M96 and M96 Pro select D2 VSS_NCTF_28 Not pull low
M96PRO@ R223 10K_0402_5% D53 VSS_NCTF_29 internal pull up
1 2 PCH_GPIO12 E1 VSS_NCTF_30 INIT3_3V# P6
10K_0402_5% R219 E53 VSS_NCTF_31
TP24 C10 Internal: Pull up 20k
IBEXPEAK-M QV20 A0_FCBGA1071
During Reset: High
HM55R3@ Initial: High

1 @ 2 BT_RST#
10K_0402_5% R228
A A

1 @ 2 EC_SMI#
R258 1K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 30 of 58
5 4 3 2 1
 5 4 3 2 1

+1.05VS +3VS
U11G POWER +3VS_VCCADAC
L12
AB24 VCCCORE[1] VCCADAC[1] AE50 2 1
1 1 AB26 69mA 2 1 BLM18PG181SN1D_0603
C295 C294 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52
10U_0805_10V4Z 1U_0402_6.3V4Z AD26 C296 C297 C298
VCCCORE[4]

CRT
D AD28 AF53 0.01U_0402_25V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z D
2 2 VCCCORE[5] VSSA_DAC[1] 1 2
AF26 VCCCORE[6]

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30 VCCCORE[8] close to AE50
AF31 VCCCORE[9]
AH26 VCCCORE[10]
AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 VCCCORE[13] > 1mA VCCALVDS AH38
AJ30 VCCCORE[14]
AJ31 VCCCORE[15] VSSA_LVDS AH39

+1.05VS 1432mA
VCCTX_LVDS[1] AP43
59mA VCCTX_LVDS[2] AP45
AT46

LVDS
VCCTX_LVDS[3]
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
+3VS
BJ24 VCCAPLLEXP 40mA
VCC3_3[2] AB34

AN20 VCCIO[25] 375mA VCC3_3[3] AB35

AN22 2

HVCMOS
VCCIO[26] 0.1U_0402_16V4Z
AN23 VCCIO[27] VCC3_3[4] AD35
AN24 C303
VCCIO[28]
AN26 VCCIO[29] 1
AN28 VCCIO[30] close to AB34
BJ26 VCCIO[31]
C BJ28 C
VCCIO[32]
AT26 VCCIO[33]
AT28 VCCIO[34]
+1.05VS AU26 VCCIO[35] +PCH_VRM +PCH_VRM
AU28 VCCIO[36]
1 2 AV26 VCCIO[37]
C304 10U_0805_10V4Z AV28 196mA VCCVRM[2] AT24 +PCH_DMI_VRM 1 2
VCCIO[38] R333 0_0402_5% +1.5VS
1 2 AW26 VCCIO[39]
C305 1U_0402_6.3V4Z AW28 3062mA
VCCIO[40] +VTT

DMI
1 2 BA26 AT16 2 @ 1
C306 1U_0402_6.3V4Z VCCIO[41] VCCDMI[1] R334 0_0402_5%
BA28 VCCIO[42] 61mA +PCH_VCCDMI +1.8VS
1 2 BB26 VCCIO[43] VCCDMI[2] AU16 1 2
C307 1U_0402_6.3V4Z BB28 1 R335 0_0603_5%
VCCIO[44] C309
1 2 BC26 VCCIO[45] 2 1

PCI E*
C308 1U_0402_6.3V4Z BC28 1U_0402_6.3V4Z R336 0_0402_5%
VCCIO[46]
BD26 VCCIO[47] 2
BD28 VCCIO[48] close to AT16
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 AK19 +1.8VS_PCH_NAND +1.8VS
VCCIO[52] VCCPNAND[4]
BH27 VCCIO[53] VCCPNAND[5] AK15
156mA VCCPNAND[6] AK13 1
R338
2
0_0603_5%
AN30 VCCIO[54] VCCPNAND[7] AM12 2
+3VS

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
+3VS AM15 C311
VCCPNAND[9] 0.1U_0402_16V4Z @
1 2
1 R339 0_0603_5%
2 1 AN35 VCC3_3[1] 375mA close to Ak13
C310 0.1U_0402_16V4Z
B B

+PCH_VRM 2 1 +PCH_FDI_VRM AT22

R340 0_0402_5% VCCVRM[1] +3VS
BJ18 VCCFDIPLL 37mA VCCME3_3[1] AM8
VCCME3_3[2] AM9
FDI

+1.05VS AM23 VCCIO[1] 85mA VCCME3_3[3] AP11 2

VCCME3_3[4] AP9
C313 0.1U_0402_16V4Z
1
close to AM8
IBEXPEAK-M QV20 A0_FCBGA1071
HM55R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 31 of 58
5 4 3 2 1
 5 4 3 2 1

U11J POWER +1.05VS

AP51 VCCACLK[1] VCCIO[5] V24

52mA VCCIO[6] V26 1
C316
AP53 VCCACLK[2] 3062mA VCCIO[7] Y24
VCCIO[8] Y26
1U_0402_6.3V4Z
2
AF23 VCCLAN[1] VCCSUS3_3[1] V28
VCCSUS3_3[2] U28
VccLAN may be grounded if Intel LAN is disabled AF24 VCCLAN[2] 320mA VCCSUS3_3[3] U26
VCCSUS3_3[4] U24
D VCCSUS3_3[5] P28 D
2 1 +TP_PCH_VCCDSW Y20 P26 +3VALW
C320 0.1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6]
VCCSUS3_3[7] N28
Near AD38 VCCSUS3_3[8] N26
+1.05VS AD38 VCCME[1] VCCSUS3_3[9] M28
1 1 1 VCCSUS3_3[10] M26 2 2
AD39 L28 C321 C325

USB
C391 C322 C318 VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
If two VccME rails can be 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z AD41 J28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 VCCME[3] VCCSUS3_3[13] 1 1
J26
combined, only total 2 x 22 —F and AF43
VCCSUS3_3[14]
H28
2 x 1 —F caps are necessary VCCME[4]
163mA
VCCSUS3_3[15]
VCCSUS3_3[16] H26
AF41 VCCME[5] VCCSUS3_3[17] G28
1849mA VCCSUS3_3[18] G26
AF42 VCCME[6] VCCSUS3_3[19] F28
Near V39 VCCSUS3_3[20] F26
V39 E28 +3VALW +5VALW
VCCME[7] VCCSUS3_3[21]

Clock and Miscellaneous

1 1 1 VCCSUS3_3[22] E26
V41 C28

CH751H-40PT_SOD323-2
C447 C323 C324 VCCME[8] VCCSUS3_3[23]
VCCSUS3_3[24] C26

1
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z V42 B27
2 2 2 VCCME[9] VCCSUS3_3[25] D16 R344
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
100_0402_1%
Y41 U23

2
VCCME[11] VCCSUS3_3[28] +3VS +5VS
Y42 VCCME[12] VCCIO[56] V23 +1.05VS

1
F24 +PCH_VCC5REFSUS 2 1
V5REF_SUS C326 0.1U_0402_16V4Z D17 R346
+VCCRTCEXT
> 1mA
C 1 2 V9 DCPRTC CH751H-40PT_SOD323-2 C
C327 0.1U_0402_16V4Z 100_0402_1%

2
+1.05VS L17 1 2 196mA > 1mA K49 +PCH_VCC5REF +PCH_VCC5REF
10UH_LB2012T100MR_20% V5REF
1 +PCH_VRM AU24

PCI/GPIO/LPC
VCCVRM[3]
1 1
1

C328 + C329 +3VS C330

220U_B2_2.5VM_R15 1U_0402_6.3V4Z R347 +1.05VS_PCHDPLL_A
68mA VCC3_3[8] J38
BB51 VCCADPLLA[1]
0_0603_5% BB53 L38 1U_0402_6.3V4Z
2 2 @ VCCADPLLA[2] VCC3_3[9] 2
2
69mA M36 C333
2

L18 1 +1.05VS_PCHDPLL_B VCC3_3[10] 0.1U_0402_16V4Z

2
10UH_LB2012T100MR_20%
BD51 VCCADPLLB[1] 375mA
1 BD53 VCCADPLLB[2] VCC3_3[11] N36
1
1
C331 + C332 +1.05VS 1U_0402_6.3V4Z AH23 P36
220U_B2_2.5VM_R15 1U_0402_6.3V4Z VCCIO[21] VCC3_3[12]
1 1 1 AJ35 VCCIO[22]
AH35 VCCIO[23] VCC3_3[13] U35
2 2 C334 C335 C336 +3VS
1U_0402_6.3V4Z AF34 3062mA
2 2 2 VCCIO[2]
VCC3_3[14] AD13 2 1
1U_0402_6.3V4Z AH34 C337 0.1U_0402_16V4Z
VCCIO[3]
AF32 VCCIO[4]
VCCSATAPLL[1] AK3
1 2 +VCCSST V12 31mA AK1
C338 0.1U_0402_16V4Z DCPSST VCCSATAPLL[2]

+1.05VS
1 2 +V1.1A_INT_VCCSUS Y22 DCPSUS
C341 0.1U_0402_16V4Z AH22
B VCCIO[9] B

+3VALW 163mA
P18 VCCSUS3_3[29] 196mA VCCVRM[4] AT20 +PCH_VRM
1 2 U19

SATA
VCCSUS3_3[30]

PCI/GPIO/LPC
C343 0.1U_0402_16V4Z AH19 +1.05VS
VCCIO[10]
U20 VCCSUS3_3[31] 1
AD20 C342
VCCIO[11] 1U_0402_6.3V4Z
U22 VCCSUS3_3[32]
VCCIO[12] AF22
+3VS 2
375mA VCCIO[13] AD19
1
C344
2
0.1U_0402_16V4Z
V15 VCC3_3[5] 3062mA VCCIO[14] AF20
VCCIO[15] AF19
V16 VCC3_3[6] VCCIO[16] AH20
+VTT Y16 AB19
VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
1 2 VCCIO[19] AB22
C345 4.7U_0603_6.3V6K +1.05VS
> 1mA VCCIO[20] AD22
1 2 AT18 V_CPU_IO[1]
C346 0.1U_0402_16V4Z AA34 +PCH_VCCME1 R351 1 2 0_0402_5%
CPU

VCCME[13]
1 2 VCCME[14] Y34 +PCH_VCCME2 R352 1 2 0_0402_5%
C347 0.1U_0402_16V4Z AU18 1849mA Y35 +PCH_VCCME3 R353 1 2 0_0402_5%
V_CPU_IO[2] VCCME[15]
VCCME[16] AA35 +PCH_VCCME4 R354 1 2 0_0402_5%
+RTCVCC
RTC

1 2 A12 VCCRTC 2mA 6mA VCCSUSHDA L30 +3VALW VCCSUSHDA can be

HDA

C351 0.1U_0402_16V4Z
either 1.5V or 3.3V
A 1 A
1 2 IBEXPEAK-M QV20 A0_FCBGA1071 C350
C348 1U_0402_6.3V4Z HM55R3@
1U_0402_6.3V4Z
2
1 2
C349 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 32 of 58
5 4 3 2 1
 5 4 3 2 1

U11I
AY7 VSS[159] VSS[259] H49
B11 H5 U11H
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AB16 VSS[0]
B19 VSS[162] VSS[262] K11
B23 VSS[163] VSS[263] K43 AA19 VSS[1] VSS[80] AK30
B31 VSS[164] VSS[264] K47 AA20 VSS[2] VSS[81] AK31
B35 VSS[165] VSS[265] K7 AA22 VSS[3] VSS[82] AK32
B39 VSS[166] VSS[266] L14 AM19 VSS[4] VSS[83] AK34
B43 VSS[167] VSS[267] L18 AA24 VSS[5] VSS[84] AK35
B47 VSS[168] VSS[268] L2 AA26 VSS[6] VSS[85] AK38
D B7 VSS[169] VSS[269] L22 AA28 VSS[7] VSS[86] AK43 D
BG12 VSS[170] VSS[270] L32 AA30 VSS[8] VSS[87] AK46
BB12 VSS[171] VSS[271] L36 AA31 VSS[9] VSS[88] AK49
BB16 VSS[172] VSS[272] L40 AA32 VSS[10] VSS[89] AK5
BB20 VSS[173] VSS[273] L52 AB11 VSS[11] VSS[90] AK8
BB24 VSS[174] VSS[274] M12 AB15 VSS[12] VSS[91] AL2
BB30 VSS[175] VSS[275] M16 AB23 VSS[13] VSS[92] AL52
BB34 VSS[176] VSS[276] M20 AB30 VSS[14] VSS[93] AM11
BB38 VSS[177] VSS[277] N38 AB31 VSS[15] VSS[94] BB44
BB42 VSS[178] VSS[278] M34 AB32 VSS[16] VSS[95] AD24
BB49 VSS[179] VSS[279] M38 AB39 VSS[17] VSS[96] AM20
BB5 VSS[180] VSS[280] M42 AB43 VSS[18] VSS[97] AM22
BC10 VSS[181] VSS[281] M46 AB47 VSS[19] VSS[98] AM24
BC14 VSS[182] VSS[282] M49 AB5 VSS[20] VSS[99] AM26
BC18 VSS[183] VSS[283] M5 AB8 VSS[21] VSS[100] AM28
BC2 VSS[184] VSS[284] M8 AC2 VSS[22] VSS[101] BA42
BC22 VSS[185] VSS[285] N24 AC52 VSS[23] VSS[102] AM30
BC32 VSS[186] VSS[286] P11 AD11 VSS[24] VSS[103] AM31
BC36 VSS[187] VSS[287] AD15 AD12 VSS[25] VSS[104] AM32
BC40 VSS[188] VSS[288] P22 AD16 VSS[26] VSS[105] AM34
BC44 VSS[189] VSS[289] P30 AD23 VSS[27] VSS[106] AM35
BC52 VSS[190] VSS[290] P32 AD30 VSS[28] VSS[107] AM38
BH9 VSS[191] VSS[291] P34 AD31 VSS[29] VSS[108] AM39
BD48 VSS[192] VSS[292] P42 AD32 VSS[30] VSS[109] AM42
BD49 VSS[193] VSS[293] P45 AD34 VSS[31] VSS[110] AU20
BD5 VSS[194] VSS[294] P47 AU22 VSS[32] VSS[111] AM46
BE12 VSS[195] VSS[295] R2 AD42 VSS[33] VSS[112] AV22
BE16 VSS[196] VSS[296] R52 AD46 VSS[34] VSS[113] AM49
BE20 VSS[197] VSS[297] T12 AD49 VSS[35] VSS[114] AM7
C BE24 T41 AD7 AA50 C
VSS[198] VSS[298] VSS[36] VSS[115]
BE30 VSS[199] VSS[299] T46 AE2 VSS[37] VSS[116] BB10
BE34 VSS[200] VSS[300] T49 AE4 VSS[38] VSS[117] AN32
BE38 VSS[201] VSS[301] T5 AF12 VSS[39] VSS[118] AN50
BE42 VSS[202] VSS[302] T8 Y13 VSS[40] VSS[119] AN52
BE46 VSS[203] VSS[303] U30 AH49 VSS[41] VSS[120] AP12
BE48 VSS[204] VSS[304] U31 AU4 VSS[42] VSS[121] AP42
BE50 VSS[205] VSS[305] U32 AF35 VSS[43] VSS[122] AP46
BE6 VSS[206] VSS[306] U34 AP13 VSS[44] VSS[123] AP49
BE8 VSS[207] VSS[307] P38 AN34 VSS[45] VSS[124] AP5
BF3 VSS[208] VSS[308] V11 AF45 VSS[46] VSS[125] AP8
BF49 VSS[209] VSS[309] P16 AF46 VSS[47] VSS[126] AR2
BF51 VSS[210] VSS[310] V19 AF49 VSS[48] VSS[127] AR52
BG18 VSS[211] VSS[311] V20 AF5 VSS[49] VSS[128] AT11
BG24 VSS[212] VSS[312] V22 AF8 VSS[50] VSS[129] BA12
BG4 VSS[213] VSS[313] V30 AG2 VSS[51] VSS[130] AH48
BG50 VSS[214] VSS[314] V31 AG52 VSS[52] VSS[131] AT32
BH11 VSS[215] VSS[315] V32 AH11 VSS[53] VSS[132] AT36
BH15 VSS[216] VSS[316] V34 AH15 VSS[54] VSS[133] AT41
BH19 VSS[217] VSS[317] V35 AH16 VSS[55] VSS[134] AT47
BH23 VSS[218] VSS[318] V38 AH24 VSS[56] VSS[135] AT7
BH31 VSS[219] VSS[319] V43 AH32 VSS[57] VSS[136] AV12
BH35 VSS[220] VSS[320] V45 AV18 VSS[58] VSS[137] AV16
BH39 VSS[221] VSS[321] V46 AH43 VSS[59] VSS[138] AV20
BH43 VSS[222] VSS[322] V47 AH47 VSS[60] VSS[139] AV24
BH47 VSS[223] VSS[323] V49 AH7 VSS[61] VSS[140] AV30
BH7 VSS[224] VSS[324] V5 AJ19 VSS[62] VSS[141] AV34
C12 VSS[225] VSS[325] V7 AJ2 VSS[63] VSS[142] AV38
C50 VSS[226] VSS[326] V8 AJ20 VSS[64] VSS[143] AV42
B B
D51 VSS[227] VSS[327] W2 AJ22 VSS[65] VSS[144] AV46
E12 VSS[228] VSS[328] W52 AJ23 VSS[66] VSS[145] AV49
E16 VSS[229] VSS[329] Y11 AJ26 VSS[67] VSS[146] AV5
E20 VSS[230] VSS[330] Y12 AJ28 VSS[68] VSS[147] AV8
E24 VSS[231] VSS[331] Y15 AJ32 VSS[69] VSS[148] AW14
E30 VSS[232] VSS[332] Y19 AJ34 VSS[70] VSS[149] AW18
E34 VSS[233] VSS[333] Y23 AT5 VSS[71] VSS[150] AW2
E38 VSS[234] VSS[334] Y28 AJ4 VSS[72] VSS[151] BF9
E42 VSS[235] VSS[335] Y30 AK12 VSS[73] VSS[152] AW32
E46 VSS[236] VSS[336] Y31 AM41 VSS[74] VSS[153] AW36
E48 VSS[237] VSS[337] Y32 AN19 VSS[75] VSS[154] AW40
E6 VSS[238] VSS[338] Y38 AK26 VSS[76] VSS[155] AW52
E8 VSS[239] VSS[339] Y43 AK22 VSS[77] VSS[156] AY11
F49 VSS[240] VSS[340] Y46 AK23 VSS[78] VSS[157] AY43
F5 VSS[241] VSS[341] P49 AK28 VSS[79] VSS[158] AY47
G10 VSS[242] VSS[342] Y5
G14 Y6 IBEXPEAK-M QV20 A0_FCBGA1071
VSS[243] VSS[343] HM55R3@
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
A H30 VSS[255] VSS[355] AK45 A
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

Security Classification Compal Secret Data Compal Electronics, Inc.

IBEXPEAK-M QV20 A0_FCBGA1071 2009/01/23 2010/01/23 Title
HM55R3@
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 33 of 58
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn. SATA ODD Conn

+5VS
1.2A
Place closely JHDD SATA CONN. +5VS
1.1A
Place components closely ODD CONN. USB Board
1 1 1 1
C356 C357 C358 C359 1 1 1 1 1 W=60mils
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C352 C353 C354
2 2 2 2 10U_0805_10V4Z
@
10U_0805_10V4Z 1U_0402_6.3V4Z
C355
0.1U_0402_16V4Z
C360
0.1U_0402_16V4Z
+5VALW 1.4A
U14
+USB_VCCA
For EMI request
2 2 2 2 2
1 GND OUT 8 2 1
2 7 C361 1000P_0402_50V7K
IN OUT
D 3 IN OUT 6 D
SSD HDD need 400mA for 3V(PHISON) 41 USB_EN# 4 EN# FLG 5 USB_OC#0 29,41
+3VS 1
+3VS rail reserve for SSD G528_SO8
for 16" use C362
1 1 1
for 17" expansion using 4.7U_0805_10V4Z
C363 C364 2 @
1 C365 C366 JODD
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ @ @ @ 1 +5VS
2 2 2 GND SATA_PTX_C_DRX_P4_ODD JODDB
A+ 2
2 SATA_PTX_C_DRX_N4_ODD
A- 3 1 1
GND 4 2 2
5 SATA_PRX_DTX_N4_ODD 3
B- SATA_PRX_DTX_P4_ODD 3
B+ 6 4 4
7 5 +USB_VCCA
JHDD GND 5
6 6
7 SATA_PRX_DTX_P4 W=60mils JUSBB
7 SATA_PRX_DTX_N4
GND 1 DP 8 8 8 1 1
2 SATA_PTX_C_DRX_P1 C369 1 2 0.01U_0402_25V7K 9 +5VS 9 2
A+ SATA_PTX_DRX_P1 25 +5V 9 2
3 SATA_PTX_C_DRX_N1 C367 1 2 0.01U_0402_25V7K 10 10 SATA_PTX_C_DRX_N4 3
A- SATA_PTX_DRX_N1 25 +5V 10 3
4 11 11 SATA_PTX_C_DRX_P4 4
GND SATA_PRX_DTX_N1 C368 1 MD 11 4
B- 5 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N1 25 15 GND GND 12 12 12 5 5
6 SATA_PRX_DTX_P1 C370 1 2 0.01U_0402_25V7K 14 13 13 6
B+ SATA_PRX_C_DTX_P1 25 GND GND GND 6
7 14 USB20_N0_R 7
GND GND USB20_P0_R 7
8 8
SANTA_206401-1_RV E&T_6905-E12N-00R 9
@ @ USB20_N1_R 9
V33 8 +3VS 10 10
9 USB20_P1_R 11
V33 11
V33 10 12 12
C 11 13 C
GND GND
GND 12 14 GND
GND 13
14 SATA_PTX_C_DRX_P4_ODD C371 1 2 16@ 0.01U_0402_25V7K E&T_6905-E12N-00R
V5 +5VS
15 SATA_PTX_C_DRX_N4_ODD C372 1 2 16@ 0.01U_0402_25V7K @
V5
V5 16
17 SATA_PRX_DTX_N4_ODD C373 1 2 16@ 0.01U_0402_25V7K
GND SATA_PRX_DTX_P4_ODD C374 1
Reserved 18 2 16@ 0.01U_0402_25V7K
GND 19
V12 20
24 21 SATA_PRX_DTX_P4 C375 1 2 17@ 0.01U_0402_25V7K
GND V12 SATA_PRX_C_DTX_P4 25
23 22 SATA_PRX_DTX_N4 C376 1 2 17@ 0.01U_0402_25V7K
GND V12 SATA_PRX_C_DTX_N4 25
SATA_PTX_C_DRX_N4 C377 1 2 17@ 0.01U_0402_25V7K
SATA_PTX_DRX_N4 25
SANTA_19A202-1_22P SATA_PTX_C_DRX_P4 C378 1 2 17@ 0.01U_0402_25V7K
SATA_PTX_DRX_P4 25
@ Reserve for EMI request
this is temp. footprint
@ R73 0_0402_5%
1 2
L53

29 USB20_P0 1 2 USB20_P0_R
1 2
eSATA/USB +USB_VCCB
USB20_N0_R
W=60mils 29 USB20_N0 4 4 3 3
220U_6.3V_M_R15 1000P_0402_50V7K WCM-2012-900T_0805
B @ R87 0_0402_5% B
1 1 1
W=60mils C379 +
1 2
+5VALW
U15
1.4A +USB_VCCB C380
2
C381
2
2
1 GND OUT 8
2 7 0.1U_0402_16V4Z Reserve for EMI request
IN OUT D18 @
3 IN OUT 6
USB_EN# 4 5 2 @ R77 0_0402_5%
EN# FLG USB_OC#3 29,41
1 1 2
G528_SO8 1
C383
3 eSATA/USB Conn L54
2
C382 4.7U_0805_10V4Z PJDLC05_SOT23-3 JESATA
1000P_0402_50V7K @ 1 USB 29 USB20_N1 1 2 USB20_N1_R
2 USB20_N3_R VBUS 1 2
2 D-
1 USB20_P3_R 3 D+
For EMI request 4 29 USB20_P1 4 3 USB20_P1_R
GND 4 3
5 WCM-2012-900T_0805
C385 1 GND
25 SATA_PTX_DRX_P5 2 0.01U_0402_25V7K SATA_PTX_C_DRX_P5 6 A+
C386 1 2 0.01U_0402_25V7K SATA_PTX_C_DRX_N5 7 ESATA @ R88 0_0402_5%
25 SATA_PTX_DRX_N5 A-
Reserve for EMI request 8 GND SHIELD 12 1 2
C387 1 2 0.01U_0402_25V7K SATA_PRX_DTX_N5 9 13
25 SATA_PRX_C_DTX_N5 B- SHIELD
@ R72 0_0402_5% C388 1 2 0.01U_0402_25V7K SATA_PRX_DTX_P5 10 14
25 SATA_PRX_C_DTX_P5 B+ SHIELD
1 2 11 GND SHIELD 15

L52 FOX_3Q318111
@
29 USB20_N3 1 2 USB20_N3_R
A 1 2 A

29 USB20_P3 4 3 USB20_P3_R
4 3
WCM-2012-900T_0805

@ R85 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 34 of 58
5 4 3 2 1
 5 4 3 2 1

BlueTooth Interface MDC 1.5 Conn.

+3VS +3VS
+3VALW

2
2
R361 C396 1 1 1 1
100K_0402_5% 0.1U_0402_16V7K
BT@ BT@ Bluetooth Connector C392 C393 C394 C395

3
1 S
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z

1
G
JBT 2 MDC@ 2 MDC@ 2 MDC@ 2 MDC@
30 BT_PWR# 1 2 2
D R362 47K_0402_5% 1 12 D
BT@ C390 Q28 BT@ GND2
D 11

1
0.01U_0402_25V7K AO3413_SOT23 GND1
BT@ JMDC
2
+BT_VCC
10 10 1 GND1 RES0 2 +3VALW
29 USB20_P5 9 9 25 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
29 USB20_N5 8 8 5 GND2 3.3V 6
36 WLAN_BT_CLK 7 7 25 AZ_SYNC_MD 7 IAC_SYNC GND3 8
30 BT_DET# 1 BT@ 2 6 AZ_SDIN1_MD_R 9 10
6 IAC_SDATA_IN GND4
30 BT_RST# 1 BT@ 2BT_RESET# R365 0_0402_5% 5 5 25 AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD 25
R366 0_0402_5% 4
36 WLAN_BT_DATA 4

2
3 3
1 2 2 R368

GND
GND
GND
GND
GND
GND
+3VS 2
R367 @ 4.7K_0402_5% 1 10_0402_5%
1 @
+BT_VCC
ACES_87213-1000G 2 1 AZ_SDIN1_MD_R ACES_88018-124G
25 AZ_SDIN1_MD

13
14
15
16
17
18

1
2
C397 (MAX=200mA)
1 @ R369 33_0402_5% MDC@ @ 1
0.1U_0402_16V4Z C400
BT@ C398 C399 BT@R370
BT@R370 Connector for MDC Rev1.5 10P_0402_50V8J
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5% @
BT@ 2 BT@ 2

1
For EMI

C please close to JKB1 C

KEYBOARD KEYBOARD KSO16 1

C401
2
100P_0402_50V8J
KSO17 1 2
CONN. for 16" CONN. for 17" KSO2
C402
1
100P_0402_50V8J
2
C404 100P_0402_50V8J
KSO1 1 2
C405 100P_0402_50V8J
KSI[0..7] KSO0 1 2
KSO[0..17]
KSI[0..7]

KSO[0..17] 41
41
KSO4
C406
1
100P_0402_50V8J
2
Touch/B Connector
C407 100P_0402_50V8J
KSO3 1 2 JTOUCH
C408 100P_0402_50V8J 1
JKB1 JKB2 KSO5 +5VS 1
1 2 41 TP_CLK 2 2
JKB34 JKB34 1 2 +3VS C409 100P_0402_50V8J 3 5
34 34 41 TP_DATA 3 GND
KSO16 KSO16 R372 300_0402_5% KSO14 1 2 4 6
33 33 C410 100P_0402_50V8J 4 GND
32 KSO17 32 KSO17 KSO6 ACES_85201-04051
31 31 1 2 2
C411 100P_0402_50V8J 1 @
30 30 KSO7
29 29 1 2 3
KSO2 KSO2 C412 100P_0402_50V8J
28 KSO1 28 KSO1 KSO13 D19 @
27 27 1 2
KSO0 KSO0 C413 100P_0402_50V8J PJDLC05_SOT23-3
26 KSO4 26 KSO4 KSO8
25 25 1 2
KSO3 KSO3 C415 100P_0402_50V8J
24 KSO5 24 KSO5 KSO9
23 23 1 2
B KSO14 KSO14 C416 100P_0402_50V8J B
22 KSO6 22 KSO6 KSO10
21 21 1 2
KSO7 KSO7 C417 100P_0402_50V8J
20 KSO13 20 KSO13 KSO11
19 19 1 2
KSO8 KSO8 C418 100P_0402_50V8J
18 KSO9 18 KSO9 KSO12
17 17 1 2
KSO10 KSO10 C419 100P_0402_50V8J
16 KSO11 16 KSO11 KSO15
15 15 1 2
KSO12 KSO12 C420 100P_0402_50V8J
14 KSO15 14 KSO15 KSI7 1 2
13
12
11
KSI7
KSI2
13
12
11
KSI7
KSI2 KSI2
C421
1
100P_0402_50V8J
2
SW/B Connector
KSI3 KSI3 C422 100P_0402_50V8J
10 KSI4 10 KSI4 KSI3
9 9 1 2
KSI0 KSI0 C423 100P_0402_50V8J
8 KSI5 8 KSI5 KSI4 JPOWER
7 7 1 2
KSI6 KSI6 C424 100P_0402_50V8J
6 KSI1 6 KSI1 KSI0 1 1 ON/OFFBTN#_R 43
5 5 1 2 2 2 KSO0 41 EC_PLAYBTN#
JKB4 JKB4 2 1 C425 100P_0402_50V8J
4 CAPS_LED# 4 CAPS_LED# R376 300_0402_5%
+3VS
KSI5 3 3 KSI1 41 EC_MUTEBTN#
ON/OFFBTN#_R C426 1
3 3 CAPS_LED# 41 1 2 4 4 KSI3 41 EC_FRDBTN# 2@ 220P_0402_50V7K
C427 100P_0402_50V8J
2 NUM_LED# 2 NUM_LED# KSI6 5 5 KSI5 41 EC_REVBTN#
KSI1 C428 1
1 1 NUM_LED# 41 1 2 6 6 KSI2 41 2@ 220P_0402_50V7K
C429 100P_0402_50V8J
ACES_88170-3400 ACES_88170-3400 KSI1 7 7 KSI3 C430 1
1 2 8 8 2@ 220P_0402_50V7K
@ @ C431 100P_0402_50V8J
CAPS_LED# 9 9 KSI5 C432 1
1 2 10 10 2@ 220P_0402_50V7K
C433 100P_0402_50V8J
NUM_LED# GND 11 KSI2 C434 1
1 2 GND 12 2@ 220P_0402_50V7K
C435 100P_0402_50V8J
A A
ACES_85201-1005N
@
For EMI
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 35 of 58
5 4 3 2 1
 +3VS
PCIe Mini Card-WLAN/WiMax PCIe Mini Card-3G
J3G +3VS
PJ27 +3V_WLAN 90 MIL For SED
For SED 1 1 2 2
+3VALW 2 1 +3V_WLAN 3 4 0.1U_0402_16V4Z
2 1 0.1U_0402_16V4Z 3 4
5 5 6 6 1 1 1

1
1 1 1 7 8 +UIM_PWR CM4 CM5 CM6 C255
JUMP_43X79 7 8

1
9 10 UIM_DATA 0.01U_0402_25V4Z 3G@ 3G@ 47P_0402_50V8J
@ CM1 CM2 CM3 C253 9 10 UIM_CLK 3G@ 3G@
Short PJ27 for Wimax 11 12

2
WLAN@ WLAN@ WLAN@ 47P_0402_50V8J 11 12 UIM_RESET 2 2 2
PJ26 13 14

2
2 2 2 WLAN@ 13 14 UIM_VPP 4.7U_0805_10V4Z
Short PJ26 for WLAN 15 15 16 16
+3VS 2 1 0.01U_0402_25V4Z 4.7U_0805_10V4Z 17 18
2 1 17 18
19 19 20 20 3G_OFF# 41
21 22 PLT_RST#
JUMP_43X79 21 22
23 23 24 24
@ 25 26
+3V_WLAN +1.5VS 25 26
For SED 27 27 28 28
29 30 PM_SMBCLK
+1.5VS 0.1U_0402_16V4Z 29 30 PM_SMBDATA
31 31 32 32
1 1 1 33 33 34 34

1
JWLAN 35 36 USB20_N12 29
CM7 CM8 CM9 C254 35 36
1 1 2 2
WLAN@ WLAN@ WLAN@ 47P_0402_50V8J
37 37 38 38 USB20_P12 29 3G
35 WLAN_BT_DATA 3 4 +3VS 39 40

2
3 4 2 2 2 WLAN@ 39 40
35 WLAN_BT_CLK 5 5 6 6 41 41 42 42
7 8 0.01U_0402_25V4Z 4.7U_0805_10V4Z 43 44
26 CLKREQ_WLAN# 7 8 43 44
9 9 10 10 45 45 46 46
26 CLK_WLAN# 11 11 12 12 47 47 48 48
26 CLK_WLAN 13 13 14 14 49 49 50 50
15 15 16 16 51 51 52 52
17 18 +UIM_PWR
17 18 XMIT_OFF#
19 19 20 20 XMIT_OFF# 41 53 GND1 GND2 54
21 22 PLT_RST#
21 22 PLT_RST# 5,13,29,37,41,42
26 PCIE_PRX_WLANTX_N2 23 23 24 24

1
25 26 FOX_AS0B226-S40N-7F RM2
26 PCIE_PRX_WLANTX_P2 25 26
27 28 @ 4.7K_0402_5%
27 28 @
29 29 30 30 PM_SMBCLK 11,12,22,26
26 PCIE_PTX_C_WLANRX_N2 31 31 32 32 PM_SMBDATA 11,12,22,26 J3GSIM
26 PCIE_PTX_C_WLANRX_P2 33 34

2
33 34 +UIM_PWR
35 35 36 36 USB20_N13 29 +UIM_PWR 1 VCC GND 4
WLAN/ WiFi 37 38 USB20_P13 29 WiMax UIM_RESET 2 5 UIM_VPP
37 38 RST VPP

1
+3V_WLAN 39 40 1 UIM_CLK 3 6 UIM_DATA
39 40 DM1 CLK I/O
41 41 42 42
43 44 CM13 RLZ20A_LL34 7 8 1
43 44 NC NC

1
45 46 0.1U_0402_16V4Z 3G@ 1 1
45 46 3G@ 2 MOLEX_47273-0001~D CM14
47 48

2
47 48
41 E51_TXD 1 2 49 49 50 50 1 2 PLT_RST# CM15 CM16 @ 22P_0402_50V8J
2 @
41 E51_RXD 1R16 0_0402_5%
2 51 51 52 52 RN5 100K_0402_5% 10P_0402_50V8J 10P_0402_50V8J DM2 DM3 DM4
R17 0_0402_5% 3G@ 2 2 3G@ DAN217_SC59 DAN217_SC59 DAN217_SC59
53 54 @ @ @

2
GND1 GND2
Debug card using
+UIM_PWR
FOX_AS0B226-S40N-7F
@

+3VALW_CARD +3VS_CARD +1.5VS_CARD JEXP

Imax = 0.275A Imax = 1.35A Imax = 0.75A
1 GND
1 1 1 1 1 1 USB20_N8_R 2
CN1 CN2 CN3 CN4 CN5 CN6 USB20_P8_R USB_D-
3 USB_D+
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z CP_USB# 4
NEW@ NEW@ NEW@ NEW@ NEW@ NEW@ CPUSB#
5 RSV
2 2 2 2 2 2
6 RSV
PM_SMBCLK 7
PM_SMBDATA SMB_CLK
8 SMB_DATA
+3VALW UN1 NEW@ 60mils +1.5VS_CARD 9 +1.5V
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD 10 +1.5V
1 NEW@ 2 CP_USB# 14 1.5Vin 1.5Vout 13 27,37 EC_SWI# 11 WAKE#
RN4 100K_0402_5% +3VALW_CARD 12
PERST# +3.3VAUX
share with USB OC PIN 40mils 13 PERST#
+3VS 2 3.3Vin 3.3Vout 3 +3VS_CARD +3VS_CARD 14 +3.3V
RN3
1 2EXP_CPPE#
10K_0402_5%
need always pull high 4 3.3Vin 3.3Vout 5
CLKREQ#
15 +3.3V
40mils 16 CLKREQ#
+3VALW 17 15 +3VALW_CARD EXP_CPPE# 17
AUX_IN AUX_OUT 29 EXP_CPPE# CPPE#
26 CLK_NEW# 18 REFCLK-
PLT_RST# 6 19 19
SYSRST# OC# 26 CLK_NEW REFCLK+
20 GND GND 31
20 8 PERST# 21 32
41,51 SYSON SHDN# PERST# 26 PCIE_PRX_NEWTX_N1 PERn0 GND
26 PCIE_PRX_NEWTX_P1 22 PERp0
+3VS +3VS 1 16 Reserve for EMI request 23 29
38,41,44,47,50,52,54 SUSP# STBY# NC GND GND
26 PCIE_PTX_C_NEWRX_N1 24 PETn0 GND 30
+3VS EXP_CPPE# 10 7 R125 0_0402_5% NEW@ 26 PCIE_PTX_C_NEWRX_P1 25
CPPE# GND PETp0
1

RN6 1 1 2 26
10K_0402_5% CN7 CP_USB# GND
9 CPUSB# Thermal_Pad 21
1

@ 0.1U_0402_16V4Z L56 @ 27
RN7 UN2 @ RCLKEN GND
18 RCLKEN 28 GND
5

10K_0402_5% @ 2 USB20_P8_R
29 USB20_P8 1 2
2

@ CLKREQ# TPS2231MRGPR-2 QFN 1 2 SANTA_132862-2_26P

2
G Vcc

B CLKREQ_NEW# @
4 CLKREQ_NEW# 26
2

Y USB20_N8_R this is temp. footprint

1 A 29 USB20_N8 4 4 3 3
6

NC7SZ32P5X_NL_SC70-5 WCM-2012-900T_0805
3

Q5A
2N7002DW-T/R7_SOT363-6 R124 0_0402_5% NEW@
RCLKEN 2 another at page44 1 2
1

CLKREQ# 1 2 CLKREQ_NEW#
RN8 0_0402_5%
NEW@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 36 of 58
 A B C D E

+LAN_VDD12
Close to Pin10,13,30,36,45

2 2 2 2 2
CL1 CL2 CL3 CL4 CL5
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1

Place Close to Chip UL1

26 PCIE_PRX_C_LANTX_P3 CL6 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P3 20 33 LAN_DO PAD T40

HSOP LED3/EEDO LAN_DI
LED2/EEDI/AUX 34 1 2 +3V_LAN
26 PCIE_PRX_C_LANTX_N3 CL7 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N3 21 35 LAN_SK_LAN_LINK# RL1 3.6K_0402_5% Close to Pin1,37,29
HSON LED1/EESK LAN_CS
EECS 32 2 1
15 RL2 1K_0402_5% +3V_LAN
26 PCIE_PTX_C_LANRX_P3 HSIP
38 LAN_ACTIVITY#
LED0
26 PCIE_PTX_C_LANRX_N3 16 HSIN
RTL8103EL-GR 2 LAN_MDI0+
+3V_LAN MDIP0 LAN_MDI0-
26 CLK_LAN 17 REFCLK_P MDIN0 3 2 2 2
18 5 LAN_MDI1+ CL8 CL9 CL10
26 CLK_LAN# REFCLK_M MDIP1
1 @ 2 EC_SWI# 6 LAN_MDI1-
RL3 100K_0402_5% MDIN1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
26 CLKREQ_LAN# 1 2 25 CLKREQB NC 8
R153 0_0402_5% 1 1 1
NC 9
5,13,29,36,41,42 PLT_RST# 27 PERSTB NC 11 Close to Pin48
NC 12
+3VS
RL4 1 2 2.49K_0402_1% 46 4
RSET NC
1

26 48 +VCTRL12 +VCTRL12
27,36 EC_SWI# LANWAKEB VCTRL12A
RL5 ISOLATEB 28
1K_0402_1% ISOLATEB
VDDTX 19 +EVDD12 1 2 Close to Pin19
LAN_X1 41 30 +LAN_VDD12
2 LAN_X2 CKXTAL1 DVDD12 CL11 CL12 +EVDD12 2
42 36
2

ISOLATEB CKXTAL2 DVDD12 10U_0805_10V4Z 0.1U_0402_16V4Z

DVDD12 13
2 @ 1
DVDD12 10

NC 39
RL6 2 2
15K_0402_5% YL1 23 44 CL13 CL14
LAN_X1 2 NC NC
1LAN_X2 24 NC VCTRL12D 45 +LAN_VDD12
1U_0402_6.3V4Z 0.1U_0402_16V4Z
1 1
25MHz_20pF_6X25000017 7 GND VDD33 29 +3V_LAN
1 1 14 GND VDD33 37
CL15 CL16 31 GND
47 GND AVDD33 1
27P_0402_50V8J 27P_0402_50V8J 40
2 2 NC
22 GNDTX NC 43

RTL8103EL-GR_LQFP48_7X7

For EMI request

CL17 68P_0402_50V8J
LAN Conn.
1 @ 2 ISOLATEB 2 1
41,44 WOL_EN#
R161 0_0402_5% JLAN
LAN_ACTIVITY# 2 1 12
RL7 150_0402_1% Yellow LED-

+3V_LAN 2 1 11 Yellow LED+

RL8 150_0402_1%
8 PR4-
3 3

7 PR4+
RJ45_MIDI1- 6 PR2-
5 PR3-
UL2
4 PR3+
LAN_MDI0+ 1 16 RJ45_MIDI0+
LAN_MDI0- TD+ TX+ RJ45_MIDI0- RJ45_MIDI1+
2 TD- TX- 15 3 PR2+
2 1 3 14 RL9
CL18 0.01U_0402_16V7K CT CT CL19 1
4 NC NC 13 2 1000P_0402_50V7K 1 2 75_0402_1% RJ45_MIDI0- 2 PR1-
5 12 1 2 1 2 RJ45_GND 14
NC NC CL20 1000P_0402_50V7K 75_0402_1% RJ45_MIDI0+ SHLD2
2 1 6 CT CT 11 1 PR1+
CL21 0.01U_0402_16V7K LAN_MDI1+ 7 10 RJ45_MIDI1+ RL10 13
LAN_MDI1- RD+ RX+ RJ45_MIDI1- LAN_SK_LAN_LINK# SHLD1
8 RD- RX- 9 2 1 10 Green LED-
RL11 150_0402_1%
2 1 9 Green LED+
Place these components NS681680 CL22 68P_0402_50V8J
TYCO_2068888-1_12P-T
colsed to UL2
For EMI request @
+3V_LAN 2 1
RL12 150_0402_1%

RJ45_GND 1 2 1000P_1808_3KV7K LANGND

CL23 1 1
CL24 CL25
4 4
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 37 of 58
A B C D E
 5 4 3 2 1

+3VS_DVDD RA1
Codec 10U_0805_10V4Z 30mil 2 1
1 1 0_0603_5%
+3VS
Audio regulator +5VS
CA1 CA2

1
+AVDD
2 2 PJ22

1
RA3 0.1U_0402_16V4Z JUMP_43X39
2 1 10U_0805_10V4Z 0.1U_0402_16V4Z 40mil @
+VDDA

2
0_0603_5% 1 1 1 1 1
CA3 CA4 CA5 CA6 CA57 10U_0805_10V4Z +VDDA

2
+5VALW
1 1 1
2 2 2 2 2 4.75V
D CA7 CA8 CA56 D
10U_0805_10V4Z 0.1U_0402_16V4Z 100P_0402_50V8J 100P_0402_50V8J 2 UA1
For EMI request 2 2 2 CA9 2
0.1U_0402_16V4Z 1U_0402_6.3V4Z

25

38
1 VIN VOUT 5

9
UA2 For EMI request @ CA10
1 1U_0402_6.3V4Z
2

AVDD1

AVDD2

DVDD_IO
DVDD
GND CA11 1 @
36,41,44,47,50,52,54 SUSP# 3 SHDN# BP 4 2 1

For EMI request 14 35 0.22U_0402_10V4Z

LINE2-L LOUT1_L AMP_SPK_L 39
APL5151-475BC-TRL_SOT23-5 @
15 36 @
LINE2-R LOUT1_R AMP_SPK_R 39
1 2
CA52 100P_0402_50V8J 16 39
39 MIC2_L MIC2_L LOUT2_L
Int. Mic MIC@
17 41
39 MIC2_R MIC2_R LOUT2_R
CA51 100P_0402_50V8J
1 2 23 LINE1_L SPDIFO1 48
MIC@
24 LINE1_R SPDIFO2 45
1 2
CA54 100P_0402_50V8J 21 33 1 RA4 2
39 MIC1_C_L MIC1_L HPOUT_L HP_L 39
63.4_0402_1%
Ext. Mic 22 32 1 RA5 2
39 MIC1_C_R MIC1_R HPOUT_R HP_R 39
CA53 100P_0402_50V8J 63.4_0402_1%
1 2
1 2 MONO_IN 12 37
CA12 100P_0402_50V8J BEEP_IN MONO_OUT
Beep sound
C 6 46 C
25 AZ_BITCLK_HD BITCLK DMIC_CLK1/2
5 44
25 AZ_SDOUT_HD SDATA_OUT DMIC_CLK3/4 EC Beep RA7
25 AZ_SDIN0_HD 2 1 AZ_SDIN0_HD_R 8 SDATA_IN LINE2_VREFO 20 1U_0402_6.3V4Z
41 EC_BEEP# 1 2
RA6 33_0402_5% 1 2 47K_0402_5%
11 18 CA46
25 AZ_RST_HD# RESET# LINE1_VREFO
10 28 10mil
25 AZ_SYNC_HD SYNC MIC1_VREFO
10mil
+MIC1_VREFO
PCI Beep RA8
CA13
19 +MIC2_VREFO 1 2 1 2 MONO_IN
MIC2_VREFO 1U_0402_6.3V4Z 25,28 PCH_SPKR
25 SPK_SEL 2 GPIO0/DMIC_DATA1/2 47K_0402_5%
31 1 2 1 2 0.1U_0402_16V4Z
CPVEE CA14 2.2U_0603_6.3V4Z CA45 MIC@
3 GPIO1/DMIC_DATA3/4
27 AC_VREF CA16 CA17 CA58
VREF

100P_0402_50V8J
10U_0805_10V4Z
SENSE_A 13 SENSE A AC_JDREF

0.1U_0402_16V4Z
JDREF 40 1 1 1

1
SENSE_B 34 1
SENSE B

2
20K_0402_1%

100P_0402_50V8J
CBN 30 1 2 1

CA55
2 1 EAPD# 47 CA15 RA12 CA18
39 MUTE# EAPD 2 2 2

1 RA9
RA11 0_0402_5% 29 2.2U_0603_6.3V4Z 10K_0402_5% 0.1U_0402_16V4Z
CBP 2
43

2
IF test OK, link direct NC 2
4 DVSS AVSS1 26 For EMI request
7 DVSS AVSS2 42

ALC272-GR_LQFP48_7X7
B CA19 @ 100P_0402_50V8J DGND AGND CA47 1 2 0.1U_0603_50V7K
B

1 2 2 1 AZ_BITCLK_HD
RA13 @ 100_0402_5% CA48 1 2 0.1U_0603_50V7K
GPIO0-->SPK_SEL HIGH:HARMAN
CA20 @ 100P_0402_50V8J LOW:NO-BRAND CA49 1 2 0.1U_0603_50V7K
1 2 AZ_RST_HD# 2 1 +3VS
RA15 4.7K_0402_5% CA50 1 2 0.1U_0603_50V7K
@
For EMI request 1 2
RA18 0_0603_5%

Sense Pin Impedance Codec Signals Function

39.2K PORT-A (PIN 39, 41) place close to chip
20K PORT-B (PIN 21, 22) Ext. MIC 39 MIC_SENSE 1 RA19 2 SENSE_A
SENSE A 20K_0402_1%

10K PORT-C (PIN 23, 24) SENSE_B

39 NBA_PLUG 1 2
RA20 5.1K_0402_1%
5.1K PORT-D (PIN 35, 36) SPK out
A 1 RA21 2 A
20K_0402_1%
39.2K PORT-E (PIN 14, 15) MIC@

20K PORT-F (PIN 16, 17) Int. MIC

SENSE B Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 37) Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
5.1K PORT-I (PIN 32, 33) Size Document Number Rev
Headphone out AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 38 of 58
5 4 3 2 1
 Ext. Mic
CH751H-40PT_SOD323-2
TPA6017 Medium Range Amplifier CA21
RA23 2 RA22
1K_0402_5% 4.7K_0402_5%
1 1
DA1
2 +MIC1_VREFO
4.7U_0805_10V4Z 2 1 2 1 MIC1_L
38 MIC1_C_L
+5VS 4.7U_0805_10V4Z 2 1 2 1 MIC1_R
38 MIC1_C_R
0.1U_0402_16V4Z 1K_0402_5%
CA22 RA24 2 RA25 1 1 2 +MIC1_VREFO
4.7K_0402_5% DA2
1 1 1 CH751H-40PT_SOD323-2

CA23
10U_0805_10V4Z
CA24 CA25 Int. Mic 2 MIC@ 1 +MIC2_VREFO
2 2 2 4.7K_0402_5% RA26
1 @ 2 INT_MIC_R 22
0.1U_0402_16V4Z 10 dB MIC@ RA27 MIC@ RA28 0_0402_5%
CA28 1K_0402_5% JMIC
1U_0402_6.3V4Z 2 1 2 1 INT_MIC 1 1 NC1 3
+5VS 38 MIC2_L
1 2 2 2 NC2 4

1
1U_0402_6.3V4Z CA30 reserve for test

16
15
38 MIC2_R 2 1 2 1

6
UA3 RA29 RA31 1K_0402_5% 220P_0402_50V7K close to JMIC ACES_85204-0200N
100K_0402_5% 100K_0402_5% CA29 RA30 MIC@ @
Rin =70Kohm

VDD
PVDD1
PVDD2
MIC@

3
@ MIC@

2
7 2 DA3 @
CA26 0.033U_0402_25V7K RIN+ GAIN0 PSOT24C_SOT23
3

1
GAIN1

1
1
38 AMP_SPK_R LINE_C_OUTR 17 RA33
CA27 0.033U_0402_25V7K RIN- SPKR+ RA32 100K_0402_5%
ROUT+ 18
100K_0402_5% @

2
14 SPKR-

2
ROUT-
9
CA31 0.033U_0402_25V7K LIN+
4 SPKL+
Speaker Connector @ DA4 PJDLC05_SOT23-3
2
LOUT+
1
38 AMP_SPK_L LINE_C_OUTL 5 3
CA32 0.033U_0402_25V7K LIN- SPKL- JSPK
LOUT- 8 GAIN0 GAIN1 Av(db)Rin(ohm)
SPKL+ LA2 1 2 FBMA-L11-160808-800LMT_0603 SPK_L1 1
SPKL- LA3 1 FBMA-L11-160808-800LMT_0603 SPK_L2 1
0 0 6 90K 2 2 2
setting 68Hz SPKR+ LA4 1 2 FBMA-L11-160808-800LMT_0603 SPK_R1 3
SPKR- LA5 1 FBMA-L11-160808-800LMT_0603 SPK_R2 3
0 1 10 70K 2 4 4
F=1/2ʌRC --> -3db NC 12 Keep 10 mil width
1 0 15.6 45K @ DA5 PJDLC05_SOT23-3 ACES_85204-0400N
C=0.033U,R=70K,F=68Hz 10 AMP_BYPASS 3 @
BYPASS
38 MUTE# 19 SHUTDOWN 1 1 21.6 25K 1
2 2
GND5
GND1
GND2
GND3
GND4

CA33
0.47U_0603_10V7K
1
TPA6017A2_TSSOP20
21
20
13
11
1

HeadPhone/LINE Out JACK

JLINE
5

38 NBA_PLUG 4

LA6 1 2 HP_R_L 3
38 HP_R
KC FBM-L11-160808-121LMT 0603 6
LA7 1 2 HP_L_L 2
38 HP_L
KC FBM-L11-160808-121LMT 0603 1

1 FOX_JA6333L-B3T0-7F
+3VS 3 CA34 @

+3VS Volume Control 1

2
0.1U_0402_16V4Z
@
1

2
RA34 DA6 @
100K_0402_5% PJDLC05_SOT23-3
1

CA35 0.1U_0402_16V4Z
RA35 RA36 +3VS 1 2 For EMI request
2
5

SW1 10K_0402_5% 10K_0402_5% +3VS

1
DIP

1
2

CA36
Ext.MIC/LINE IN JACK
P

NC

2 1 2 2 4 0.1U_0402_16V4Z JEXMIC
A RA37 10K_0402_5% A Y 2
5
G

74LVC1G14GW_SOT353-5 UA5
1 UA4 1 14 4
38 MIC_SENSE
3

COM CD1# VCC

2 D1 CD2# 13
3 12 MIC1_R LA8 1 2 MIC1_L_R 3
CP1 D2 KC FBM-L11-160808-121LMT 0603
B 3 1 2 4 SD1# CP2 11 6
RA38 10K_0402_5% 5 10 MIC1_L LA9 1 2 MIC1_L_L 2
Q1 SD2# KC FBM-L11-160808-121LMT 0603
1 1 6 Q1# Q2 09 1 1
DIP

7 08 CA39
CA37 CA38 GND Q2# FOX_JA6333L-B3T0-7F
SW_XRE094_3P 0.01U_0402_16V7K 0.01U_0402_16V7K 74LCX74MTC_TSSOP14 3 1 CA40 1 1 @
4

2 2 2 0.1U_0402_16V4Z
1
2 @ CA41 CA42
120P_0402_50V8K @
0.1U_0402_16V4Z DA7 @ 2 @ 2 2
ENCODER_DIR 41
PJDLC05_SOT23-3
ENCODER_PULSE 41
120P_0402_50V8K
For EMI request

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 39 of 58
 5 4 3 2 1

RC3 0_0402_5%
2 1

+3VS_CR CC2 0.1U_0402_16V4Z

1 2
RC1 0_0603_5%
+3VS 1 2
UC1

1 CC3 0.1U_0402_16V4Z 1
CC1 AV_PLL
D 2 1 3 NC D
0.1U_0402_16V4Z 7 NC
+VCC_3IN1 9 CARD_3V3
2
11 D3V3
+3VS_CR 33 D3V3 VREG 10
MS_D4 22 1
30 CC4
NC
1 +3VS_CR 8 3V3_IN 1U_0402_6.3V4Z
1U_0402_6.3V4Z CC5 RST#_R 44
MODE SEL RST# 2
45 MODE_SEL
47 XTLO XD_CLE_SP19 43
+3VS_CR 2 XTLI 48 XTLI XD_CE#_SP18 42
XD_ALE_SP17 41
4 40 SD_DATA2
29 USB20_N10 DM SD_DAT2/XD_RE#_SP16
2

5 39 SD_DATA3
29 USB20_P10 DP SD_DAT3/XD_WE#_SP15
RC5 CR_LED# 14 38
100K_0402_5% GPIO0 XD_RDY_SP14 RC6
SD_DAT4/XD_WP#/MS_D7_SP13 37 1 2 22_0402_5% SDCLK
SD_DAT5/XD_D0/MS_D6_SP12 35
34 SD_MS_CLK RC7 1 2 22_0402_5% MSCLK
1

SD_CLK/XD_D1/MS_CLK_SP11 MS_DATA3_SD_DATA6
SD_DAT6/XD_D7/MS_D3_SP10 31
RC4 0_0402_5% 29 MSCD#
RST# RST#_R MS_INS#_SP9 MS_DATA2_SD_DATA7
2 1 SD_DAT7/XD_D2/MS_D2_SP8 28
27 SD_MS_DATA0
SD_DAT0/XD_D6/MS_D0_SP7 MS_DATA1
1 SD_DAT1/XD_D3/MS_D1_SP6 26
CC6 25 MSBS
1U_0402_6.3V4Z XD_D5_SP5 SD_DATA1
XD_D4/SD_DAT1_SP4 23
21 SDCD#
2 SD_CD#_SP3 SDWP#
SD_WP_SP2 20
XD_CD#_SP1 19
C 18 C

2
EEDI
13 XTAL_CTR
3 in 1 Card Reader
+3VS RREF XTAL_CTR
MS_D5 24
MODE SEL 12 DGND
32 DGND EEDO 15
1

EECS 16 confirm all pin define with connector spec.

RC8 6 17
120_0402_5% AGND EESK SDCMD
46 AGND SD_CMD 36
1

1
CC7 RC9 JREAD @
2

0.1U_0402_16V4Z 0_0402_5% Vf=2.0V(typ),2.4V(max) SDWP# 1 SD-WP

2
@ DC1 RTS5159-GR_LQFP48_7X7 SD_DATA1 2
2 HT-110UYG-CT_YEL/GRN RC10 RC11 SD_MS_DATA0 SD-DAT1
3
2

6.19K_0402_1% 0_0402_5% SD-DAT0

4 SD-GND
5 MS-GND
MSBS 6
1

1
SDCLK MS-BS
7 SD-CLK
MS_DATA1 8
CR_LED# SD_MS_DATA0 MS-DAT1
9 MS-DAT0
+VCC_3IN1 10 SD-VCC
MS_DATA2_SD_DATA7 11 MS-DAT2
1 1 12 SD-GND
CC8 CC9 MSCD# 13
1U_0402_6.3V4Z 0.1U_0402_16V4Z MS_DATA3_SD_DATA6 MS-INS
14 MS-DAT3
SDCMD 15
2 2 MSCLK SD-CMD
16 MS-SCLK
17 MS-VCC
SD_DATA3 18
B SD-DAT3 B
19 MS-GND
SD_DATA2 20 22
SDCD# SD-DAT2 GND1
48Mhz 21 SD-CD GND2 23
TAITW_R009-125-LR_RV

1 2 XTLI
22 CLK_48M_CR
RC12 0_0402_5%
R C USB AUTO DE-LINK MS FORMATTER Description
@ CC14 10P_0402_50V8J
0 NC YES Recommended
NC 47P YES YES
+3VS_CR 1 2 XTAL_CTR
RC13 0_0402_5% MSCLK 1 2
NC NC Compatible with RTS5158E @ RC14 10_0402_5% @ CC11 10P_0402_50V8J

NC 680P YES LED ON SDCLK 1 2

@ RC15 10_0402_5% @ CC13 10P_0402_50V8J
10K 180P LED ON
10K 680P YES
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 40 of 58
5 4 3 2 1
 5 4 3 2 1

+3VALW
+3VALW
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 2 2 C442
C436 1 2
C437 C438 C439 C440 C441
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2 2 1 1

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K

22
33
96

67
9
for EMI request U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
CLK_PCI_EC

1
D D
R377 1 21
30 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 22
@ 10_0402_5% 2 23
30 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# 38
25,42 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 1 2 H_PROCHOT# 5,53
4 27 R403 @ 0_0402_5%
25,42 LPC_FRAME# ACOFF 47
2

LFRAME# ACOFF/FANPWM2/GPIO13
1 25,42 LPC_AD3 5 LAD3
25,42 LPC_AD2 7 LAD2 PWM Output
C443 8 63 BATT_TEMPA
25,42 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 46
@ 22P_0402_50V8J BATT_TEMPA
2 25,42 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 1
C445
2
100P_0402_50V8J
ADP_I/AD2/GPIO3A 65 ADP_I 47
CLK_PCI_EC 12 AD Input 66 ACIN_D 1 2
29 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 47
13 75 C446 100P_0402_50V8J
5,13,29,36,37,42 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
ECRST# 37 76
+3VALW R378 ECRST# SELIO2#/AD5/GPIO43
30 EC_SCI# 20 SCI#/GPIO0E
47K_0402_5% 38
43 WL_BT_LED# CLKRUN#/GPIO1D
2 1 ECRST# 68
DAC_BRIG/DA0/GPIO3C DAC_BRIG 22
EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 6
2 1 DA Output IREF/DA2/GPIO3E 71 IREF 47
C444 0.1U_0402_16V4Z KSI0 55 72
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 47
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A +5VS
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 USB_EN# 34
+3VALW KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C ENCODER_DIR 39
KSI6 61 PS2 Interface 86 TP_CLK 1 2
KSI6/GPIO36 PSDAT2/GPIO4D ENCODER_PULSE 39
1 2 KSO1 KSI7 62 87 TP_CLK 4.7K_0402_5% R379
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 35
R380 47K_0402_5% KSO0 39 88 TP_DATA TP_DATA 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 35
1 2 KSO2 KSO1 40 4.7K_0402_5% R381
R382 47K_0402_5% KSO2 KSO1/GPIO21
41 KSO2/GPIO22
C KSO3 42 97 VGATE +3VALW C
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 27,53
to avoid EC entry ENE test mode KSO4 43 98
KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# 37,44
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 42 2 1
KSO7 46 SPI Device Interface 47K_0402_5% R383
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119
KSI[0..7] KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 42
KSO10 49 120
35 KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 42
KSO11 50 SPI Flash ROM 126
KSO[0..17] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 42
KSO12 51 128 SYSON 1 2
35 KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# 42
KSO13 52 R5 4.7K_0402_5%
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73
RP7 KSO16 KSO15/GPIO2F CIR_RX/GPIO40
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
+3VALW 1 8 EC_SMB_CK1 KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 47
2 7 EC_SMB_DA1 90
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# 43
+3VS 3 6 EC_SMB_CK2 91
CAPS_LED#/GPIO53 CAPS_LED# 35
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO 92
46 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# 43
EC_SMB_DA1 78 93
46 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# 43
2.2K_0804_8P4R_5% EC_SMB_CK2 79 SM Bus 95
21,26 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 36,51
EC_SMB_DA2 80 121
21,26 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 53 +3VALW
127 ACIN_D
AC_IN/GPIO59
1 2
6 100 R341 330K_0402_5%
27 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 27
27 PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# 26
15 102 D21
30 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 43
16 103 ACIN_D 2 1
LID_SW#/GPIO0A EC_SWI#/GPXO06 PWRME_CTRL 25 ACIN 27,43,45
27 PCH_SUSPWRDN 1 2 17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 PM_PWROK 27
B R402 @ 0_0402_5% CH751H-40PT_SOD323-2 B
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 22
49 VTTP_EN 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 XMIT_OFF# 36
30 THM_ALT# 25 EC_THERM#/GPIO11 GPXO10 107 3G_OFF# 36
6 FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108
29 FANFB2/GPIO15
36 E51_TXD 30 EC_TX/GPIO16
36 E51_RXD 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 27
R337 100K_0402_5% 32 112
43 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 VGA_ENBKL 14
1 2 VTTP_EN 34 114
43 PWR_SUSP_LED# PWR_LED#/GPIO19 GPXID3 USB_OC#3 29,34
35 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115
GPXID5 116 SUSP# 36,38,44,47,50,52,54
R342 100K_0402_5% 117
GPXID6 PBTN_OUT# 27
1 2 E51_TXD 118
GPXID7 USB_OC#0 29,34
CRY1 122
CRY2 XCLK1 +EC_V18R
123 XCLK0 V18R 124
AGND

R389
GND
GND
GND
GND
GND

CRY1 1 2CRY2 C448

4.7U_0805_10V4Z
@ 10M_0402_5% KB926QFD3_LQFP128_14X14
11
24
35
94
113

69

1 1
1

C449 C450
18P_0402_50V8J

Y4
18P_0402_50V8J
OSC

OSC

2 2
A A
NC

NC
2

Security Classification Compal Secret Data Compal Electronics, Inc.

32.768KHZ_12.5PF_Q13MC14610002 2009/01/23 2010/01/23 Title
Issued Date Deciphered Date
Schematic, LA5322P M/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 41 of 58
5 4 3 2 1
 SPI Flash (256KB) Lid SW LPC Debug Port
Socket: SP07000F500 & SP07000H900 Please place the PAD under DDR DIMM.
+3VALW It's for 16" using
U21 16@
+3VALW APX9132ATI-TRL_SOT23-3 H7
+3VS
2 3

GND
20mils VDD VOUT LID_SW# 41
1 6 5
C451 U22
8 4 1 1

1
0.1U_0402_16V4Z VCC VSS
25,41 SERIRQ 1 2 7 4 PLT_RST# 5,13,29,36,37,41
2 C453 C452 R392 0_0402_5%
3 W 0.1U_0402_16V4Z 10P_0402_50V8J
2 16@ 16@ 2
7 HOLD 25,41 LPC_AD3 8 3 LPC_AD2 25,41

41 SPI_CS# 1 S
25,41 LPC_AD1 9 2 LPC_AD0 25,41
41 SPI_CLK 6 C

41 EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO 41
+3VALW It's for 17" using 25,41 LPC_FRAME# 10 1 CLK_PCI_DDR 29
MX25L2005CMI-12G SO8 U23 17@

2
APX9132ATI-TRL_SOT23-3
@ DEBUG_PAD R393
2 3 LID_SW# 22_0402_5%

GND
VDD VOUT

1
1 1 2

1
C455 C456 C457
0.1U_0402_16V4Z 10P_0402_50V8J 22P_0402_50V8J
SPI_CLK 2 17@ 17@ 2 1
1 R394 2 1 2
10_0402_5% C454 10P_0402_50V8J

reserve for EMI, close to U22 reserve for EMI

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 42 of 58
 5 4 3 2 1

Power Button +3VALW

ISPD

2
R395
ON/OFFBTN#_R 35
ZZZ UV1 UV1
100K_0402_5%
D28

1
SW2 @ ON/OFFBTN#
1 3 ON/OFFBTN#_R 1
2 ON/OFFBTN# 41 PCB GPU
TOP side 3 1 2 51_ON# 45
D 2 4 1 R51 0_0402_5% PCB SKU LA-5322P M92-XTX M96 D
C458 CHN202UPT SC-70 M92XTX@ M96@
6 SMT1-05-A_4P 0.1U_0402_25V6
5

6
@ PJP1 U11
2 Q6A
SW3 @ 2N7002DW-T/R7_SOT363-6
1 3 2 another at page 44
DC-IN
41 EC_ON
16

2
BTM side 2 4 For EMI request

1
R396 PJP1 HM55
SMT1-05-A_4P 10K_0402_5% NSWAA45@ HM55R1@
6
5

PJP1

1
debug phase using

DC-IN
17 PJP1
NTWAA45@

Screw Hole
C H8 H9 H10 H11 H12 H13 H14 H15 C
ACIN 27,41,45
Vf=2.0V(typ),2.4V(max)
DC-IN LED If=30mA(max) POWER/SUSPEND LED
2

H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
D22 @ @ @ @ @ @ @ @
+3VALW 1 2 2 1 6 1
R397 120_0402_5%
HT-110UYG-CT_YEL/GRN Q35A H16 H17 H18 H24 H25 H26
2N7002DW-T/R7_SOT363-6 D23

2 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

PWR_SUSP_LED# 41

1
@ @ @ @ @ @
BATT CHARGE/FULL LED +3VALW 1
R398
2
120_0402_5%
1

Vf=1.9V(typ),2.4V(max) for amber 3 H19 H34 H23 Dummy

PWR_ON_LED# 41
Vf=2.0V(typ),2.4V(max) for green
If=30mA(max) HT-210UD/UYG_AMB/GRN H_3P0 H_4P1X3P1N H_3P1N

1
D24 @ @ @ H35 H33
2 BATT_CHG_LOW_LED# 41

+3VALW 1 2 1 H_3P0N H_3P0

1
R399 120_0402_5% @ @
3 H27 H28 H29 H32
BATT_FULL_LED# 41
CPU
HT-210UD/UYG_AMB/GRN H_3P7 H_3P7 H_3P7 H_3P7

1
@ @ @ @
B WL&BT LED D25 H31 H30
B

+3VS 1 2 2 1 WL_BT_LED# 41 MDC

R400 120_0402_5%
WLAN@ HT-110UD_1204_AMBER H_3P2 H_3P2

1
WLAN@ @ @

MINI CARD H36 H37 3G H38 H39

H_3P7 H_3P7 H_3P7 H_3P7

1
@ @ @ @

H20 H21 H22

VGA
H_3P0 H_3P0 H_3P0
SATA_LED# 25

1
@ @ @
2

HDD LED
2 R404 1 6 1
+3VS
10K_0402_5%
PCB Fedical Mark PAD
5

Q9A
D27 2N7002DW-T/R7_SOT363-6
+3VS 1 2 2 1 3 4 FD5 FD6 FD7 FD8
R405 120_0402_5%
HT-110UYG-CT_YEL/GRN Q9B 2N7002DW-T/R7_SOT363-6 @ @ @ @
A A

1
1 @ 2
R50 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 43 of 58
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS
4.7U_0805_10V4Z +1.5V +1.5VS
4.7U_0805_10V4Z
1 1 1 1 Vgs=10V,Id=14.5A,Rds=6mohm
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 1 1

470_0805_5%

470_0805_5%
8 1 8 1 Q31 C463 C464
D S D S

470_0805_5%
7 D S 2 7 D S 2 8 D S 1

2
2 2 R406 2 2 R407
6 D S 3 6 D S 3 7 D S 2
2 2 R408
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4
SI4800BDY_SO8 D G
1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB 1U_0402_6.3V4Z

3 1

3 1
0.022U_0402_25V7K

0.01U_0402_25V7K
47K_0402_5% 47K_0402_5% FDS6676AS_SO8 1 R411
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 2 +VSB

3 1
1

6
C466 220K_0402_5%

4.7U_0805_10V4Z
1 1

6
0.1U_0402_25V6
C465 R412 Q10A C467 C468 R413 Q11A FDS6676AS

C470
330K_0402_5% Q10B 200K_0402_5% Q11B C469 R414 Q12A
2 2 SUSP 2 2 @ SUSP 5 820K_0402_5% Q12B
2 5 2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 2 SUSP 5
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

2
2N7002DW-T/R7_SOT363-6

4
+3VALW TO +3V_LAN
+3VALW
+3VALW
+3VALW
2

Vgs=-4.5V,Id=3A,Rds<97mohm
R415
100K_0402_5% 2

2
C471 Q32

2
2 0.1U_0402_16V7K AO3413_SOT23 R425 @ 2
1

3
S
PJ24 100K_0402_5%

2
1 G
37,41 WOL_EN# 1 2 2 JUMP_43X79
R416 47K_0402_5% @ 0.75VR_EN# 52

1
1
D
1
1

C474
1

3
0.01U_0402_25V7K +3V_LAN @ Q44B
2N7002DW-T/R7_SOT363-6
2
5,49 VTTPWROK 1 @ 2 0.75VR_EN 5
1 1 R158 100K_0402_5%

4
6
C476 C477 1U_0402_6.3V4Z @ Q44A
4.7U_0805_10V4Z 2N7002DW-T/R7_SOT363-6
2 2
SUSP 2

1
Reserve for EMI request
3 3

+0.75VS +5VALW
+3VS
2

2
2 R421 R422
C473 47_0805_5% 100K_0402_5%
0.1U_0402_16V7K
@
1

1
1 SUSP
9,52 SUSP
3

3
Q6B
2N7002DW-T/R7_SOT363-6 Q5B
2N7002DW-T/R7_SOT363-6
5 SUSP 5
36,38,41,47,50,52,54 SUSP#
another at page43

2
4

4
R423
10K_0402_5%

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 44 of 58
A B C D E
 A B C D

VS
VIN PR1
PL1 VIN 1M_0402_1%
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2

1
1
PJP1 N1 PR3

1000P_0402_50V7K

1000P_0402_50V7K

680P_0402_50V7K
1 10A_125V_451010MRL PR2 5.6K_0402_5% PR4
+ 84.5K_0402_1% 10K_0402_1%

1
1 1

2 1 2 ACIN 27,41,43

2
+

PC1

PC3

@ PC68
PC2 PC4 PR5

8
3 100P_0402_50V8J 100P_0402_50V8J 22K_0402_1% PU1A

2
-
1 2 3

P
+ PACIN
- 4 O 1 PACIN 47
2 -

G
@ SINGA_2DW-0005-B03

1
PR6 LM393DG_SO8

4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%

2
2

2
2 1 RTCVREF
PR8
VIN 10K_0402_1%
3.3V Vin Detector

2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976

1
BATT+ 2 1

1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11

2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS 1 2 2

PR12
1

1K_1206_5%
1

1
PC8 PD4
PR13 PC7 0.1U_0603_25V7K 2 1 N3 1 2
100K_0402_1% 0.22U_0603_25V7K VIN B+
2

2
RLS4148_LL34-2 PR14
2

1K_1206_5%
43 51_ON# 1 2
PR15 1 2
22K_0402_1%
RTC Battery PR16
1K_1206_5%

1
RTCVREF
1

PR19 PR20
PR17
200_0603_5%
- PBJ1 + VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR18
499K_0402_1%
PR21 PR22 PU2 G920AT24U_SOT89-3 2 1 +RTCBATT
3.3V +RTCBATT

2
560_0603_5% 560_0603_5%
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN PD5

8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1

GND
2 5

P
48 EN0 +
PC9 PC10 1 7
10U_0805_10V4Z 1 O
47 ACON 3 6 2 1 RTCVREF
2

1
G
1U_0805_25V4Z
SP093MX0000

1
LM393DG_SO8 PR23 PR24 PC11

1
10K_0402_1% 499K_0402_1% 1000P_0402_50V7K

1
PR26

2
PC12 @ PR25
@PR25 191K_0402_1%

2
3 3

PJ9 1000P_0402_50V7K 66.5K_0402_1%

2
1
2 1

2
PJ1 2 1 PC13
+3VALWP 2 1 +3VALW @ JUMP_43X118 1000P_0402_50V7K

2
2 1
@ JUMP_43X118 PJ2
(5A,200mils ,Via NO.= 10) +1.5VP 2 1 +1.5V PR27
2 1

1
D 47K_0402_1%
OCP(min)=7.7A @ JUMP_43X118 PQ2
2 2 1 PACIN
SSM3K7002FU_SC70-3
G
(15A,600mils ,Via NO.= 30) S

3
PJ4
+5VALWP 2 2 1 1 +5VALW OCP(min)=18.14A

1
@ JUMP_43X118 PJ5
(5A,200mils ,Via NO.= 10) 2 2 1 1

OCP(min)=7.9A @ JUMP_43X118 PJ14 2 +5VALWP

+1.1VSP 2 2 1 1 +1.1VS
PJ8
PJ7
@ JUMP_43X79 PQ3
+VSBP 2 1 +VSB
+VTTP 2 2 1 1 +VTT
(2A,80mils ,Via NO.= 4) Precharge detector DTC115EUA_SC70-3

3
2 1 @ JUMP_43X118
@ JUMP_43X39 (18A,720mils ,Via NO.=36)
15.97V/14.84V FOR
+1.05VSP
PJ11
+1.05VS
ADAPTOR
(120mA,40mils ,Via NO.= 1) OCP(min)=20.64A 2 2 1 1

PJ13 @ JUMP_43X79
2 2 1 1 (7.0A,280mils ,Via NO.=14)
PJ10
+0.75VSP 2 1 +0.75VS @ JUMP_43X118 OCP(min)=8.4A
4 2 1 4

@ JUMP_43X79
(1.5A,60mils ,Via NO.= 4) PJ16
+VGA_COREP 2 2 1 1 +VGA_CORE
@ JUMP_43X118
PJ15
+1.8VSP 2 2 1 1 +1.8VS (26A,1040mils ,Via NO.=52) Security Classification Compal Secret Data Compal Electronics, Inc.
@ JUMP_43X79 OCP(min)=20.14A(M92) 2009/01/23 2010/01/23 Title
Issued Date Deciphered Date
(4A,80mils ,Via NO.= 8) Schematic, LA5322P M/B
OCP(min)=28.65A(M96) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OCP(min)=4.9A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 45 of 58
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
1 1

For 16" VMB VL

PF2 PL2 VL ENTRIP1 48
PJP2 15A_65V_451015MRL SMB3025500YA_2P VL
1 BATT_S1 1 2 1 2
1 BATT+
2 2

2
3 BATT_P3 1 2 1 2
3 +3VALWP
4 BATT_P4 PR28 PR29 PR30
4

1
BATT_P5 1K_0402_1% 47K_0402_1% 47K_0402_1% D
5 5
10 6 EC_SMDA PC14 PC15 PC16 2 PQ4
GND 6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K PH1 0.1U_0603_25V7K PR31 G SSM3K7002FU_SC70-3
11 7

1
GND 7 47K_0402_1%
12 8 S

3
GND 8

1
13 9 100K_0402_1%_TSM0B104F4251RZ 1 2

2
GND 9 PR32 PR33

8
@ SUYIN_200045MR009G171ZR 1K_0402_1% 12.4K_0402_1% PU3A
1 2 3

P
+
1 2 1

2
TM_REF1 O ENTRIP2 48
2 -

G
PD6
@ PD15
@PD15 LM393DG_SO8 RLS4148_LL34-2

4
1

For 17" PJSOT24C_SOT23-3

0.22U_0805_16V7K
@PD14
@ PD14 2
PJP3 PJSOT24C_SOT23-3 1

1
D

15.8K_0402_1%
1 BATT_S1 3
1

1
PC17
2 PR36 2 PQ5
2

1000P_0402_50V7K
PR37
3 BATT_P3 6.49K_0402_1% G SSM3K7002FU_SC70-3
2

3 BATT_P4
4 2 1 +3VALWP 2 1 VL S

3
4

1
5 BATT_P5
5

PC18
10 6 EC_SMDA PR38

2
GND 6 EC_SMCA 100K_0402_1%
11 7

2
GND 7
1

12 GND 8 8

1
13 9 PR39
2 GND 9 1K_0402_1% 2

@ SUYIN_200045MR009G171ZR PR40
100K_0402_1%
2
2

2
PR34 PR35
BATT_TEMPA 41
100_0402_1% 100_0402_1%
1

EC_SMB_DA1 41

EC_SMB_CK1 41
PH2 near main Battery CONN :
BAT. thermal protection at 90 degree C
Recovery at 55 degree C

VL VL

PQ6

2
TP0610K-T1-E3_SOT23-3

1
PR41
47K_0402_1%
B+ 3 1 +VSBP PH2 PR42
47K_0402_1%

1
3 3
100K_0402_1%

0.22U_1206_25V7K

0.1U_0603_25V7K

100K_0402_1%_TSM0B104F4251RZ 1 2

2
1

1
PR43

PC19

PC20

PR44

8
12.1K_0402_1% PU3B
@ @ 1 2 5

P
2

+
7 2 1
2

TM_REF1 O
6 -

G
VL PR45 PD7

1
22K_0402_1% LM393DG_SO8 RLS4148_LL34-2

4
1 2 PC21 PR46
2

0.22U_0805_16V7K 16.9K_0402_1%

2
PR47

2
100K_0402_1%

PR48
1

0_0402_5% D
1 2 2 PQ7
48 POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K

S
3
1

@ PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 46 of 58
A B C D
 A B C D

B+
AO4407A_SO8 PQ10
1 8
@PC188
@ PC188 2 7
P2 P3 B+ 0.1U_0603_25V7K
1 2 CHG_B+
3 6
5
PQ8 AO4407A_SO8 PQ9 AO4407A_SO8 PR49 0.015_2512_1% PJ17
VIN 8 1 1 8 1 4 2 1

4
2 1
7 2 2 7

470P_0402_50V7K
0.1U_0603_25V7K

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
6 3 3 6 2 3 @ JUMP_43X118 CSIN
5 5 AO4407A_SO8 PQ11
1 8
CSIP 2 7

4
1
1 1

3 6

1
PQ12 TP0610K-T1-E3_SOT23-3 5

3
PQ13 PR50 PR196 10_0603_5%

2
DTA144EUA_SC70-3 200K_0402_1% 3 1 1 2 DCIN

4
PC26 P3

2
1

PC144

PC182

PC23

PC24

PC25
2 5600P_0402_25V7K PR52

1
PC27 PR53 PQ14 47K_0402_1%

1
PR51 0.1U_0603_25V7K 100K_0402_1% DTC115EUA_SC70-3 1 2

2
47K_0402_1% VIN

2
PR54 PD8
2

2
100K_0402_1% 2 FSTCHG PR55 PD9
1

2
1

PD10 2 1 2 1 10K_0402_1% 1 2 ACOFF

1SS355_SOD323-2 3
1 2 6251VDD SUSP# 36,38,41,44,50,52,54 1SS355_SOD323-2

1
2.2U_0603_6.3V6K
RB715F_SOT323-3 PR57

PC28
2 PR56 200K_0402_1%

3
1

1
PQ15 10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 2 1 PU5 PC30
41 FSTCHG 0.1U_0603_25V7K

2
1

100K_0402_1%
1 2 1 24 DCIN 2 1 PQ17 PD11
3

VDD DCIN
1

1
2 PQ16 DTC115EUA_SC70-3 2 1 2

PR58
G SSM3K7002FU_SC70-3 PC29
S PR59 .1U_0402_16V7K 2 23 1SS355_SOD323-2
3

150K_0402_1% ACSET ACPRN PR60

20_0603_5%
2

1
6251_EN CSON D
3 EN CSON 22 1 2

1
@ PC33
@PC33 PC31 PC32 2 PACIN

5
6
7
8
680P_0402_50V7K 0.047U_0603_16V7K 0.1U_0603_25V7K G
CSON 1 2 4 21 1 2 S PQ18

3
CELLS CSOP PR61 PQ19 SSM3K7002FU_SC70-3
PC34 6800P_0402_25V7K 20_0603_5% AO4466_SO8
2 2
1 2 5 ICOMP CSIN 20 2 1
1

2
D PR62 4
2 PQ20 PC36 PR63 6.81K_0402_1% PC35 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2

1
VCOMP CSIP PL3 PR66
S
3

0.01U_0402_25V7K 1 2 PR65 47K_0402_1% PR64 10U_LF919AS-100M-P3_4.5A_20% 0.02_2512_1% BATT+

3
2
1
PR67 1 2 7 18 LX_CHG 2.2_0603_1% 1 2 CHG 1 4
ICM PHASE

4.7_1206_5%
22K_0402_5% @PC37
@ PC37 100P_0402_50V8J

5
6
7
8

AO4466_SO8

PR220
PACIN 1 2 1 2 2 3
45 PACIN

10U_1206_25V6M

10U_1206_25V6M
PC38 6251VREF 8 17 DH_CHG
PR68 .1U_0402_16V7K VREF UGATE PR69 PC39
45 ACON 41 ADP_I
154K_0402_1% 0_0603_5% 0.1U_0603_25V7K

1
PC40

PC41
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
41 IREF CHLIM BOOT
1

1
PQ22 PR70 4

680P_0603_50V8J
0.01U_0402_25V7K

DTC115EUA_SC70-3 53.6K_0402_1% PD12

2
PQ21

PC169
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1

1
PC42

ACOFF 2 PR71 1 26251VDD

41 ACOFF

3
2
1
120K_0402_1% PR72 11 14 DL_CHG
VADJ LGATE

2
20K_0402_1% PR73
2

4.7_0603_5%
2

12 13 PC43
3

1
GND PGND 4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24

PR74
15.4K_0402_1%
Iada=0~4.737A(90W) CP= 92%*Iada; CP=4.36A 41 CHGVADJ
1 2
1

3 Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A PR75 3

31.6K_0402_1%
VIN
2

CP mode

1
Vaclim=0.736V(90W) PR70=53.6k PR49=0.015 PR76
309K_0402_1%

Vaclim=1.08V(65W) PR70=75k PR49=0.02

2
PR98 10K_0402_1%
1 2 ADP_V 41
1

1
@PD13
@ PD13 PR77
GLZ4.3B_LL34-2 47K_0402_1% PC44
.1U_0402_16V7K

2
2

CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge Vcell CHGVADJ
IREF=0.254V~3.048V 4V 0V
VCHLIM need over 95mV 4.2V 1.882V
4
4.35V 3.2935V 4

CELLS VDD GND Float

CELL number 4 3 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 47 of 58
A B C D
 5 4 3 2 1

2VREF_51125

1U_0603_10V6K
D D

1
PC45

2
PR78 PR79
13K_0402_1% 30K_0402_1%
1 2 1 2

PR80 PR81
B++
20K_0402_1% 19.1K_0402_1%
B++
1 2 1 2

PJ18
B+ 2 2 1 1 +3VLP
PC46 2200P_0402_50V7K

ENTRIP2

ENTRIP1
0.1U_0603_25V7K

JUMP_43X118 PR82 PR83

10U_1206_25V6M

10U_1206_25V6M
150K_0402_1% 150K_0402_1%
1

2200P_0402_50V7K
@ 1 2 1 2

1
PC47

PC49
PC48
4.7U_0805_10V6K
2

2
6

5
6
7
8
PC50
PU6

8
7
6
5

1
C C

ENTRIP2

VREF

ENTRIP1
VFB2

TONSEL

VFB1
PC183

25 PQ24
PQ23 P PAD AO4466_SO8

2
AO4466_SO8
@ 7 24 POK 46 4
VO2 VO1
4
8 23 PC52
PR84 VREG3 PGOOD PR85 .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
0_0603_5% VBST2 VBST1 0_0603_5%
1
2
3

PL4 PC51 UG_3V 10 21 UG_5V PL5

4.7U_LF919AS-4R7M-P3_5.2A_20% .1U_0402_16V7K DRVH2 DRVH1 4.7U_LF919AS-4R7M-P3_5.2A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
1

8
7
6
5

5
6
7
8

1
4.7_1206_5%

4.7_1206_5%
LG_3V 12 19 LG_5V
DRVL2 DRVL1
PR86

PR87
SKIPSEL
PQ25 PQ26

VREG5
EN0 45
220U_6.3V_M

220U_6.3V_M
VCLK
@ AO4712_SO8 AO4712_SO8 @
Ipeak=5A 1

GND
1

EN0

VIN
2

2
Imax=3.5A + +
PC53

PC54
4 4
PR88 TPS51125RGER_QFN24_4X4
F=305kHZ

13

14

15

16

17

18
1

1
680P_0603_50V8J

680P_0603_50V8J
499K_0402_1%
2 2
PC55

PC56
Total capacitor B+ 1 2
2

1
2
3

3
2
1

2
1
100K_0402_5%
220u @ @

1
1U_0402_6.3V6K
ESR=15m ohm

PR89
1 2 VL
PC87

PC57
4.7U_0805_10V6K
@ PR90

2
B 0_0402_5% B

Ipeak=5A

2
ENTRIP1 46 ENTRIP2 46 Imax=3.5A
B++
F=245kHZ

0.1U_0603_25V7K
Total capacitor

2
PC58
220u
1

D D
2VREF_51125
PQ27 2 2 PQ28 ESR=15m ohm
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

VL 2 1

PR91
100K_0402_1%
1

VS 1 2 2 PQ29
G SSM3K7002FU_SC70-3
49.9K_0402_1%

0.01U_0402_16V7K

PR92 S
3
1

100K_0402_1%
1
PR93

PC59

A A

@
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 48 of 58
5 4 3 2 1
 A B C D

1 PL6 1

B+ HCB4532KF-800T90_1812

2 1 +VTTP_B+

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
+VTTP_VCC
1

1
PC85
PC189

PC186 PR94
5,44

PC60

PC61

PC62
6.81K_0402_1% PR95 2.2_0603_1%
2

2
@ @ @ VTTPWROK 1 2 1 2

BST_+VTTP
PC63

DH_+VTTP
LX_+VTTP
1 2 0.1U_0603_25V7K
+5VALW
PR101 2K_0402_1%

DH_+VTTP

5
PR96
0_0402_5% PR97 PQ30
Ipeak=18A

16

15
8

1
PU7 4.7_0603_5%
1 2 TPCA8030-H_SOP-ADV8-5 Imax=12.6A

PHASE

BOOT
UG
GND

PGOOD
+VTTP_VCC

2
4 F=231.5kHZ
3 VIN PVCC 14 1 2 PC64 Total capacitor 990u
+VTTP_VCC 2.2U_0603_6.3V6K
ESR=2.25m ohm

3
2
1
4 13 DL_+VTTP PL7
VCC LG 1.0UH_PCMC104T-1R0MN_20A_20%
1

PC65 1 2
2

2.2U_0603_6.3V6K
+VTTP 2

APW7138NITRL_SSOP16
12
2

PGND

330U_D2E_2.5VM_R9M
TPCA8028-H_SOP-ADVANCE8-5
1

1
PQ31
+

PC67
PR100
5 11 SE_+VTTP 1 2 4.7_1206_5%
EN ISEN PR99
4.99K_0402_1% 2

FSET

2
NC

VO
FB
4

680P_0603_50V8J
.1U_0402_16V7K

1
1 2
41 VTTP_EN
6

10
1

PC70
PR102
0_0402_5%

3
2
1

2
PC69

+VTTP
FB_+VTTP
2

Material Note:
33.2K_0402_1%

0.01U_0402_16V7K
1

1
330uF/ 6mohm, number are 3,
1
PR103

57.6K_0402_1%
PR104

power x1, HW x2
@ PC71
2
1

2200P_0603_50V7K
2

H_VTTVID1= Low, 1.1V PC72

33P_0402_50V8J
H_VTTVID1= High, 1.05V
2

1
PC73
2

3 3

1 2 1 2+VTTP
PR106 PR107
+3VS 3.32K_0402_1% 0_0402_5%
2

+3VS
180K_0402_1%

@ PR105
@ PR291

40.2K_0402_1% PR108 1 2
VTT_SENSE 8
2

4.42K_0402_1% PR109 PJ23

100K_0402_5%

10_0402_5% +VTTP 2 1 +1.05VS

1

2 1
@ PR294

1 2
VSS_SENSE_VTT 8
2N7002W-T/R7_SOT323-3

@ PR293 PR110 @ JUMP_43X79

2

4.7K_0402_5% D 10_0402_5% (7.0A,280mils ,Via NO.=14)

1

@ PQ56

1 2 2
G
S
3
1
1

1
.1U_0402_16V7K

1 2 2
8 H_VTTSELECT
@ PC229
0.01U_0402_16V7K

@ PR292
3

2
PMBT2222A_SOT23-3
@ PQ55

10K_0402_5%
100K_0402_5%

1
@ PC228
@ PR290

2
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 49 of 58
A B C D
 A B C D

PJ19
1.05V_B+ 2 1 B+
2 1

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K
@ JUMP_43X118

1
1 1

@ PC74

@ PC75

PC184

PC83
Ipeak=7A

5
6
7
8
@ PQ32
@PQ32 Imax=4.9A

2
AO4466_SO8 @ @
F=315kHZ
@PR111
@ PR111 Total capacitor 660u
255K_0402_1% 4 ESR=5m ohm
1 2
@ PR112
@PR112
0_0402_5% @ PR113 2.2_0603_1%
@PR113
SUSP# 1 2 BST_1.05V1 2

3
2
1
1
@ @PL8
@ PL8

15

14
PC77

1
@PC76
@PC76 @PU8
@ PU8 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K 1 2 1 2

EN_PSV

TP

VBST
+1.05VSP

4.7_1206_5%
2 13 DH_1.05V 0.1U_0603_25V7K
TON DRVH

@ PR114
@PR115
@ PR115 3 12 LX_1.05V
VOUT LL

5
6
7
8

220U_6.3V_M
100_0603_1% 1
1 2 4 11 1 2 +5VALW

D
D
D
D
+5VALW V5FILT TRIP

@ PC78
@PR116
@ PR116 +

2
5 10 10K_0402_1% @ PQ33
@PQ33
VFB V5DRV FDS6670AS_NL_SO8

1
2

680P_0603_50V8J
6 9 DL_1.05V 4 G
PGOOD DRVL

PGND

@ PC80
@PC79
@ PC79

GND
4.7U_0603_6.3V6K @ PC81
@PC81

2
1

S
S
S
47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 @PC82
@PC82

3
2
1
2 4.7U_0805_10V6K 2

2
@PR117
@ PR117
4.02K_0402_1%
1 2
1

@ PR118
@PR118
10K_0402_1%
2

PJ21
1.8VSP_B+ 2 1 B+
2 1

2200P_0402_50V7K
4.7U_1206_25V6K

4.7U_1206_25V6K

0.1U_0603_25V7K
@ JUMP_43X118

1
PC173

PC174

PC187

PC86
5
6
7
8

2
PQ53 @ @
AO4466_SO8

3
PR246 3

255K_0402_1% 4
1 2
PR247
30K_0402_5% PR248 2.2_0603_1%
36,38,41,44,47,52,54 SUSP# 1 2 1 2

3
2
1
1

PL17
15

14

PC176
1

PC175 PU9 4.7U_LF919AS-4R7M-P3_5.2A_20%

.1U_0402_16V7K BST_1.8VSP 1 2 1 2
EN_PSV

TP

VBST

+1.8VSP
2

2 13 DH_1.8VSP 0.1U_0603_25V7K
TON DRVH

4.7_1206_5%
Ipeak=4A

PR251
PR249 3 12 LX_1.8VSP
VOUT LL

5
6
7
8
Imax=2.8A

220U_6.3V_M
100_0603_1% 1
+5VALW 1 2 4 11 1 2 +5VALW PQ54
V5FILT TRIP F=315kHZ

PC181
PR250 AO4712_SO8 +

2
5 10 9.1K_0402_1%
VFB V5DRV Total capacitor 220u
1

1
2

680P_0603_50V8J
6 9 DL_1.8VSP 4 ESR=15m ohm
PGOOD DRVL
PGND

PC180
PC177
GND

4.7U_0603_6.3V6K @ PC178
2

2
1

47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC179
7

3
2
1
4.7U_0805_10V6K
2

PR252
14K_0402_1%
1 2
1

4 4

PR253
10K_0402_1%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 50 of 58
A B C D
 5 4 3 2 1

B+
1 2 B+_1.5V

PC84 2200P_0402_50V7K
0.1U_0603_25V7K
PL9 LX_1.5V
HCB4532KF-800T90_1812

10U_1206_25VAK

4.7U_0805_25V6-K
1.5V_VCC

10U_1206_25VAK
DH_1.5V

1
PC90
PR122

PC88

PC89
10K_0402_1% 1 2 1 2
BST_1.5V

2
PR123 PC91
0_0603_5% 0.1U_0603_25V7K

2
PC185
D D
+5VALW
@ @

5
PR124
0_0603_5% PQ34

21.5V_VCC
Ipeak=15A

16

15
1

2
8

1
PU10 Imax=10.5A
PR125 4

PHASE

BOOT
GND

PGOOD

UG
4.7_0603_5% F=231.5kHZ
2 PC92
Total capacitor 1210u

2.2U_0603_6.3V6K
3 VIN PVCC 14 1

PC93
1.5V_VCC TPCA8030-H_SOP-ADV8-5 ESR=2.73m ohm

3
2
1
2.2U_0603_6.3V6K

1
PL10
4 13 DL_1.5V +1.5VP
VCC LG 0.9UH_MMD-10DZ-R90M-D1_25A_20%
2
1 2
APW7138NITRL_SSOP16

1
TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
PGND 12
@ PR126
4.7_1206_5%

220U_6.3V_M
10U_1206_25VAK
PR128 1

PQ36

1
+

PC95
1 2 5 11 ISEN_1.5V 1 2

1 2
36,41 SYSON EN ISEN

@ PQ35

PC94
4 4

680P_0603_50V8J
0_0402_5% PR127

FSET

2
2

PC96
4.7K_0402_1%

NC

VO
FB
1

.1U_0402_16V7K

2
PC97

C C

10

3
2
1

3
2
1
@
2

57.6K_0402_1%
1

1
1

1
PR129

2
PR130
PC98 49.9K_0402_1% @PC99
@ PC99
22P_0402_50V8J 0.01U_0402_25V7K
2

2
PR131

2
4.87K_0402_1%
1

1
PC100
2200P_0402_25V7K
2

1
PR132

3.24K_0402_1%

2
B B

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23
Schematic, LA5322P M/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 51 of 58
5 4 3 2 1
 A B C D

+1.5V

1
PJ25

1
@ JUMP_43X79
1 1

2
2
PU11
1 VIN VCNTL 6 +5VALW

10U_0805_10V4Z
4.7U_0805_6.3V6K
2 GND NC 5

1
3 VREF NC 7

1
PC101

PC102
PR134 PR133 PC103
4 8

2
0_0402_5% 1K_0402_1% VOUT NC 1U_0603_10V6K

2
1 2 @ 9
9,44 SUSP

2
TP
G2992F1U_SO8

2N7002KW_SOT323-3

0.1U_0402_10V7K
@ PR135
+0.75VSP

1
D

PQ37
0_0402_5%
1 2 2 PR136
44 0.75VR_EN# G 1K_0402_1%

1
S

3
1
PC105

PC104
@ PC106 10U_0805_6.3V6M

2
.1U_0402_16V7K

2
2 2

+1.5V

+5VALW

1
PJ20

1
@ JUMP_43X79

2
2

1
PC107
1U_0603_6.3V6M

2
1

PC108
4.7U_0805_6.3V6K PU12
6
2

VCNTL
3 5 VIN VOUT 3 +1.1VSP 3

PR137 9 4
VIN VOUT

22U_0805_6.3V6M

22U_0805_6.3V6M
0.01U_0402_25V7K
10K_0402_5%

1
1 2 8 PR138
36,38,41,44,47,50,54 SUSP# EN

PC109

PC110

PC111
7 2 1K_0402_1%
POK GND FB

2
1

2
PC112 APL5930KAI-TRG_SO8 @
1

.1U_0402_16V7K
2

1
PR139
2.61K_0402_1%

PR140

2
4.7K_0402_5%
+3VS 1 2

16 PCIE_OK

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 52 of 58
A B C D
 8 7 6 5 4 3 2 1

CPU_VID0 2 1 PR229 1K_0402_1% CPU_VID0 2 1 @ PR230 1K_0402_1% +CPU_B+

PL11
CPU_VID1 2 1 PR231 1K_0402_1% CPU_VID1 2 1 @ PR232 1K_0402_1% HCB4532KF-800T90_1812
1 2 B+
CPU_VID2 2 1 PR233 1K_0402_1% CPU_VID2 2 1 @ PR234 1K_0402_1%

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
CPU_VID3 CPU_VID3

470P_0603_50V8J
PR141 0_0402_5% 1@ PR235 1K_0402_1% PR236 1K_0402_1%

0.1U_0603_25V7K
2 2 1

220U_25V_M
H 8 CPU_VID0 1 2 1 1 H

100U_25V_M
PR142 0_0402_5% CPU_VID4 2 1@ PR237 1K_0402_1% CPU_VID4 2 1 PR238 1K_0402_1%

1
+ +

PC114

PC115

PC116

PC172

PC171

@ PC190
8 CPU_VID1 1 2

PC113
PR143 0_0402_5% CPU_VID5 2 1 PR239 1K_0402_1% CPU_VID5 2 1 @ PR240 1K_0402_1%
8 CPU_VID2 1 2

2
5
PR144 0_0402_5% CPU_VID6 CPU_VID6 2 @ 2
2 1@ PR241 1K_0402_1% 2 1 PR242 1K_0402_1%
1 2 PQ39
8 CPU_VID3
PR145 0_0402_5% H_DPRSLPVR 2 1 PR243 1K_0402_1% H_DPRSLPVR 2 1 @ PR244 1K_0402_1%
1 2 TPCA8030-H_SOP-ADV8-5
8 CPU_VID4
PR146 0_0402_5% H_PSI# 2 1 PR245 1K_0402_1%
8 CPU_VID5 1 2 4
PR147 0_0402_5%
1 2 +VTT
8 CPU_VID6
PC117

3
2
1
PR148 2.2_0603_1% 0.22U_0603_25V7K
PR149 0_0402_5% BOOT2 1 2 BOOT2_2 1 2
1 2 PL12
41 VR_ON
UGATE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
G PR150 0_0402_5% G
1 2 PHASE2 4 1 +CPU_CORE
8 H_DPRSLPVR
3 2 V2N
22 CLK_ENABLE#

10K_0402_5%
PR151
4.7_1206_5%
@ PQ40

TPCA8028-H_SOP-ADVANCE8-5

1
PQ41

3.65K_0805_1%
+3VS PR155 TPCA8028-H_SOP-ADVANCE8-5 PR154

PR152

PR153
1.91K_0402_1% 1_0402_5%
1 2 CLK_ENABLE# @ PR156
LGATE2 4 4 0_0402_5%

2
2

1 2 V1N
PR157
1.91K_0402_1% @ PR158
PR159 VSUM+ 0_0402_5%

3
2
1

3
2
1

1
V3N

680P_0603_50V8J
0_0402_5% 1 2
27,41 VGATE
1

PC118
1 2 VSUM-

2
@ PR160 1K_0402_1%
F
1 2 ISEN2 F
+VTT
PR161 0_0402_5%
8 H_PSI# 1 2
PR162
1 2 ISL62883HRZ-T_QFN40_5X5~D +CPU_B+
147K_0402_1%
+5VALW +5VALW

10U_1206_25V6M

10U_1206_25V6M
PC119

0.1U_0603_25V7K
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

+VTT 1 2

1
@ PC125

@ PC120
PU14 1 2

1
@ PC121
1U_0603_10V6K
PR163 68_0402_5% @ PQ42
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

5,41 H_PROCHOT#

2
1 2 @ PR165 @ PC123

2
1

@ PC122
30 PR164 0_0603_5% 0.22U_0603_25V7K TPCA8030-H_SOP-ADV8-5

2
PR166 0_0402_5% BOOT2 PU13
UGATE2 29 0_0402_5%
1 28 5 1 BOOST_CPU31 2 1 2 4

2
@ PC124 56P_0402_50V8 PGOOD PHASE2 VCC BOOT
2 27

1
PSI# VSSP2 UGATE_CPU3
1 2 3 RBIAS LGATE2 26 6 FCCM UGATE 8
H_PROCHOT#_R 4 25 @ PL13
@ PR167 4.02K_0402_1% VR_TT# VCCP PHASE_CPU3 0.36UH_PCMC104T-R36MN1R17_30A_20%
5 24 2 7

3
2
1
E NTC PWM3 PWM PHASE E
1 2 2 1 6 VW LGATE1 23
7 22 3 4 LGATE_CPU3 4 1 +CPU_CORE
@ PH3 COMP VSSP1 GND LGATE
8 FB PHASE1 21
470KB_0402_5%_ERTJ0EV474J 1 2 9 @ ISL6208CRZ-T_QFN8 3 2 V3N
ISEN3
UGATE1

PR169
4.7_1206_5%
10 PR168 0_0402_5%
BOOT1
ISUM+

ISEN2

1
ISEN1

ISUM-
VSEN
249K_0402_1%

IMON
1000P_0402_50V7K
8.06K_0402_1%

1U_0603_10V6K

PC126 1 2

TPCA8028-H_SOP-ADVANCE8-5
VDD
RTN

1
VIN

3.65K_0805_1%
22P_0402_50V8J 41 @ PR170
AGND
1

1
PQ43
PC127

PC128

@ PQ44 @ @ PR174 1_0402_5%

PR172

PR171

TPCA8028-H_SOP-ADVANCE8-5 10K_0402_5%
11
12
13
14
15
16
17
18
19
20

PR176
2

2
@ PR173
562_0402_1% PC130 4 4 @ @ PR175

2
@ 1 2 1 2 0_0402_5%
2

2
1
2V1N

680P_0603_50V8J
1

PC129
390P_0402_50V7K
PR178 PR177 0_0402_5% @ PR179 VSUM-

3
2
1

3
2
1

2
2.43K_0402_1% 1 2 0_0402_5%
1 2 1 2 @ 1 2 V2N
8 IMVP_IMON
PC131 PR180 0_0402_5%
D 10P_0402_50V8J 1 2 +CPU_B+ D
0.22U_0603_25V7K

1 2 1 2 @ PR221 0_0402_5% VSUM+

1 2 PR184 1_0402_5% ISEN3
ISEN3
PC132 PR181 1 2 +5VALW +CPU_B+
150P_0402_50V8J 412K_0402_1%
PC170 0.22U_0402_6.3V6K

PC133 0.22U_0402_6.3V6K

PC134 0.22U_0402_6.3V6K

ISEN2 1 2
1

1
PC135

PC136

PC137
1U_0603_10V6K

0.22U_0603_25V7K

PR182 0_0402_5%
ISEN1 1 2 PR185
2

470P_0603_50V8J
8.25K_0402_1%
BOOT1
1

10U_1206_25V6M

10U_1206_25V6M
Layout Note: PR183 0_0402_5%
2

PQ45
PH3 place near

1
PC138
VSSSENSE
2

PC139

PC140
Phase1 L-MOS TPCA8030-H_SOP-ADV8-5

2
VSUM+ UGATE1 4
VSUM-

82.5_0402_1%

+CPU_CORE 1 2 @
PC141
1

@ PR186 10_0402_5% PR188 2.2_0603_1% 0.22U_0603_25V7K

0.047U_0402_16V7K

C C

3
2
1
1
PR187

2.61K_0402_1%

2 BOOT1_1 1
0.22U_0603_10V7K

1 2
PR189

PL14
10K_0603_1%_TSM1A103F34D1RZ

0.36UH_PCMC104T-R36MN1R17_30A_20%
1

1
PC142

PC143
0.01U_0402_25V7K

8 VCCSENSE 1 2
2

PHASE1 4 1 +CPU_CORE
2

PR190 0_0402_5%
2

2
1

3 2 V1N
1

5
PC145 PQ46

TPCA8028-H_SOP-ADVANCE8-5
@ PQ47
PC146

4.7_1206_5%
330P_0402_50V7K
2

1
10K_0402_5%
PR191

3.65K_0805_1%
TPCA8028-H_SOP-ADVANCE8-5
2

1
PR194
1_0402_5%

PR193
330P_0402_50V7K

LGATE1 4 4
1

2
11K_0402_1%

PR192
PR195 @ PR198

2
1

PH4
PC148

PR197

PC147 1.2K_0402_1% 0_0402_5%

2
1000P_0402_50V7K 1 2 1 2 V2N
PR199 0_0402_5%
2

3
2
1

3
2
1

680P_0603_50V8J
1 2 Layout Note: @ PR200 VSUM-
8 VSSSENSE
2

B B

PC149
0_0402_5%
Place near Phase1 Choke 1 2 V3N

2
@ PR201 10_0402_5%
1 2 1 21 2 VSUM- VSUM+
@ PC150 @ PR202 ISEN1
1200P_0402_50V7K 100_0402_1%
.1U_0402_16V7K
1

PC151
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 53 of 58
8 7 6 5 4 3 2 1
 5 4 3 2 1

B+ 1 2 B+_core
PL15 LX_VCORE
HCB4532KF-800T90_1812

10U_1206_25VAK

4.7U_0805_25V6-K
6268_VCC

10U_1206_25VAK
DH_VCORE

1
PC154
PR203 PR204 2.2_0603_1%

PC152

PC153
10K_0402_1% 1 2 1 2
BST_VCORE

2
PC155
0.1U_0603_25V7K

2
D D
+5VALW

5
PR205
0_0603_5% PQ48

26268_VCC

16

15
1

2
8

1
PU15
PR206 4

PHASE

BOOT
GND

PGOOD

UG
4.7_0603_5%

3 VIN PVCC 14 1 2 PC156

6268_VCC TPCA8030-H_SOP-ADV8-5

3
2
1
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
PC157

PL16
4 13 DL_VCORE +VGA_COREP
VCC LG
1

0.56U_PCMC104T-R56MN_25A_20%
1 2
APW7138NITRL_SSOP16
2

1
TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
PGND 12
@PR207
@ PR207

330U_D2E_2.5VM_R9M
4.7_1206_5%

10U_1206_25VAK

10U_1206_25VAK
PR208 1

PQ50

PC160

1
1 2 5 11 ISEN_VCORE 1 2 +

1 2
EN ISEN

2
8,41,44,47,50,52 SUSP#

PQ49

PC158

PC161
4 4 @

0_0402_5%
680P_0603_50V8J
0_0402_5% PR209

FSET

2
1

@ PC159

PR210
.1U_0402_16V7K

7.15K_0402_1%

NC

VO
FB
PC162

2
C C
2

10

3
2
1

3
2
1

1
PR211
10_0402_5% +VGA_CORE

57.6K_0402_1%
1 2
1

1
1

1
PR212

2
PR213
PC163 49.9K_0402_1% @PC164
@ PC164

1000P_0402_50V7K
22P_0402_50V8J 0.01U_0402_25V7K
2

2
PR214

2
4.75K_0402_1%
1

1
@ PC166
1
PC165
2200P_0402_25V7K
2

2
+5VALW

2
PR215
23.7K_0402_1%

2
B B
PR216

SSM3K7002FU_SC70-3
10K_0402_1%

1 1
1
PR217
D 15K_0402_1%

1
PQ51
PR218 2 1 2
G
7.5K_0402_1% S

.1U_0402_16V7K
VFB(0.6)=Vout*Rbottom/(Rtop+Rbottom)

PC167

SSM3K7002FU_SC70-3
FSW=1/(75E-12*57.6K)=231.48KHz

1
D

PQ52
2 1 2
M96 M92 G
VGA_PWRSEL 14
M96 M92 S PR219

0.01U_0402_25V7K
0_0402_5%

PC168
VGA_PWSELECT Core Voltage Level Core Voltage Level
Imax=18.23A Imax=12.81A

2
High 0.98 V 0.98 V Ipeak=26.05A Ipeak=18.30A
Iocp=28.65A Iocp=20.14A
Low 1.1 V 1.2 V
PR209=7.15K PR209=5.36K
PR214 = 4.75K PR214 = 4.75K PQ50=unpop PQ50=unpop
resistor setting PR218 =7.5K PR218 = 7.5K
PR215 =23.7K PR215 = 13K
A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23
Schematic, LA5322P M/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 54 of 58
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

NSWAA LA-5322P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.1 TO 0.2
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------
D D
3/25 31,32 DEL L14,C302,L15,C312,L16,C314,C315,L19,C339,C340 DG1.5: these pins have internal VRM

NSWAA LA-5322P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.2 TO 0.3
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------
6/29 11 Add R92,R93 To support M1 mode
6/29 27 Change R324 from 10K to 330K To solve ACIN LED issue
7/02 30 Change BT_PWR# from GPIO0 to GPIO34, add For common design with NSKAA
VGA_HDMI_HPD on GPIO0.
7/02 35 DEL JCAM (R431,R432,C403,R371,R373,R374,R375,L20) CAM cable combine with LVDS
7/02 22 DEL R387 Remove +5VALW power to camera
7/02 40 DEL YC1,CC10,CC12 Remove 12MHz crystal to cardreader
C 7/02 40 DEL RC2 Remove +3VALW to cardreader C

7/02 15~18 Add LV31,CV253,CV236,CV270,LV35,LV36,CV303,CV304, Reserve for support Park/Madsion

CV305,CV306,CV307,CV308,LV34,RV157,RV156,RV24,RV56
RV59,RV60,RV126,RV127
7/03 22 Add R120,R401 Reserve +1.5VS to clk gen for low power clk gen test
7/03 22,30 Add R154 Reserve LVDS_SEL on PCH GPIO45
7/03 30,41 Connect PCH GPIO33 to EC pin 103 as PWRME_CTRL To reflash ME BIOS
Change 3G_OFF# from EC pin 103 to pin 107
7/17 43 Add R50 on SATA_LED# Reserve for cost down plan
7/17 29 DEL R277,D12, Connect USB_OC#3_D to USB_OC#3
7/17 27,41,43 DEL R384, D14. Add R331 Modify ACIN circuit
7/17 22,43 Change Q7,Q34 to Dual Q35 For cost down
7/20 5,9,11, Add Q41,R19,R123,R22,D54,U10,R33,R52,Q33,R424,R417, Reserve S3 power reduction circuit
30,44 C179,Q46,C472,R417,R418,C205,C186,C185,C180,PJ30,PJ31,
B
R80,Q44,R425,R158,Q39,Q40,R94,R95,R122,R121 B

Add RST_GATE on PCH GPIO46

7/27 41 Add R5 To solve SYSON glitch issue
7/27 30,41 Connect PCH GPIO49 to EC pin25 as THM_ALT# Reserve for test
7/27 8,9,11, Add C144,C159,C218,C216,C217,CV309,CV310,CV311,CV312 For cost down
16,20
7/30 9,44 Add C160,C256,C257,C258,C473,C475 For EMI request
7/30 25,42 Change U13 to 8MB, U22 to 1MB For SW and EC request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 55 of 58
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

NSWAA LA-5322P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.3 TO 0.4
NO DATE PAGE MODIFICATION LIST PURPOSE
D -------------------------------------------------------------------------------------------------------------------------------------------------------- D

8/19 14,22 Add R159,R160 for VGA BKL control Reserve for deep green test
9/1 Change +3VL to +3VALW, DEL PJ12 .
9/1 25,42 Change EC ROM to 256KB and PCH ROM to 4MB For PVT test
9/1 34 Add L52,R72,R85,L53,R73,R87,L54,R77,R88 For EMI request
9/9 37 Connect WOL_EN# to LAN IC For PVT test

NSWAA LA-5322P SCHEMATIC CHANGE LIST

REVISION CHANGE: 0.4 TO 1.0
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------
9/30 25 Change C287,C290 from 18p to 15p To fine tune RTC timing
9/30 5 Change R22 from 10k to 1k Modify S3 circuit
C 10/28 5 Reserve C301,C384,C389 Reserve for S3 power saving circuit C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401717
Date: Monday, January 25, 2010 Sheet 56 of 58
5 4 3 2 1
NO DATE PAGE MODIFICATION LIST PURPOSE
-------------------------------------------------------------------------------------------------------------
EVT P47-PWR_CHARGER Change PR65 100 to 47k For CPU throtting setting (2009/05/20)

EVT P48-PWR_3VALWP/5VALWP Change PR81 19.6k to 19.1k modify +5VALWP voltage to 5.14V (2009/05/20)

EVT P49-PWR_+1.1V_VTTP Add PR290 100K, PR291 180K, PR292 10K, Add switching circuit for H_VTTSELECT function (2009/05/20)
PR293 4.7K, PR294 100K, PC228 0.01U,
PC229 0.1U, PQ55,PQ56

EVT P49-PWR_+1.1V_VTTP Change PR94 10K to 3.4K Set VTTPWROK voltage level to 1.1V (2009/05/20)
Add PR101 1K

EVT P53-PWR_CPU_CORE Remove PR186,PR201 10 Ohm Modify CPU_CORE circuit (2009/05/27)

EVT P46-PWR_BATTERY CONN / OTP Change PH1,PH2 0603 sizt to 0402 size For cost down (2009/05/27)

EVT P50-PWR_1.05VSP/1.8VSP Change PR115,PR249 422Ohm to 100 Ohm avoid 2nd source RT8209B can no power on (2009/06/05)
Change PC79,PC177 1U to 4.7U

EVT P52-PWR_0.75VSP/1.1VSP Change PU12 APL5913 to APL5930 For cost down (2009/06/05)

EVT P45-PWR_DCIN/DECTOR Remove DC301000F00 Remove DC IN JACK((2009/06/05))

EVT P54-PWR_VGA_COREP Change PR210 10 Ohm to 0 Ohm Change VGA_CORE sense from HW terminal to PWR (2009/06/05)
Change PR211 0 Ohm to 10 Ohm

EVT P54-PWR_VGA_COREP Change PL16 0.36U to 0.56U Change CPU_CORE CHOKE to 0.56U(2009/06/05)

EVT P50-PWR_1.05VSP/1.8VSP Change PR116 14.7k to 10k Set 1.05V OCP to 8.54A(2009/06/05)
Change PR250 15.4k to 9.1k Set 1.8V OCP to 4.93A(2009/06/05)

EVT P51-PWR_1.5VP Change PR127 7.15k to 2.1k Set 1.5V OCP to 17A(2009/06/05)

EVT P49-PWR_+VTTP Change PR99 5.9k to 2.43k Change VTT OCP to 19.7A(2009/06/05)

DVT P50-PWR_1.05VSP/1.8VSP Add PC175 0.1U For power sequence(2009/07/07)

Change PR247 0 to 30k

DVT P49-PWR_+VTTP Change PR99 2.43k to 4.99k Set OCP(2009/07/07)

DVT P51-PWR_1.5VP Change PR127 2.1k to 4.7k Set OCP(2009/07/07)

DVT P45-PWR_CPU_CORE PC133, PC134 SE083224Z80 to SE124224K80 PC133, PC134 tolerance Y5V to X5R(2009/0/07)

DVT P50-PWR_1.05VSP/1.8VSP Change PC79, PC177 SE00000MAN0 to SE107475K80 Change part number(2009/07/07)

DVT P41-PWR_3VALWP/5VALWP Add PC87 1U_0402_6.3V6K Avoid pre-charge can not finish(2009/07/07)

DVT P41-PWR_3VALWP/5VALWP Add PC45 0.22U to 1U Prevent +3VALW/+5VALW can’t boot up (2009/07/07)
DVT P45-PWR_CPU_CORE Change PR229~PR245 and PR160 10k to 1k Change VID, PSI# and DPRSLPVR select resistor from 10k to 1k (2009/07/17)

DVT P45-PWR_CPU_CORE Change PR157 10k to 1.91k Change PGOOD pull high resistor 10k to 1.91k(2009/07/17)

DVT P45-PWR_CPU_CORE Remove PH3, PC124, PR167 Modify circuit for CPU_CORE(2009/07/17)
Change PC133, PC134, PC170 pin 2 from GND to VSUM-
Change PR152, PR192 0402 size to 0805 size
DVT P39-PWR_BATTERY CONN / OTP Change +3VLP to +3VALWP Remove +3VLP power rail (2009/07/17)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 57 of 58
NO DATE PAGE MODIFICATION LIST PURPOSE
-------------------------------------------------------------------------------------------------------------
DVT P47-PWR_CHARGER Reserve PC188 0.1U Reserve for EMI solution (2009/07/23)
DVT P49-PWR_+VTTP Reserve PC189 0.1U Reserve for EMI solution (2009/07/23)
DVT P49-PWR_+VTTP Change PR95 0 ohm to 2.2 ohm Add boot strap resistor (2009/07/23)
DVT P49-PWR_+VTTP Add PR100 4.7 ohm, PC70 680P Add snubber (2009/07/23)
DVT P49-PWR_+VTTP Change PR94 3.4k to 1.5k, PR101 1k to 3k For HW solution(S3 power reduction ) (2009/07/23)
DVT P49-PWR_+VTTP Add PJ23 For power test(2009/07/23)
DVT P52-PWR_0.75VSP/1.1VSP Add 0.75VR_EN control signal For HW solution(S3 power reduction ) (2009/07/23)
DVT P53-PWR_CPU_CORE Add PR151, PR191 4.7 ohm, PC118, PC149 680P Add snubber (2009/07/23)
DVT P53-PWR_CPU_CORE Change PR148, PR188 0 ohm to 2.2 ohm Add boot strap resistor (2009/07/23)
DVT P53-PWR_CPU_CORE Add PC190 0.1U Reserve for EMI solution (2009/07/23)
DVT P45-PWR_CPU_CORE Remove PQ40, PQ47 For design change(2009/07/28)
DVT P52-PWR_0.75VSP/1.1VSP Change PC101 10U to 4.7U For design change(2009/07/28)
DVT P52-PWR_0.75VSP/1.1VSP Change PC106 SE076104KM8 to SE076104K80 Change to COMPAL PN(2009/08/03)
DVT P45-PWR_CPU_CORE Change PC151 SE076104KM8 to SE076104K80 Change to COMPAL PN(2009/08/03)
DVT Change PC53, PC54, PC78, PC95, PC181 SF22001M200 is forbids to use (2009/08/03)
SF22001M200 to SF000001H00

DVT P45-PWR_CPU_CORE Change PR195 1.1k to 1.2k Change Ri for load line (2009/08/03)
DVT P45-PWR_CPU_CORE Remove PR202 100 ohm, PC150 1200P Modify CPU_CORE circuit (2009/08/03)
DVT P49-PWR_+VTTP Change PU7 ISL6268 to APW7138 For cost down (2009/08/03)
Remove PC71 0.01U For APW7138 solution (2009/08/03)
DVT P51-PWR_1.5VP Change PU10 ISL6268 to APW7138 For cost down (2009/08/03)
Remove PC99 0.01U For APW7138 solution (2009/08/03)
DVT P54-PWR_VGA_COREP Change PU15 ISL6268 to APW7138 For cost down (2009/08/03)
Remove PC164 0.01U For APW7138 solution (2009/08/03)
DVT P51-PWR_1.5VP Change PL9 SM01000DJ00 to SM010018210 Use same PN bead (2009/08/03)
DVT P53-PWR_CPU_CORE Change PL11 SM010020720 to SM010018210 Use same PN bead (2009/08/03)
DVT P54-PWR_VGA_COREP Change PL15 SM01000DJ00 to SM010018210 Use same PN bead (2009/08/03)
DVT P39-PWR_BATTERY CONN / OTP Change PR33 13.7k to 12.4k Set OTP (2009/08/03)
Change PR37 15.4k to 15.8k
DVT P47-PWR_CHARGER Add PR220 4.7 ohm, PC169 680P Add charger snubber(RF solution) (2009/08/03)
Add PC144 0.1U, PC182 470P Add charger snubber(RF solution) (2009/08/03)
DVT P45-PWR_CPU_CORE Add PC113 2200P, PC114 470P, PC138 470P RF solution (2009/08/03)
PVT P42-PWR_+VTTP Change PL7 0.47U to 1U Design change (2009/09/04)
PVT P42-PWR_+VTTP Remove PC66, PC68 10U Design change (2009/09/04)
PVT P47-PWR_CHARGER Change PR70 8.25k to 53.6k, PR72 26.7k to 20k Set 90W CP (2009/09/04)
PVT P45-PWR_DCIN/DECTOR Add PC68 680P For EMI solution (2009/09/14)
PVT P46-PWR_BATTERY CONN / OTP Add PD14, PD15 Reserve for EMI(ESD diode) (2009/09/14)
PVT P42-PWR_+VTTP Remove PR290, PR291, PR292, PR293, PR105, Remove VTTP voltage switch circuit(arrandale only) (2009/09/14)
PC228, PC229, PQ55, PQ56

PVT P47-PWR_CHARGER Change PR64 PN SD013220B80 to SD014220B80 Use same PN (2009/09/14)

PVT P49-PWR_+VTTP Change PR95 PN SD013220B80 to SD014220B80 Use same PN (2009/09/14)
PVT P50-PWR_1.05VSP/1.8VSP Change PR113, PR248 0 ohm to 2.2 ohm Add boot trap resistor (2009/09/14)
Add PR114, PR251 4.7 ohm, PC80, PC180 680P Add snubber (2009/09/14)
PVT P45-PWR_CPU_CORE Change PR148, PR188 PN SD013220B80 to SD014220B80 Use same PN (2009/09/14)
PVT P54-PWR_VGA_COREP Change PR204 PN SD013220B80 to SD014220B80 Use same PN (2009/09/14)
PVT P50-PWR_1.05VSP/1.8VSP Change PR117 8.25k to 4.02k Avoid FB trace noise (2009/09/18)
Change PR118, PR253 20.5k to 10k
Change PR252 28.7k to 14k
PREMP P45-PWR_DCIN/DECTOR Change PC7 SE041224K80 to SE000005Z80 Change CAP size from 1206 to 0603 (2009/10/09)
PREMP P46-PWR_BATTERY CONN / OTP Change PR44 13.7k to 12.1k Modify OTP setting (2009/10/09)
PREMP P44-PWR_CPU_CORE Change PL12, PL14 SH000005680 to SH12036BM00 Use 5% tolerance DCR choke (2009/10/09)
PREMP P51-PWR_1.5VP Change PR131 4.75k to 4.87k Adjust voltage divided resistor (2009/10/27)
PREMP P49-PWR_+VTTP Change PR94 1.5k to 39.2k Adjust VTTPWROK voltage 3.3V to 1.05V (2009/10/27)
Change PR101 3k to 10.5k
PREMP P50-PWR_1.05VSP/1.8VSP Remove 1.05V component Cost down (2009/11/3)
MP P49-PWR_+VTTP Change PR94 39.2k to 6.81k Modify resistor for VTTPWROK voltage (2009/11/26)
PR101 10.5k to 2k

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/23 Deciphered Date 2009/10/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, LA5322P M/B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401717 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 25, 2010 Sheet 58 of 58
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