Dell Latitude E5530 Compal LA-7902P Rev 1.0 Schematics
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thetkomyint7.mmDell Latitude E5530 Compal LA-7902P Rev 1.0 Schematics
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COMPAL CONFIDENTIAL
MODEL NAME : QXW10
1 1
PCB NO : LA-7902P (DA60000PV00 )
BOM P/N : 4319F831L01
GPIO MAP: E4_VC_GPIO_map_rev_1.1
2 2
Korbel 15 UMA
Ivy/Sandy Bridge + Panther POINT(HM77 w/o Vpro,/QM77 w/Vpro)
2012-03-07
REV : 1.0 (A00)
@ : Nopop Component
CONN@ : Connector Component
3 3
MB Type BOM P/N
* TPM(R1) 4319F831L01 1@ 3@ 5@
TPM DIS(R1) 4319F831L02 2@ 3@
TPM(R3) 4319F831L03 1@ 3@ 5@
TPM DIS(R3) 4319F831L04 2@ 3@
* HM77 w/o Vpro
QM77 w/ Vpro
PCH XDP PXDP@
4 4
HDMI LOGO 46@
MB PCB
Part Number Description DELL CONFIDENTIAL/PROPRIETARY
DA60000PV00 PCB 0LH LA-7902P REV0 M/B UMA
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
A B
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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
C D
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
E
Sheet 1 of 61
Rev
1.0
A B C D E
Block Diagram
Memory BUS (DDR3) DDRIII-DIMM X2
1333/1600 MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
Ivy/Sandy Bridge pg12~13
1 1
rPGA CPU
On IO board
USB2.0[11]
CRT CONN VGA For MB/DOCK BT 4.0 pg41
pg37
Video Switch pg6~11
VGA PI3V713-AZLEX USB2.0[12]
pg23 Camera pg24 Through LVDS Cable
FDI DMI2
Lane x 8 Lane x 4 USB2.0[13]
VGA Fingerprint CONN pg41
HDMI CONN DPB INTEL USB SATA[4]
pg25 E-SATA
DPC USB3.0[3]
DPD Panther POINT-M USB 3.0 Port
DOCKING PORT
USB2.0[2]
pg38 USB 2.0 Port pg36
BGA
DAI
LVDS CONN LVDS USB3.0[2]
2
pg24 HM77/QM77 USB 3.0 Port 2
USB2.0 [3,7] USB2.0[1]
SATA5 pg14~21 USB 2.0 Port pg36
DOCK LAN
SDXC/MMC Card Reader
USB3.0 [4] PCIE 6 USB2.0[0,9]
OZ600FJ0 USB2.0 pg37
pg33
pg33 on IO/Audio board BROADCOM
PCI Express BUS 100MHz BCM5761
HD Audio I/F PCIE7
PCI Express BUS 100MHz pg30,31
Option
SPI S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PCIE3 PCIE5 PCIE2 PCIE1
DOCK LAN
LAN SWITCH
Smart 1/2 Mini Card 1/2 Mini Card Full Mini Card China TCM1.2 LPC BUS PI3L720 pg30
33MHz INT.Speaker
/Express WLAN/WiFi WWAN SSX44B HDA Codec
Card pg35 PP pg34 pg34 pg34 pg32
W25Q64CVSSIG 92HD93 pg29
pg14
pg29
USB10 USB6 USB4 USB5 64M 4K sector
3
Discrete TPM LPC BUS Combo Jack RJ45 3
33MHz pg37
AT97SC3204 W25Q32BVSSIG HDD MDC pg37
pg32 pg14 pg27 pg37 on IO board
32M 4K sector on IO board on Audio board
CPU XDP Port
pg7 DAI
SMSC SIO FFS LNG3DM To Docking side
BC BUS pg27 RJ11
PCH XDP Port ECE5048
pg14 pg39 DMIC0 Dig.
Through Cable
SMSC KBC MIC
WiFi ON/OFF pg37 MEC5055 ODD Through LVDS Cable
PWM FAN
pg22
EMC4021
pg22
pg28
pg40
DC/DC Interface DMIC1 Sigle.
pg42
MIC
LED
pg43
4
TP CONN KB CONN on PWR board 4
pg41 pg41
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, UMA Block Diagram
A B
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C D
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Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
E
Sheet 2 of 61
Rev
1.0
5 4 3 2 1
POWER STATES
USB 3.0 PORT# Connetion USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
1 NA 0 JUSB (Right side-IO/B)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
2 JUSB1 (Left side) 1 JUSB1 (Left side)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
3 JESA1 (Left side) 2 JESA1 (Left side ESATA)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
4 MLK DOCK 3 DOCKING
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCH
*1 6 JMINI3(Flash)-for w/ Vpro
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
*1 7 DOCKING
8 NA
PM TABLE
9 JUSB (Right side-Audio/B)
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C C
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
10 Express card
+3.3V_ALW_PCH +1.8V_RUN (M-OFF)
power
+3.3V_RTC_LDO +1.5V_RUN
plane 11 Bluetooth
+0.75V_DDR_VTT
+VCC_CORE
12 Camera
+1.05V_RUN_VTT
+1.05V_RUN
State 13 BIO
*1: HM76 don't support port 6,7
S0 ON ON ON ON ON
SATA DESTINATION
S3 ON ON OFF ON OFF
SATA 0 HDD
S5 S4/AC ON OFF OFF ON OFF
SATA 1 ODD/ E3 Module Bay
B
S5 S4/AC don't exist OFF OFF OFF OFF OFF PCI EXPRESS DESTINATION B
SATA 2 NA
need to update Power Status and PM Lane 1 MINI CARD-1 WWAN
Table SATA 3 NA
Lane 2 MINI CARD-2 WLAN
SATA 4 ESATA
Lane 3 Express card
SATA 5 Dock
Lane 4 None
Lane 5 1/2vMINI CARD-3 PCIE
UMA DP/HDMI Port Connetion
Port B MB HDMI Conn Lane 6 MMI
Lane 7 10/100/1G LOM
Port C Dock DP port 2
Lane 8 None
A Port D Dock DP port 1 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Index and Config.
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 3 of 61
5 4 3 2 1
5 4 3 2 1
SIO_SLP_S3#
MCARD_WWAN_PWREN
MODC_EN
MCARD_MISC_PWREN
EN_INVPWR FDC654P
+BL_PWR_SRC
(Q21)
D D
SI3456BDV SI3456BDV
ADAPTER
(Q27) (Q30)
1.05V_0.8V_PWROK
ISL95836
+VCC_GFXCORE
(PU700)
SI3456 SI3456
+5V_HDD +5V_MOD (Q42) (Q40)
+PWR_SRC
BATTERY PJP3 PJP4
+5V_RUN Pop option
ALWON
+3.3V_PCIE_FLASH
C RT8205 C
+5V_ALW
CHARGER (PU100) +3.3V_PCIE_WWAN
+3.3V_ALW
1.05V_VTTPWRGD
TM/TL(PT)
AUX_EN_WOWL
SIO_SLP_S3#
PCH_ALW_ON
RUN_ON
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_S3#
AUX_ON
vPro DASH
SUS_ON
RT8207
TPS51212 TPS51212
ISL95836 (PU200)
SYN470 TPS51461
(PU700) (PU500) (PU400) SI3456 SI3456 S13456 SI3456 DMN3030LSS SI3456
(PU300) (PU7)
DDR_ON
SIO_SLP_S4#
B (Q38) (Q49) (Q54) (Q34) (Q61) (Q55) (Q58) B
1.05V_0.8V_PWROK
DASH(PT) DASH(SSI)
0.75V_DDR_VTT_ON
CPU_VTT_ON
SIO_SLP_A#
SIO_SLP_S3#
SIO_SLP_S3#
CPU1.5V_S3_GATE
+1.5V_MEM
+1.8V_RUN +VCC_SA +3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_M
+VCC_CORE +1.05V_RUN_VTT +1.05V_M SIO_SLP_S3#
R563 R206
Pop option DASH(SSI)
PJP7 SIO_SLP_S3#(PT) AO4304L AO4304L
(QC3) (Q59)
+3.3V_M +3.3V_RUN +5V_RUN +3.3V_SUS
PJP8(SSI)
SI4164
A (Q63) A
+1.5V_CPU_VDDQ +1.5V_RUN +0.75V_DDR_VTT DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
+1.05V_RUN BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 4 of 61
Rev
1.0
5 4 3 2 1
2.2K
SMBUS Address [0x9a]
2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
DMN66D0L
C9 MEM_SMBDATA 200 DIMM1 SMBUS Address [A0]
DMN66D0L
DMN66D0L
202
PCH
DMN66D0L LAN_APE_SMB_DATA0 L09 DIMM2
D
C8 DMN66D0L 200 SMBUS Address [A4] D
LAN_APE_SMB_CLK0 L10 BCM LOM SMBUS Address [C8]
G12
DMN66D0L MCTP Endpoint ID 0x09
PLDM Sensor Aggregator 0xDA
M16 E14 53
2.2K XDP1 SMBUS Address [TBD]
2.2K +3.3V_LAN 51
SML1_SMBDATA
2.2K
SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 SMBUS Address [TBD]
2.2K
3A 3A
2.2K
+3.3V_ALW 10K
A50 SIO_LAN_SMBCLK
1E +3.3V_RUN
B53 SIO_LAN_SMBDAT 10K
1E
4
6 G Sensor
2.2K SMBUS Address [3B]
C
+3.3V_ALW C
2.2K
B5 LCD_SMBCLK 30
1B WWAN
A4 LCD_SMDATA 32 SMBUS Address [TBD]
1B
2.2K
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K
2.2K +3.3V_ALW SMBUS Address
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70
DOCK_SMB_DAT
129 DOCKING MSLICE_EC: 0x72
1A A3 USB: 0x59
B
2.2K AUDIO: 0x34 B
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
+3.3V_SUS
2.2K
MEC 5055 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 10
1G CHARGER_SMBCLK
A47 9 Charger
1G CHARGER_SMBDAT SMBUS Address [0x12]
2.2K
+3.3V_ALW
2.2K
2D B7 BAY_SMBDAT
A
2D A7 BAY_SMBCLK A
Compal Electronics, Inc.
Title
SMBUS TOPOLOGY
5 4
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Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 5 of 61
Rev
1.0
5 4 3 2 1
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. JCPU1I CONN@
(2)PEG_ICOMPO use 12mil connect to RC2
T35 VSS161 VSS234 F22
T34 VSS162 VSS235 F19
+1.05V_RUN_VTT T33 E30
VSS163 VSS236
T32 VSS164 VSS237 E27
T31 VSS165 VSS238 E24
1
T30 E21
RC2 VSS166 VSS239
T29 E18
VSS167 VSS240
24.9_0402_1%~D T28 E15
D VSS168 VSS241 D
T27 E13
JCPU1A CONN@ VSS169 VSS242
T26 E10
2
PEG_COMP VSS170 VSS243
J22 P9 E9
PEG_ICOMPI VSS171 VSS244
J21 P8 E8
DMI_CRX_PTX_N0 PEG_ICOMPO VSS172 VSS245
<16> DMI_CRX_PTX_N0 B27 H22 P6 E7
DMI_CRX_PTX_N1 DMI_RX#[0] PEG_RCOMPO VSS173 VSS246
<16> DMI_CRX_PTX_N1 B25
DMI_RX#[1] PEG Compensation P5
VSS174 VSS247
E6
DMI_CRX_PTX_N2 A25 P3 E5
<16> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_RX#[2] VSS175 VSS248
<16> DMI_CRX_PTX_N3 B24 K33 P2 E4
DMI_RX#[3] PEG_RX#[0] VSS176 VSS249
M35 N35 E3
DMI_CRX_PTX_P0 PEG_RX#[1] VSS177 VSS250
<16> DMI_CRX_PTX_P0 B28 L34 N34 E2
DMI_CRX_PTX_P1 DMI_RX[0] PEG_RX#[2] PEG_ICOMPI and RCOMPO signals should be shorted and routed VSS178 VSS251
<16> DMI_CRX_PTX_P1 B26 J35 N33 E1
DMI_CRX_PTX_P2 DMI_RX[1] PEG_RX#[3] VSS179 VSS252
<16> DMI_CRX_PTX_P2 A24 DMI_RX[2] PEG_RX#[4] J32 with - max length = 500 mils - typical impedance = 43 mohms N32 VSS180 VSS253 D35
DMI_CRX_PTX_P3 B23
DMI
<16> DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] H34 PEG_ICOMPO signals should be routed with - max length = 500 mils N31 VSS181 VSS254 D32
PEG_RX#[6] H31 - typical impedance = 14.5 mohms N30 VSS182 VSS255 D29
<16> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 G21 G33 N29 D26
DMI_CTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] VSS183 VSS256
<16> DMI_CTX_PRX_N1 E22 DMI_TX#[1] PEG_RX#[8] G30 N28 VSS184 VSS257 D20
<16> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 F21 F35 N27 D17
DMI_CTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] VSS185 VSS258
<16> DMI_CTX_PRX_N3 D21 DMI_TX#[3] PEG_RX#[10] E34 N26 VSS186 VSS259 C34
PEG_RX#[11] E32 M34 VSS187 VSS260 C31
<16> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 G22 D33 L33 C28
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] VSS188 VSS261
<16> DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31 L30 VSS189 VSS262 C27
<16> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 F20 B33 L27 C25
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] VSS190 VSS263
<16> DMI_CTX_PRX_P3 C21 C32 L9 C23
PCI EXPRESS* - GRAPHICS
DMI_TX[3] PEG_RX#[15] VSS191 VSS264
L8 VSS192 VSS265 C10
PEG_RX[0] J33 L6 VSS193 VSS266 C1
PEG_RX[1] L35 L5 VSS194 VSS267 B22
K34 L4 B19
<16>
<16>
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
A21
H19
FDI0_TX#[0]
FDI0_TX#[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
H35
H32
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
<16> FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 E19 G34 L1 B13
FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] VSS198 VSS271
<16> FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31 K35 VSS199 VSS272 B11
<16> FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 B21 F33 K32 B9
FDI1_TX#[0] PEG_RX[7] VSS200 VSS273
Intel(R) FDI
C FDI_CTX_PRX_N5 C
<16> FDI_CTX_PRX_N5 C20 FDI1_TX#[1] PEG_RX[8] F30 K29 VSS201 VSS274 B8
<16> FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 D18 E35 K26 B7
FDI_CTX_PRX_N7 FDI1_TX#[2] PEG_RX[9] VSS202 VSS275
<16> FDI_CTX_PRX_N7 E17 FDI1_TX#[3] PEG_RX[10] E33 J34 VSS203 VSS276 B5
PEG_RX[11] F32 J31 VSS204 VSS277 B3
PEG_RX[12] D34 H33 VSS205 VSS278 B2
<16> FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22 E31 H30 A35
FDI_CTX_PRX_P1 FDI0_TX[0] PEG_RX[13] VSS206 VSS279
<16> FDI_CTX_PRX_P1 G19 FDI0_TX[1] PEG_RX[14] C33 H27 VSS207 VSS280 A32
<16> FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 E20 B32 H24 A29
FDI_CTX_PRX_P3 FDI0_TX[2] PEG_RX[15] VSS208 VSS281
<16> FDI_CTX_PRX_P3 G18 H21 A26
FDI_CTX_PRX_P4 FDI0_TX[3] VSS209 VSS282
<16> FDI_CTX_PRX_P4 B20 M29 H18 A23
FDI_CTX_PRX_P5 FDI1_TX[0] PEG_TX#[0] VSS210 VSS283
<16> FDI_CTX_PRX_P5 C19 M32 H15 A20
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] VSS211 VSS284
<16> FDI_CTX_PRX_P6 D19 M31 H13 A3
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] VSS212 VSS285
<16> FDI_CTX_PRX_P7 F17 L32 H10
FDI1_TX[3] PEG_TX#[3] VSS213
L29 H9
FDI_FSYNC0 PEG_TX#[4] VSS214
<16> FDI_FSYNC0 J18 K31 H8
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] VSS215
<16> FDI_FSYNC1 J17 K28 H7
FDI1_FSYNC PEG_TX#[6] VSS216
J30 H6
FDI_INT PEG_TX#[7] VSS217
<16> FDI_INT H20 J28 H5
FDI_INT PEG_TX#[8] VSS218
H29 H4
FDI_LSYNC0 PEG_TX#[9] VSS219
<16> FDI_LSYNC0 J19 G27 H3
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] VSS220
<16> FDI_LSYNC1 H17 E29 H2
FDI1_LSYNC PEG_TX#[11] VSS221
F27 H1
PEG_TX#[12] VSS222
(1) EDP_COMPIO use 4mil trace to RC1 PEG_TX#[13]
D28 G35
VSS223
F26 G32
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] VSS224
E25 G29
EDP_COMP PEG_TX#[15] VSS225
A18 G26
eDP_COMPIO VSS226
A17 M28 G23
eDP_ICOMPO PEG_TX[0] VSS227
B16 M33 G20
eDP_HPD# PEG_TX[1] VSS228
M30 G17
PEG_TX[2] VSS229
L31 G11
PEG_TX[3] VSS230
C15 L28 F34
eDP_AUX PEG_TX[4] VSS231
D15 K30 F31
B eDP_AUX# PEG_TX[5] VSS232 B
K27 F29
PEG_TX[6] VSS233
J29
eDP
PEG_TX[7]
C17 J27
eDP_TX[0] PEG_TX[8]
F16 H28
eDP_TX[1] PEG_TX[9]
C16 G28
eDP_TX[2] PEG_TX[10]
G15 E28
eDP_TX[3] PEG_TX[11]
F28
PEG_TX[12]
C18 D27
eDP_TX#[0] PEG_TX[13]
E16 E26
eDP_TX#[1] PEG_TX[14]
D16 D25
eDP_TX#[2] PEG_TX[15] TYCO_2013620-3_IVYBRIDGE
F15
eDP_TX#[3]
TYCO_2013620-3_IVYBRIDGE
DP Compensation
+1.05V_RUN_VTT
1
RC1
24.9_0402_1%~D
A A
2
EDP_COMP
DELL CONFIDENTIAL/PROPRIETARY
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandt Bridge (1/6)
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 6 of 61
5 4 3 2 1
5 4 3 2 1
Follow DG Rev0.71 SM_DRAMPWROK topology +1.05V_RUN_VTT
+1.5V_CPU_VDDQ +3.3V_ALW_PCH
+1.05V_RUN_VTT +1.05V_RUN_VTT
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
+3.3V_ALW_PCH
1
CC156 0.1U_0402_25V6K~D 1 1
1
1 2 RC12
CC65
CC66
200_0402_1%~D JXDP1
5
UC2 @ RC124 1 2
1K_0402_1%~D 2 2 XDP_PREQ# GND0 GND1 CFG16
1 B 3 4 CFG16 <9>
P
<39,40> RUNPWROK
2
RUNPWROK_AND OBSFN_A0 OBSFN_C0
4 1 2 PM_DRAM_PWRGD_CPU XDP_PRDY# 5 6 CFG17 CFG17 <9>
2
O RC28 130_0402_1%~D OBSFN_A1 OBSFN_C1
+3.3V_ALW_PCH 1 2 2 7 8
A GND2 GND3
2
RC18 200_0402_1%~D SYS_PWROK_XDP XDP_OBS0 9 10 CFG0 CFG0 <9>
74AHC1G09GW_TSSOP5~D RC64 @ XDP_OBS1 OBSDATA_A0 OBSDATA_C0 CFG1
<16> PM_DRAM_PWRGD Place near JXDP1 11 12 CFG1 <9>
3
39_0402_5%~D OBSDATA_A1 OBSDATA_C1
13 14
D XDP_OBS2 GND4 GND5 CFG2 D
15 16 CFG2 <9>
XDP_OBS3 OBSDATA_A2 OBSDATA_C2 CFG3
17 18 CFG3 <9>
1 1
OBSDATA_A3 OBSDATA_C3
19 20
D CFG10 GND6 GND7 CFG8
<9> CFG10 21 22 CFG8 <9>
QC1 @ CFG11 OBSFN_B0 OBSFN_D0 CFG9
<11,42> RUN_ON_CPU1.5VS3# 2 <9> CFG11 23 24 CFG9 <9>
G SSM3K7002FU_SC70-3~D OBSFN_B1 OBSFN_D1
25 26
XDP_OBS4 GND8 GND9 CFG4
S 27 28 CFG4 <9>
3
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 30 CFG5 <9>
OBSDATA_B1 OBSDATA_D1
The resistor for HOOK2 should beplaced 31 32
XDP_OBS6 GND10 GND11 CFG6
such that the stub is very small on CFG0 net 33
OBSDATA_B2 OBSDATA_D2
34 CFG6 <9>
XDP_OBS7 35 36 CFG7 CFG7 <9>
OBSDATA_B3 OBSDATA_D3
37 GND12 GND13 38
INTEL suggest RC64 and QC1 NO stuff by default H_CPUPWRGD 1 2 H_CPUPWRGD_XDP 39 40 CLK_XDP
PWRGOOD/HOOK0 ITPCLK/HOOK4
<14,16> SIO_PWRBTN#_R
RC51 2 1K_0402_1%~DCFD_PWRBTN#_XDP 41 42 CLK_XDP#
RC6 0_0402_5%~D HOOK1 ITPCLK#/HOOK5
43 VCC_OBS_AB VCC_OBS_CD 44
CFG0 1 2 XDP_HOOK2 45 46 XDP_RST#_R
+1.05V_RUN_VTT HOOK2 RESET#/HOOK6
<16,39> SYS_PWROK
RC71 2 1K_0402_1%~D SYS_PWROK_XDP 47 HOOK3 DBR#/HOOK7 48 XDP_DBRESET#
@RC9
@ RC9 0_0402_5%~D 49 50
DDR_XDP_SMBDAT_R1 GND14 GND15 XDP_TDO
<12,13,14,15,27,34> DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
1 2 H_THERMTRIP# RC1251 20_0402_5%~D DDR_XDP_SMBCLK_R1 53 54 XDP_TRST#
<12,13,14,15,27,34> DDR_XDP_WAN_SMBCLK SCL TRST# XDP_TDI
@ RC126 56_0402_5%~D RC127 0_0402_5%~D 55 56
H_CATERR# XDP_TCLK TCK1 TDI XDP_TMS
1 2 57 TCK0 TMS 58
@ RC128 49.9_0402_1%~D 59 60
H_PROCHOT# GND16 GND17
1 2
RC44 62_0402_5%~D JCPU1B CONN@ SAMTE_BSH-030-01-L-D-A CONN@
Follow check list 0.5 A28 CPU_DMI 1 2
BCLK CPU_DMI# CLK_CPU_DMI <15>
C26 A27 @ RC13 1 2 0_0402_5%~D
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
@ RC15 0_0402_5%~D XDP_RST#_R
MISC
CLOCKS
2 1 PLTRST_XDP# <17>
RC8 1K_0402_1%~D
C C
<39> CPU_DETECT# AN34 SKTOCC#
A16 CPU_DPLL 1 2
DPLL_REF_CLK CPU_DPLL# RC16 1
A15 2 1K_0402_1%~D +1.05V_RUN_VTT
DPLL_REF_CLK# RC17 1K_0402_1%~D
CLK_XDP
H_CATERR# AL33
Remove DPLL Ref clock (for eDP only) 1
@ RC48
2
0_0402_5%~D RH107
1 2
0_0402_5%~D
CLK_CPU_ITP <15>
CATERR# CLK_XDP# 1 2 CLK_CPU_ITP# <15>
RH106 0_0402_5%~D
D
DDR3_DRAMRST#_CPU
THERMAL
<40> PECI_EC AN33 R8 3 1 DDR3_DRAMRST# <12>
PECI SM_DRAMRST#
QC2
VR1 TOPOLOGY DDR3 Max 500mils
MISC
BSS138W-7-F_SOT323-3~D
G
<9> CLK_XDP_ITP 1 2
2
1
<40,51,52> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 @ RH109 0_0402_5%~D
RC57 56_0402_5%~D PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC50
A5 <9> CLK_XDP_ITP# 1 2
Close to JCPU1 SM_RCOMP[1] SM_RCOMP2 4.99K_0402_1%~D DDR_HVREF_RST @ RH108 0_0402_5%~D
A4
SM_RCOMP[2]
<22> H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 SM_RCOMP2 --> 15mil 1
2
RC129 0_0402_5%~D THERMTRIP#
SM_RCOMP1/0 --> 20mil CC177
place RC129 near CPU 0.047U_0402_16V4Z~D
2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
AP27
PREQ#
AR26 XDP_TCLK 1 2
TCK XDP_TMS <15> DDR_HVREF_RST_PCH
AR27 @RC46
@ RC46 0_0402_5%~D
H_PM_SYNC TMS XDP_TRST#
AM34 AP30 1 2
PWR MANAGEMENT
<16> H_PM_SYNC <40> DDR_HVREF_RST_GATE
JTAG & BPM
PM_SYNC TRST# @RC47
@ RC47 0_0402_5%~D DDR_HVREF_RST <12>
AR28 XDP_TDI_R
TDI XDP_TDO_R M3 control
AP26
TDO
<18> H_CPUPWRGD 1 2 VCCPWRGOOD_0_R AP33
B RC25 1K_0402_5%~D UNCOREPWRGOOD B
AL35 XDP_DBRESET#_R 2 1 XDP_DBRESET# XDP_DBRESET# <14,16>
PM_DRAM_PWRGD_CPU DBR# RC26 0_0402_5%~D
V8
SM_DRAMPWROK
AT28 XDP_OBS0_R 1 2 XDP_OBS0
BPM#[0] XDP_OBS1_R 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
BPM#[1]
AR29 RC30 1 2 1 2 PU/PD for JTAG signals
AR30 XDP_OBS2_R RC31 1 2 0_0402_5%~D XDP_OBS2 RC23 0_0402_5%~D
PCH_PLTRST#_R BPM#[2] XDP_OBS3_R RC33 0_0402_5%~D XDP_OBS3 +3.3V_RUN
AR33 AT30 1 2
RESET# BPM#[3] XDP_OBS4_R RC34 0_0402_5%~D XDP_OBS4
AP32 1 2
BPM#[4] XDP_OBS5_R RC36 0_0402_5%~D XDP_OBS5 XDP_TDO_R XDP_TDO
AR31 1 2 1 2
BPM#[5] XDP_OBS6_R RC37 0_0402_5%~D XDP_OBS6 RC24 0_0402_5%~D XDP_DBRESET#RC19 2
AT31 1 2 1 1K_0402_1%~D
BPM#[6] XDP_OBS7_R RC38 0_0402_5%~D XDP_OBS7
AR32 1 2
BPM#[7] RC39 0_0402_5%~D
+1.05V_RUN_VTT
For ESD concern, please put near CPU
XDP_TMS RC27 2 1 51_0402_1%~D
TYCO_2013620-3_IVYBRIDGE
XDP_TDI RC29 2 1 51_0402_1%~D
Reserve for ESD in 6/22 VCCPWRGOOD_0_R XDP_PREQ# @ RC32 2 1 51_0402_1%~D
Buffered reset to CPU +3.3V_RUN SM_RCOMP2
+1.05V_RUN_VTT Place closed JCPU1
100P_0402_50V8J~D
SM_RCOMP1 XDP_TDO RC35 2 1 51_0402_1%~D
1
1 SM_RCOMP0
0.1U_0402_25V6K~D
XDP_DBRESET# RC130
CC141
140_0402_1%~D
200_0402_1%~D
25.5_0402_1%~D
1 10K_0402_5%~D
1
1
75_0402_1%~D
RC4
XDP_TCLK RC40 2 1
2
CC140
RC42
RC43
RC45
1 51_0402_1%~D
2
CE13 XDP_TRST# RC41 2 1
2 51_0402_1%~D
UC1 0.047U_0402_16V4Z~D
2
2
@ 2
1 NC VCC 5
A A
<14,17> PCH_PLTRST# 2 A
3 4 PCH_PLTRST#_BUF 1 2 PCH_PLTRST#_R Avoid stub in the PWRGD path
GND Y RC10 43_0402_5%~D while placing resistors RC25 & RC130
SN74LVC1G07DCKR_SC70-5~D 1
DELL CONFIDENTIAL/PROPRIETARY
100P_0402_50V8J~D
CC142
Open drain buffer
2
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandy Bridge (2/6)
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 7 of 61
5 4 3 2 1
5 4 3 2 1
JCPU1D CONN@
JCPU1C CONN@
AE2 M_CLK_DDR2
D M_CLK_DDR0 <13> DDR_B_D[0..63] SB_CK[0] M_CLK_DDR#2 M_CLK_DDR2 <13> D
<12> DDR_A_D[0..63] AB6 M_CLK_DDR0 <12> AD2 M_CLK_DDR#2 <13>
SA_CK[0] M_CLK_DDR#0 DDR_B_D0 SB_CLK#[0] DDR_CKE2_DIMMB
AA6 M_CLK_DDR#0 <12> C9 R9 DDR_CKE2_DIMMB <13>
DDR_A_D0 SA_CLK#[0] DDR_CKE0_DIMMA DDR_B_D1 SB_DQ[0] SB_CKE[0]
C5 V9 DDR_CKE0_DIMMA <12> A7
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_B_D2 SB_DQ[1]
D5 D10
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D3 C8
DDR_A_D3 SA_DQ[2] DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D2 A9 AE1 M_CLK_DDR3 <13>
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D5 SB_DQ[4] SB_CK[1] M_CLK_DDR#3
D6 AA5 M_CLK_DDR1 <12> A8 AD1 M_CLK_DDR#3 <13>
DDR_A_D5 SA_DQ[4] SA_CK[1] M_CLK_DDR#1 DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB
C6 AB5 M_CLK_DDR#1 <12> D9 R10 DDR_CKE3_DIMMB <13>
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_CKE1_DIMMA DDR_B_D7 SB_DQ[6] SB_CKE[1]
C2 V10 DDR_CKE1_DIMMA <12> D8
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D8 SB_DQ[7]
C3 G4
DDR_A_D8 SA_DQ[7] DDR_B_D9 SB_DQ[8]
F10 F4
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F8 SA_DQ[9] F1 SB_DQ[10] SB_CK[2] AB2
DDR_A_D10 G10 AB4 DDR_B_D11 G1 AA2
DDR_A_D11 SA_DQ[10] SA_CK[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
G9 SA_DQ[11] SA_CLK#[2] AA4 G5 SB_DQ[12] SB_CKE[2] T9
DDR_A_D12 F9 W9 DDR_B_D13 F5
DDR_A_D13 SA_DQ[12] SA_CKE[2] DDR_B_D14 SB_DQ[13]
F7 SA_DQ[13] F2 SB_DQ[14]
DDR_A_D14 G8 DDR_B_D15 G2
DDR_A_D15 SA_DQ[14] DDR_B_D16 SB_DQ[15]
G7 SA_DQ[15] J7 SB_DQ[16] SB_CK[3] AA1
DDR_A_D16 K4 AB3 DDR_B_D17 J8 AB1
DDR_A_D17 SA_DQ[16] SA_CK[3] DDR_B_D18 SB_DQ[17] SB_CLK#[3]
K5 SA_DQ[17] SA_CLK#[3] AA3 K10 SB_DQ[18] SB_CKE[3] T10
DDR_A_D18 K1 W10 DDR_B_D19 K9
DDR_A_D19 SA_DQ[18] SA_CKE[3] DDR_B_D20 SB_DQ[19]
J1 SA_DQ[19] J9 SB_DQ[20]
DDR_A_D20 J5 DDR_B_D21 J10
DDR_A_D21 SA_DQ[20] DDR_B_D22 SB_DQ[21] DDR_CS2_DIMMB#
J4 SA_DQ[21] K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# <13>
DDR_A_D22 J2 AK3 DDR_CS0_DIMMA# DDR_B_D23 K7 AE3 DDR_CS3_DIMMB#
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# <12> SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_CS1_DIMMA# DDR_B_D24 M5 AD6
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> DDR_B_D25 SB_DQ[24] SB_CS#[2]
M8 SA_DQ[24] SA_CS#[2] AG1 N4 SB_DQ[25] SB_CS#[3] AE6
DDR_A_D25 N10 AH1 DDR_B_D26 N2
DDR_A_D26 SA_DQ[25] SA_CS#[3] DDR_B_D27 SB_DQ[26]
N8 SA_DQ[26] N1 SB_DQ[27]
DDR_A_D27 N7 DDR_B_D28 M4
DDR_A_D28 SA_DQ[27] DDR_B_D29 SB_DQ[28] M_ODT2
M10 SA_DQ[28] N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 <13>
DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D30 M2 AD4 M_ODT3
C DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 M_ODT0 <12> DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 <13> C
N9 AG3 M1 AD5
DDR SYSTEM MEMORY B
DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 <12> DDR_B_D32 SB_DQ[31] SB_ODT[2]
M7 SA_DQ[31] SA_ODT[2] AG2 AM5 SB_DQ[32] SB_ODT[3] AE5
DDR SYSTEM MEMORY A
DDR_A_D32 AG6 AH2 DDR_B_D33 AM6
DDR_A_D33 SA_DQ[32] SA_ODT[3] DDR_B_D34 SB_DQ[33]
AG5 SA_DQ[33] AR3 SB_DQ[34]
DDR_A_D34 AK6 DDR_B_D35 AP3
DDR_A_D35 SA_DQ[34] DDR_B_D36 SB_DQ[35]
AK5 SA_DQ[35] AN3 SB_DQ[36] DDR_B_DQS#[0..7] <13>
DDR_A_D36 AH5 DDR_B_D37 AN2 D7 DDR_B_DQS#0
SA_DQ[36] DDR_A_DQS#[0..7] <12> SB_DQ[37] SB_DQS#[0]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ5 G6 AP2 K6
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ6 J3 AP5 N3
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AJ8 M6 AN9 AN5
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AK8 AL6 AT5 AP9
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AJ9 AM8 AT6 AK12
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AK9 AR12 AP6 AP15
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH8 AM15 AN8
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D46 SB_DQ[45]
AH9 AR6
DDR_A_D46 SA_DQ[45] DDR_B_D47 SB_DQ[46]
AL9 AR5
DDR_A_D47 SA_DQ[46] DDR_B_D48 SB_DQ[47]
AL8 AR9 DDR_B_DQS[0..7] <13>
DDR_A_D48 SA_DQ[47] DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AP11 DDR_A_DQS[0..7] <12> AJ11 C7
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AN11 D4 AT8 G3
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AL12 F6 AT9 J6
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM12 K3 AH11 M3
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AM11 N6 AR8 AN6
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AL11 AL5 AJ12 AP8
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AP12 AM9 AH12 AK11
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AN12 AR11 AT11 AP14
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D57 SB_DQ[56] SB_DQS[7]
AJ14 AM14 AN14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D58 SB_DQ[57]
AH14 AR14
DDR_A_D58 SA_DQ[57] DDR_B_D59 SB_DQ[58]
AL15 AT14 DDR_B_MA[0..15] <13>
DDR_A_D59 SA_DQ[58] DDR_B_D60 SB_DQ[59]
AK15 DDR_A_MA[0..15] <12> AT12
DDR_A_D60 SA_DQ[59] DDR_B_D61 SB_DQ[60] DDR_B_MA0
AL14 AN15 AA8
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK14 AD10 AR15 T7
B DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2 B
AJ15 W1 AT15 R7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 SB_DQ[63] SB_MA[2] DDR_B_MA3
AH15 W2 T6
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
W7 T2
SA_MA[3] DDR_A_MA4 SB_MA[4] DDR_B_MA5
V3 T4
SA_MA[4] DDR_A_MA5 SB_MA[5] DDR_B_MA6
V2 T3
SA_MA[5] DDR_A_MA6 DDR_B_BS0 SB_MA[6] DDR_B_MA7
W3 <13> DDR_B_BS0 AA9 R2
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS1 AA7 T5
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
<12> DDR_A_BS1 AF10 V1 <13> DDR_B_BS2 R6 R3
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[2] SB_MA[9] DDR_B_MA10
<12> DDR_A_BS2 V6 W5 AB7
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_MA[10] DDR_B_MA11
AD8 R1
SA_MA[10] DDR_A_MA11 SB_MA[11] DDR_B_MA12
V4 T1
SA_MA[11] DDR_A_MA12 DDR_B_CAS# SB_MA[12] DDR_B_MA13
W4 <13> DDR_B_CAS# AA10 AB10
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_RAS# AB8 R5
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_WE# AB9 R4
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[15]
<12> DDR_A_WE# AF9 V7
SA_WE# SA_MA[15]
TYCO_2013620-3_IVYBRIDGE
TYCO_2013620-3_IVYBRIDGE
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandy Bridge (3/6)
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 8 of 61
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
@ RC51
1K_0402_1%~D
2
D JCPU1E CONN@ D
AH27 @ T39 PAD~D
CFG0 VCC_DIE_SENSE
<7> CFG0 AK28 AH26
CFG1 CFG[0] VSS_DIE_SENSE
<7> CFG1 AK29
CFG[1] PEG Static Lane Reversal - CFG2 is for the 16x
CFG2 AL26
<7> CFG2 CFG3 CFG[2]
<7> CFG3 AL27
CFG4 CFG[3]
<7> CFG4 AK26
CFG[4] RSVD28
L7 @ T1 PAD~D 1:(Default) Normal Operation; Lane #
CFG5 AL29 AG7 @ T2 PAD~D CFG2
<7> CFG5 CFG6 AL30
CFG[5] RSVD29
AE7 @ T3 PAD~D
definition matches socket pin map definition
<7> CFG6 CFG7 CFG[6] RSVD30
<7> CFG7 AM31 CFG[7] RSVD31 AK2 @ T4 PAD~D 0:Lane Reversed
CFG8 AM32
<7> CFG8 CFG9 CFG[8]
AM30 W8 @ T5 PAD~D
<7> CFG9 CFG10 CFG[9] RSVD32
CFG
<7> CFG10 AM28 CFG[10]
CFG11 AM26 CFG4
<7> CFG11 CFG12 CFG[11]
AN28 AT26 @ T6 PAD~D
CFG[12] RSVD33
1
+VCC_GFXCORE CFG13 AN31 AM33 @ T7 PAD~D
CFG14 CFG[13] RSVD34 @ T8 PAD~D @ RC52
AN26 CFG[14] RSVD35 AJ27
1 2 VAXG_VAL_SENSE CFG15 AM27 1K_0402_1%~D
@RC122
@ RC122 49.9_0402_1%~D CFG16 CFG[15]
<7> CFG16 AK31 CFG[16]
1
CFG17 AN29
<7> CFG17
2
@ RC69 CFG[17]
100_0402_1%~D
T8 @ T11 PAD~D
RSVD37 @ T13 PAD~D
J16
2
RSVD38
1 2 VSSAXG_VAL_SENSE VAXG_VAL_SENSE AJ31 VAXG_VAL_SENSE RSVD39 H16 @ T15 PAD~D
@RC123
@ RC123 49.9_0402_1%~D VSSAXG_VAL_SENSE AH31 G16 @ T16 PAD~D
VCC_VAL_SNESE VSSAXG_VAL_SENSE RSVD40
AJ33 VCC_VAL_SENSE Display Port Presence Strap
VSS_VAL_SNESE AH33 VSS_VAL_SENSE
C C
1 : Disabled; No Physical Display Port
PAD~D T22 @ AJ26 RSVD5 RSVD_NCTF1 AR35 @ T17 PAD~D CFG4 attached to Embedded Display Port
AT34 @ T18 PAD~D
RSVD_NCTF2 @ T19 PAD~D
AT33
RESERVED
RSVD_NCTF3
RSVD_NCTF4 AP35 @ T20 PAD~D 0 : Enabled; An external Display Port device is
AR34 @ T21 PAD~D
+VCC_CORE RSVD_NCTF5 connected to the Embedded Display Port
1 2 VCC_VAL_SNESE PAD~D T28 @ F25
@RC120
@ RC120 49.9_0402_1%~D PAD~D T29 @ RSVD8
F24
RSVD9
1
PAD~D T30 @ F23 CFG6
@ RC71 PAD~D T31 @ RSVD10 @ T23 PAD~D
D24 B34
PAD~D T33 @ RSVD11 RSVD_NCTF6 @ T24 PAD~D CFG5
100_0402_1%~D G25 A33
PAD~D T35 @ RSVD12 RSVD_NCTF7 @ T25 PAD~D
G24 A34
RSVD13 RSVD_NCTF8
1
PAD~D T36 @ E23 B35 @ T26 PAD~D
2
VSS_VAL_SNESE PAD~D T37 @ RSVD14 RSVD_NCTF9 @ T27 PAD~D @ RC54 @ RC53
1 2 D23 C35
@RC121
@ RC121 49.9_0402_1%~D PAD~D T38 @ RSVD15 RSVD_NCTF10 1K_0402_1%~D
C30 1K_0402_1%~D
PAD~D T40 @ RSVD16
A31
PAD~D T41 @ RSVD17
B30
2
PAD~D T42 @ RSVD18
B29
PAD~D T43 @ RSVD19 @ T32 PAD~D
D30 AJ32
PAD~D T44 @ RSVD20 RSVD51 @ T34 PAD~D
B31 AK32
PAD~D T45 @ RSVD21 RSVD52
A30
PAD~D T46 @ RSVD22
C29
RSVD23
AN35 CLK_XDP_ITP <7>
PAD~D T47 @ BCLK_ITP
J20 AM35 CLK_XDP_ITP# <7>
PAD~D T48 @ RSVD24 BCLK_ITP#
B18
RSVD25 PCIE Port Bifurcation Straps
11: (Default) x16 - Device 1 functions 1 and 2 disabled
PAD~D T52 @ J15 AT2 @ T49 PAD~D
B RSVD27 RSVD_NCTF11 B
RSVD_NCTF12
AT1 @ T50 PAD~D CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
AR1 @ T51 PAD~D
RSVD_NCTF13 disabled
01: Reserved - (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D
2 enabled)
KEY
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
TYCO_2013620-3_IVYBRIDGE CFG7
1
@ RC56
1K_0402_1%~D
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately
CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Ivy/Sandy Bridge (4/6)
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 9 of 61
Rev
1.0
5 4 3 2 1
JCPU1F POWER
+1.05V_RUN_VTT
+VCC_CORE
53A
AG35
8.5A
VCC1
AG34 AH13
VCC2 VCCIO1
AG33 AH10
VCC3 VCCIO2
AG32 AG10
D VCC4 VCCIO3 D
AG31 AC10
VCC5 VCCIO4
AG30 Y10
VCC6 VCCIO5
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
AF33 J11
VCC13 VCCIO12
AF32 H14
VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 VCC19 VCCIO18 G12
AF26 F14
PEG AND DDR
VCC20 VCCIO19
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
C C
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 A11 +1.05V_RUN_VTT
VCC41 VCCIO39
AA34 VCC42
AA33 VCC43 VCCIO40 J23
1
AA32
VCC44 Note: Place the PU resistors close to CPU RC60
AA31
VCC45 75_0402_1%~D
AA30 RC61 close to CPU 300 - 1500mils
VCC46
AA29
VCC47
AA28
2
VCC48
AA27
VCC49 H_CPU_SVIDALRT#
AA26 1 2 VIDALERT_N <51>
VCC50 RC61 43_0402_5%~D
Y35
VCC51
Y34
CORE SUPPLY
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55 +1.05V_RUN_VTT
Y30
VCC56
Y29
VCC57
Y28 CAD Note: Place the PU
VCC58
1
Y27
VCC59 resistors close to CPU
Y26 RC63 RC63 close to CPU 300 - 1500mils
VCC60 130_0402_1%~D
V35
VCC61 H_CPU_SVIDALRT#
V34 AJ29
VCC62 VIDALERT# VIDSCLK Iccmax current changed for PDDG Rev0.7
SVID
V33 AJ30 VIDSCLK <51>
2
VCC63 VIDSCLK VIDSOUT
V32 AJ28 VIDSOUT <51>
VCC64 VIDSOUT
V31
V30
VCC65 CPU Power Rail Table
VCC66
V29
VCC67 H_CPU_SVIDALRT# must be routed between the S0 Iccmax
V28 Voltage Rail Voltage Current (A)
B
V27
VCC68 VIDSOUT and VIDSCLK lines to reduce cross B
VCC69
V26
VCC70
talk. 18 mils spacing to others.
U35
VCC71
VCC 0.65-1.3 53
U34
VCC72
U33
VCC73
U32
VCC74
VCCIO 1.05 8.5
U31
VCC75
U30
VCC76
U29
VCC77
VAXG 0.0-1.1 26
U28
VCC78
U27
VCC79
U26
VCC80
VCCPLL 1.8 3
R35 +VCC_CORE
VCC81
R34
VCC82
R33
VCC83
VDDQ 1.5 5
1
R32
VCC84 @ RC75 RC66
R31
VCC85
R30
VCC86 Place RC66, RC70near CPU 100_0402_1%~D 100_0402_1%~D VCCSA 0.65-0.9 6
R29 1 2
VCC87
R28
2
VCC88 VCCSENSE_R
R27 AJ35 1 2 +1.5V_MEM 1.5 12-16 *
SENSE LINES
VCC89 VCC_SENSE VCCSENSE <51>
R26 AJ34 VSSSENSE_R @ RC67 1 20_0402_5%~D
VCC90 VSS_SENSE VSSSENSE <51>
P35 @ RC68 0_0402_5%~D
VCC91
P34 2 1 +1.05V_RUN_VTT
VCC92
1
P33 RC98 10_0402_1%~D
VCC93 VTT_SENSE
P32
VCC94 VCCIO_SENSE
B10 VTT_SENSE <49> RC70 * Description
P31 A10 VSSIO_SENSE_R VSSIO_SENSE_R <49> 100_0402_1%~D
VCC95 VSS_SENSE_VCCIO
P30
VCC96
5A to Mem controller(+1.5V_CPU_VDDQ)
P29 5-6A to 2 DIMMs/channel
2
VCC97
1
10_0402_1%~D
P28
VCC98 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
P27
RC133
VCC99
P26 VCC100
A A
2
DELL CONFIDENTIAL/PROPRIETARY
TYCO_2013620-3_IVYBRIDGE CONN@
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Ivy/Sandy Bridge (5/6)
5 4
WWW.AliSaler.Com BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 10 of 61
Rev
1.0
5 4 3 2 1
+1.5V_CPU_VDDQ Source
+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 +PWR_SRC_S AO4304L_SO8
8 1 +V_DDR_SMREF +V_DDR_REF
10U_0603_6.3V6M~D
7 2
1
@
20K_0402_5%~D
6 3 1 1 2
+1.5V_MEM +1.5V_CPU_VDDQ
CC135
RC73
5 @ RC135 0_0402_5%~D JCPU1H
1
RC72
RC74 330K_0402_5%~D
1K_0402_1%~D
1K_0402_1%~D
1 2 AT35 AJ22
4
VSS1 VSS81
1
100K_0402_5%~D 2 @ @ RC134 0_0402_5%~D AT32 AJ19
2
D RUN_ON_CPU1.5VS3 VSS2 VSS82 D
AT29 AJ16
RC80
RC84
@ QC5 +V_SM_VREF_CNT VSS3 VSS83
AT27 AJ13
2
VSS4 VSS84
3
NTR4503NT1G_SOT23-3~D AT25 AJ10
VSS5 VSS85
DMN66D0LDW-7_SOT363-6~D
0.022U_0402_25V7K~D
AT22 AJ7
2
VSS6 VSS86
1
QC4B
1M_0402_5%~D
1 3 AT19 AJ4
VSS7 VSS87
RC143
RUN_ON_CPU1.5VS3# 5 1 AT16 AJ3
VSS8 VSS88
1K_0402_1%~D
1K_0402_1%~D
AT13 AJ2
VSS9 VSS89
1
CC136
@ AT10 AJ1
4
VSS10 VSS90
AT7 AH35
RC81
RC78
2
VSS11 VSS91
6
@ 1 2 2
<16,27,35,39,42,47,48,49> SIO_SLP_S3# 2 AT4 AH34
RC82 0_0402_5%~D VSS12 VSS92
AT3 AH32
QC4A VSS13 VSS93
AR25 AH30
2
DMN66D0LDW-7_SOT363-6~D VSS14 VSS94
<40> CPU1.5V_S3_GATE 1 2 2 AR22 VSS15 VSS95 AH29
@RC79
@ RC79 0_0402_5%~D AR19 AH28
VSS16 VSS96
AR16 AH25
1
RUN_ON_CPU1.5VS3 VSS17 VSS98
AR13 VSS18 VSS99 AH22
AR10 VSS19 VSS100 AH19
RUN_ON_CPU1.5VS3# <7,42> AR7 VSS20 VSS101 AH16
AR4 VSS21 VSS102 AH7
AR2 VSS22 VSS103 AH4
AP34 VSS23 VSS104 AG9
AP31 VSS24 VSS105 AG8
AP28 VSS25 VSS106 AG4
AP25 VSS26 VSS107 AF6
AP22 VSS27 VSS108 AF5
AP19 VSS28 VSS109 AF3
+VCC_GFXCORE AP16 AF2
VSS29 VSS110
AP13 VSS30 VSS111 AE35
AP10 AE34
POWER VSS31 VSS112
1
AP7 VSS32 VSS113 AE33
+VCC_GFXCORE RC99 @RC76
@ RC76 AP4 AE32
JCPU1G VSS33 VSS114
100_0402_1%~D 100_0402_1%~D AP1 VSS34 VSS115 AE31
C C
1 2 AN30 VSS35 VSS116 AE30
33A AN27 AE29
2
VSS36 VSS117
AT24 AK35 AN25 AE28
VAXG1 VAXG_SENSE VCC_AXG_SENSE <51> VSS37
VSS VSS118
SENSE
LINES
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <51> AN22 VSS38 VSS119 AE27
AT21 VAXG3 AN19 VSS39 VSS120 AE26
1
AT20 VAXG4 AN16 VSS40 VSS121 AE9
AT18 RC100 AN13 AD7
VAXG5 VSS41 VSS122
AT17 100_0402_1%~D AN10 AC9
VAXG6 VSS42 VSS123
AR24 AN7 AC8
VAXG7 +V_SM_VREF_CNT VSS43 VSS124
AR23 AN4 AC6
2
VAXG8 VSS44 VSS125
AR21 +V_SM_VREF should AM29 AC5
VAXG9 VSS45 VSS126
AR20
VAXG10 have 10 mil trace width AM25
VSS46 VSS127
AC3
AR18 AL1 AM22 AC2
VAXG11 SM_VREF VSS47 VSS128
AR17 AM19 AB35
VAXG12 VSS48 VSS129
AP24 AM16 AB34
VAXG13 Intel is recommended to provide stitching capacitors for VSS49 VSS130
AP23
AP21
VAXG14 VREF Vccd power planes +1.5V_MEM and +1.5V_CPU_VDDQ
AM13
AM10
VSS50 VSS131
AB33
AB32
VAXG15 +DIMM0_1_VREF_CPU (Follow Intel CRB) _0721 VSS51 VSS132
AP20 B4 +DIMM0_1_VREF_CPU AM7 AB31
VAXG16 SA_DIMM_VREFDQ +DIMM0_1_CA_CPU VSS52 VSS133
AP18 D1 +DIMM0_1_CA_CPU AM4 AB30
VAXG17 SB_DIMM_VREFDQ VSS53 VSS134
AP17 AM3 AB29
VAXG18 CC178 VSS54 VSS135
AN24
VAXG19 2 1 0.1U_0402_10V7K~D AM2
VSS55 VSS136
AB28
AN23 AM1 AB27
VAXG20 +1.5V_CPU_VDDQ VSS56 VSS137
AN21 AL34 AB26
VAXG21 CC179 VSS57 VSS138
AN20 2 1 0.1U_0402_10V7K~D AL31 Y9
VAXG22 VSS58 VSS139
AN18
VAXG23 6A AL28
VSS59 VSS140
Y8
AN17
5A AL25 Y6
DDR3 -1.5V RAILS
VAXG24 CC149 VSS60 VSS141
AM24 AF7 2 1 0.1U_0402_10V7K~D +1.5V_MEM AL22 Y5
VAXG25 VDDQ1 VSS61 VSS142
GRAPHICS
AM23 AF4 AL19 Y3
VAXG26 VDDQ2 VSS62 VSS143
AM21 AF1 1 AL16 Y2
VAXG27 VDDQ3 VSS63 VSS144
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
AM20 AC7 1 1 1 1 1 1 CC150 2 1 0.1U_0402_10V7K~D AL13 W35
VAXG28 VDDQ4 + VSS64 VSS145
AM18 AC4 AL10 W34
VAXG29 VDDQ5 VSS65 VSS146
CC161
CC162
CC163
CC164
CC165
CC166
CC167
AM17 AC1 AL7 W33
B VAXG30 VDDQ6 VSS66 VSS147 B
AL24 Y7 AL4 W32
VAXG31 VDDQ7 2 2 2 2 2 2 2 VSS67 VSS148
AL23 Y4 AL2 W31
VAXG32 VDDQ8 VSS68 VSS149
AL21 Y1 AK33 W30
VAXG33 VDDQ9 VSS69 VSS150
AL20 U7 AK30 W29
VAXG34 VDDQ10 VSS70 VSS151
AL18 U4 AK27 W28
VAXG35 VDDQ11 VSS71 VSS152
AL17 U1 AK25 W27
VAXG36 VDDQ12 VSS72 VSS153
AK24 P7 AK22 W26
VAXG37 VDDQ13 VSS73 VSS154
AK23 P4 AK19 U9
VAXG38 VDDQ14 VSS74 VSS155
AK21 P1 AK16 U8
VAXG39 VDDQ15 VSS75 VSS156
AK20 AK13 U6
VAXG40 VSS76 VSS157
AK18 AK10 U5
VAXG41 VSS77 VSS158
AK17 AK7 U3
VAXG42 VSS78 VSS159
AJ24 AK4 U2
VAXG43 VSS79 VSS160
AJ23 AJ25
VAXG44 VSS80
2 +DIMM0_1_VREF_CPU
1
@ RC96 1K_0402_1%~D
AJ21
AJ20
VAXG45 6A
VAXG46
1 2 +DIMM0_1_CA_CPU AJ18
@ RC97 1K_0402_1%~D VAXG47
AJ17 M27 +VCC_SA
VAXG48 VCCSA1
10U_0603_6.3V6M~D
330U_D2_2VM_R6M~D
AH24 M26 TYCO_2013620-3_IVYBRIDGE
VAXG49 VCCSA2
SA RAIL
AH23 L26
VAXG50 VCCSA3
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
AH21 J26 1 @ 1 1 1 1 CONN@
VAXG51 VCCSA4
AH20 J25
VAXG52 VCCSA5
CC168
CC169
CC170
CC171
CC172
AH18 J24 +
VAXG53 VCCSA6
AH17 H26
VAXG54 VCCSA7 2 2 2 2
H25
VCCSA8 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
H23 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
1.8V RAIL
VCCSA_SENSE VCCSA_SENSE <50>
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
A 1.2A PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
B6 added VCCSA_VID_0 to Power page
+1.8V_RUN VCCPLL1
330U_D2_2.5VM_R6M~D
A6 VCCPLL2 VCCSA_VID[0] C22 VCCSA_VID_0 <50>
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
MISC
1 1 1 1 A2 VCCPLL3 VCCSA_VID[1] C24 VCCSA_VID_1 <50>
CC176
DELL CONFIDENTIAL/PROPRIETARY
CC173
CC174
CC175
2 2 2
2 VCCIO_SEL A19
@ RC140
1 2
0_0402_5%~D
VCCP_PWRCTRL <49> Compal Electronics, Inc.
Title
TYCO_2013620-3_IVYBRIDGE Depop RC140 for ES2 CPU
Ivy/Sandy Bridge (6/6)
5
CONN@
4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 11 of 61
Rev
1.0
5 4 3 2 1
+DIMM1_VREF_DQ
+V_DDR_REFA_M3 1
@ RD7
2
0_0402_5%~D +1.5V_MEM
JDIMM1 +1.5V_MEM 2-3A to 1 DIMMs/channel
CONN@
+V_DDR_REF 1
@ RD1
2
0_0402_5%~D
1
3
VREF_DQ
VSS2
VSS1
DQ4
2
4 DDR_A_D4
JDIMM1 H=8
DDR_A_D0 5 6 DDR_A_D5 Follow CONN List_0609A
DDR_A_D1 DQ0 DQ5
7 DQ1 VSS3 8
+1.5V_MEM
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
9 10 DDR_A_DQS#0
VSS4 DQS#0 DDR_A_DQS0
11 DM0 DQS0 12
1 1 13 VSS5 VSS6 14
CD2
DDR_A_D2 15 16 DDR_A_D6
DQ2 DQ6
1
CD1
DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7 RD27
19 20
D 2 2 DDR_A_D8 VSS7 VSS8 DDR_A_D12 1K_0402_1%~D D
21 22
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
25 26
2
DDR_A_DQS#1 VSS9 VSS10
27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#_R DDR3_DRAMRST#_R 1
29 30 <13> DDR3_DRAMRST#_R 2 DDR3_DRAMRST# <7>
DQS1 RESET# RD28 1K_0402_1%~D
31 32
DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
Populate RD1, De-Populate RD7 for Intel DDR3 39
DQ16 DQ20
40
DDR_A_D17 41 42 DDR_A_D21
VREFDQ multiple methods M1 43
DQ17 DQ21
44
Populate RD7, De-Populate RD1 for Intel DDR3 DDR_A_DQS#2 VSS15 VSS16
45 DQS#2 DM2 46
VREFDQ multiple methods M3 DDR_A_DQS2 47 48
DQS2 VSS17 DDR_A_D22 @ RD29 1
49 VSS18 DQ22 50 2 0_0402_5%~D
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_A_D28 QD1
VSS20 DQ28
D
All VREF traces should DDR_A_D24 57 58 DDR_A_D29 +DIMM0_1_VREF_CPU 3 1 BSS138_NL_SOT23-3 +V_DDR_REFA_M3
DDR_A_D25 DQ24 DQ29
have 10 mil trace width 59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS3
63 64
G
2
DM3 DQS3
<8> DDR_A_DQS#[0..7] 65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30 DDR_HVREF_RST
DDR_A_D27 DQ26 DQ30 DDR_A_D31 <7> DDR_HVREF_RST
<8> DDR_A_D[0..63] 69 DQ27 DQ31 70
71 VSS25 VSS26 72
<8> DDR_A_DQS[0..7]
@ RD30 1 2 0_0402_5%~D
<8> DDR_A_MA[0..15] DDR_CKE0_DIMMA DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA 73 CKE0 CKE1 74 DDR_CKE1_DIMMA <8>
75 VDD1 VDD2 76
77 78 DDR_A_MA15 QD2
C NC1 A15 C
D
DDR_A_BS2 79 80 DDR_A_MA14 3 1 BSS138_NL_SOT23-3
<8> DDR_A_BS2 BA2 A14 +DIMM0_1_CA_CPU +V_DDR_REFB_M3
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
Layout Note:
G
85 86
2
A9 A7
87 88
Place near JDIMM1 DDR_A_MA8 89
VDD5 VDD6
90 DDR_A_MA6 DDR_HVREF_RST
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
95
A3 A2
96 M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 100
+1.5V_MEM M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
<8> M_CLK_DDR0 101 102 M_CLK_DDR1 <8>
M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
<8> M_CLK_DDR#0 103 104 M_CLK_DDR#1 <8>
CK0# CK1#
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
107 108 DDR_A_BS1 <8>
A10/AP BA1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_A_BS0 109 110 DDR_A_RAS#
<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8>
1 1 1 1 111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
<8> DDR_A_WE# 113 114 DDR_CS0_DIMMA# <8>
WE# S0#
CD3
CD4
CD5
CD6
DDR_A_CAS# 115 116 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 118
2 2 2 2 DDR_A_MA13 VDD15 VDD16 M_ODT1 +DIMM1_VREF_CA
119 120 M_ODT1 <8>
DDR_CS1_DIMMA# A13 ODT1
<8> DDR_CS1_DIMMA# 121 122
S1# NC2
123 124
VDD17 VDD18
125 126 2 1 +V_DDR_REF
NCTEST VREF_CA @ RD11 0_0402_5%~D
127 128
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
133 134 1 1
VSS29 VSS30
CD15
CD16
DDR_A_DQS#4 135 136
+1.5V_MEM DDR_A_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_A_D38
139 140
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 142
B DDR_A_D35 DQ34 DQ39 B
143 144
DQ35 VSS33
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
145 146 DDR_A_D44
DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
DQ40 DQ45
330U_SX_2VY~D
1 DDR_A_D41 149 150
DQ41 VSS35
@ CD13
1 1 1 1 1 1 1 151 152 DDR_A_DQS#5
VSS36 DQS#5
CD7
CD8
CD9
CD10
CD11
CD51
CD14
+ 153 154 DDR_A_DQS5
DM5 DQS5
155 156
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
2 2 2 2 2 2 2 2 DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
DQ49 DQ53
167 168
DDR_A_DQS#6 VSS41 VSS42
169 170
DDR_A_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_A_D54
173 174
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
Layout Note: 179
VSS46 DQ60
180
DDR_A_D56 181 182 DDR_A_D61
Place near JDIMM1.203,204 DDR_A_D57 183
DQ56 DQ61
184
DQ57 VSS47 DDR_A_DQS#7
185 186
VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
RD21 VSS51 VSS52
2 10K_0402_5%~D 197 198
+0.75V_DDR_VTT SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT <7,13,14,15,27,34>
VDDSPD SDA
1 2 201
SA1 SCL
202 DDR_XDP_WAN_SMBCLK <7,13,14,15,27,34>
RD3 10K_0402_5%~D 1 1 203 204 +0.75V_DDR_VTT
VTT1 VTT2
0.1U_0402_25V6K~D
2.2U_0603_6.3V6K~D
+0.75V_DDR_VTT
CD22
A A
205 G1 G2 206
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD21
2 2 TYCO_2-2013298-1~D
1 1 1 1
CD17
CD18
CD19
CD20
2 2 2 2 Reverse Type DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
5 4
WWW.AliSaler.Com BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 12 of 61
Rev
1.0
5 4 3 2 1
+DIMM2_VREF_DQ +1.5V_MEM CONN@ +1.5V_MEM
JDIMM2
+V_DDR_REFB_M3 1 2 1 2
2-3A to 1 DIMMs/channel
@ RD8 0_0402_5%~D VREF_DQ VSS1 DDR_B_D4
3 4
VSS2 DQ4
JDIMM2 H=4
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
+V_DDR_REF 1 2 7 DQ1 VSS3 8
@ RD4 0_0402_5%~D 1 1 9 10 DDR_B_DQS#0
VSS4 DQS#0
CD24
DDR_B_DQS0
11 DM0 DQS0 12 Check connection and symbol
CD23
13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
D DQ9 DQ13 D
25 26
DDR_B_DQS#1 VSS9 VSS10
27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R <12>
DQS1 RESET#
31 32
DDR_B_D10 VSS11 VSS12 DDR_B_D14
33 34
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37 38
DDR_B_D16 VSS13 VSS14 DDR_B_D20
39 40
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16
45 46
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
Populate RD4, De-Populate RD8 for Intel DDR3 DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
VREFDQ multiple methods M1 55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
Populate RD8, De-Populate RD4 for Intel DDR3 DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
VREFDQ multiple methods M3 61 62 DDR_B_DQS#3
VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
<8> DDR_B_DQS#[0..7] 71 VSS25 VSS26 72
<8> DDR_B_D[0..63]
All VREF traces should
have 10 mil trace width
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
<8> DDR_B_DQS[0..7] <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
<8> DDR_B_MA[0..15] NC1 A15
DDR_B_BS2 79 80 DDR_B_MA14
<8> DDR_B_BS2 BA2 A14
81 VDD3 VDD4 82
C DDR_B_MA12 DDR_B_MA11 C
83 A12/BC# A11 84
Layout Note: DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 88
Place near JDIMM2 DDR_B_MA8 89
VDD5 VDD6
90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
<8> M_CLK_DDR2 101 102 M_CLK_DDR3 <8>
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
<8> M_CLK_DDR#2 103 104 M_CLK_DDR#3 <8>
+1.5V_MEM CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108 DDR_B_BS1 <8>
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
<8> DDR_B_BS0 109 110
BA0 RAS# DDR_B_RAS# <8>
111 112
VDD13 VDD14
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_WE# 113 114 DDR_CS2_DIMMB#
<8> DDR_B_WE# DDR_B_CAS# WE# S0# M_ODT2 DDR_CS2_DIMMB# <8>
1 1 1 1 <8> DDR_B_CAS# 115 116 M_ODT2 <8>
CAS# ODT0
117 118
VDD15 VDD16 +DIMM2_VREF_CA
CD25
CD26
CD27
CD28
DDR_B_MA13 119 120 M_ODT3
DDR_CS3_DIMMB# A13 ODT1 M_ODT3 <8>
<8> DDR_CS3_DIMMB# 121 122
2 2 2 2 S1# NC2
123 124
VDD17 VDD18
125 126 2 1 +V_DDR_REF
NCTEST VREF_CA @ RD15 0_0402_5%~D
127 128
VSS27 VSS28
2.2U_0603_6.3V6K~D
0.1U_0402_25V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134 1 1
VSS29 VSS30
CD38
DDR_B_DQS#4 135 136
DQS#4 DM4
CD37
DDR_B_DQS4 137 138
+1.5V_MEM DQS4 VSS31 DDR_B_D38
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_B_D44
145 146
VSS34 DQ44
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
330U_SX_2VY~D
B DDR_B_D40 DDR_B_D45 B
147 148
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
1 151 152
VSS36 DQS#5
@ CD35
1 1 1 1 1 1 1 153 154 DDR_B_DQS5
DM5 DQS5
CD29
CD30
CD31
CD32
CD33
CD34
CD36
+ 155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
2 2 2 2 2 2 2 2 DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42
169 170
DDR_B_DQS6 DQS#6 DM6
171 172
DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
Layout Note: 183
DQ57 VSS47
184
185 186 DDR_B_DQS#7
Place near JDIMM2.203,204 187
VSS48 DQS#7
188 DDR_B_DQS7
DM7 DQS7
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
+3.3V_RUN VSS51 VSS52
197 198
SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT <7,12,14,15,27,34>
VDDSPD SDA
2 1 201 202 DDR_XDP_WAN_SMBCLK <7,12,14,15,27,34>
+0.75V_DDR_VTT RD5 10K_0402_5%~D SA1 SCL
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT1 VTT2
1
10K_0402_5%~D
0.1U_0402_25V6K~D
RD6
205 206
G1 G2
2.2U_0603_6.3V6K~D
1 1
CD43
A FOX_AS0A626-U4RN-7F A
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CD44
2
1 1 1 1 2 2
CD39
CD40
CD41
CD42
Reverse Type DELL CONFIDENTIAL/PROPRIETARY
2 2 2 2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 13 of 61
Rev
1.0
5 4 3 2 1
CMOS_CLR1 CMOS setting PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin. +3.3V_ALW_PCH JXDP2
So signal should be PU to the ALWAYS rail. USB_OC0#_R XDP_FN0
Shunt Clear CMOS <17> USB_OC0#_R USB_OC1#_R
1 2
XDP_FN1 +3.3V_ALW_PCH
1 GND0 GND1 2
XDP_FN16
PXDP@ RH1 1 2 33_0402_5%~D 3 4
<17> USB_OC1#_R USB_OC2# PXDP@ RH3 33_0402_5%~D XDP_FN2 OBSFN_A0 OBSFN_C0 XDP_FN17
Open Keep CMOS +3.3V_ALW_PCH <17> USB_OC2# USB_OC3#
1 2
XDP_FN3
5 OBSFN_A1 OBSFN_C1 6
PXDP@ RH4 1 2 33_0402_5%~D 1 7 8
<17> USB_OC3# USB_OC4#_R PXDP@ RH5 33_0402_5%~D XDP_FN4 PXDP@ XDP_FN0 GND2 GND3 XDP_FN8
1 2 9 OBSDATA_A0 OBSDATA_C0 10
<17> USB_OC4#_R USB_OC5# PXDP@ RH6 33_0402_5%~D XDP_FN5 CH1 XDP_FN1 XDP_FN9
ME_CLR1 TPM setting <17> USB_OC5#
1 2 11 OBSDATA_A1 OBSDATA_C1 12
1
USB_OC6# PXDP@ RH7 1 2 33_0402_5%~D XDP_FN6 0.1U_0402_25V6K~D 13 14
RH66 <17> USB_OC6# SIO_EXT_SMI# PXDP@ RH8 33_0402_5%~D XDP_FN7 2 XDP_FN2 GND4 GND5 XDP_FN10
Shunt Clear ME RTC Registers <17,40> SIO_EXT_SMI# SLP_ME_CSW_DEV#
1 2
XDP_FN8 XDP_FN3
15 OBSDATA_A2 OBSDATA_C2 16
XDP_FN11
1K_0402_1%~D PXDP@ RH9 1 2 33_0402_5%~D 17 18
<18,39> SLP_ME_CSW_DEV# USB_MCARD1_DET# PXDP@ RH10 33_0402_5%~D XDP_FN9 OBSDATA_A3 OBSDATA_C3
Open Keep ME RTC Registers <18,34> USB_MCARD1_DET# HDD_DET#_R
1 2
XDP_FN10
19 GND6 GND7 20
PXDP@ RH12 1 2 33_0402_5%~D 21 22
2
BBS_BIT0_R PXDP@ RH13 33_0402_5%~D XDP_FN11 OBSFN_B0 OBSFN_D0
1 2 23 OBSFN_B1 OBSFN_D1 24
PCH_GPIO36 PXDP@ RH14 1 2 33_0402_5%~D XDP_FN12 25 26
+RTC_CELL PCH_AZ_SYNC <18> PCH_GPIO36 PCH_GPIO37 PXDP@ RH15 33_0402_5%~D XDP_FN13 XDP_FN4 GND8 GND9 XDP_FN12
1 2 27
OBSDATA_B0 OBSDATA_D0
28
<18> PCH_GPIO37 PCH_GPIO16 PXDP@ RH16 33_0402_5%~D XDP_FN14 XDP_FN5 XDP_FN13
1 2 29
OBSDATA_B1 OBSDATA_D1
30
1
<18> PCH_GPIO16 TEMP_ALERT# PXDP@ RH17 33_0402_5%~D XDP_FN15
1 2 31 32
<18,39> TEMP_ALERT# GND10 GND11
1
RH282 @ PCH_GPIO15 PXDP@ RH18 1 2 33_0402_5%~D XDP_FN16 XDP_FN6 33 34 XDP_FN14
D
RH38 100K_0402_5%~D <18> PCH_GPIO15 SIO_EXT_SCI#_R PXDP@ RH19 33_0402_5%~D XDP_FN17 XDP_FN7 OBSDATA_B2 OBSDATA_D2 XDP_FN15
D
1 2 35 36
330K_0402_1%~D <18> SIO_EXT_SCI#_R PXDP@ RH20 33_0402_5%~D PXDP@ RH283 1K_0402_1%~D OBSDATA_B3 OBSDATA_D3
37 38
GND12 GND13 +3.3V_ALW_PCH
1 2 RSMRST#_XDP 1 2 1.05V_0.8V_PWROK_R 39 40
2
<16,41> PCH_RSMRST#_Q <40,51> 1.05V_0.8V_PWROK PCH_PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4
PXDP@ RH24 1K_0402_1%~D 1 2 41 42
2
<7,16> SIO_PWRBTN#_R HOOK1 ITPCLK#/HOOK5
PCH_INTVRMEN PXDP@ RH21 0_0402_5%~D 43 44
VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP
45 46
HOOK2 RESET#/HOOK6
1
47 48 XDP_DBRESET#
@ RH39
@RH39 PXDP@ RH284 0_0402_5%~D HOOK3 DBR#/HOOK7 XDP_DBRESET# <7,16>
On Die PLL VR is supplied by 49
GND14 GND15
50
330K_0402_1%~D CH2
<7,12,13,15,27,34> DDR_XDP_WAN_SMBDAT 1 2 DDR_XDP_WAN_SMBDAT_R2 51 52 PCH_JTAG_TDO
1.5V when sampled high, 1.8 V 18P_0402_50V8J~D 1 2 DDR_XDP_WAN_SMBCLK_R2 53
SDA TD0
54
<7,12,13,15,27,34> DDR_XDP_WAN_SMBCLK SCL TRST#
when sampled low 2 1 PCH_RTCX1 PXDP@ RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
2
PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS
57 58
TCK0 TMS
59 60
GND16 GND17
1
INTVRMEN- Integrated SUS YH1 RH2 SAMTE_BSH-030-01-L-D-A CONN@
32.768KHZ_12.5PF_Q13FC1350000~D 10M_0402_5%~D UH4A
1.1V VRM Enable
2
* High - Enable Internal VRs CH3 A20 C38 LPC_LAD0
2
RTCX1 FWH0 / LAD0 LPC_LAD1 LPC_LAD0 <32,34,39,40>
18P_0402_50V8J~D A38
Low - Enable External VRs FWH1 / LAD1 LPC_LAD1 <32,34,39,40> +3.3V_RUN
2 1 PCH_RTCX2_R 1 2 PCH_RTCX2 C20 B37 LPC_LAD2
LPC
RTCX2 FWH2 / LAD2 LPC_LAD2 <32,34,39,40>
@ RH286 0_0402_5%~D C37 LPC_LAD3
FWH3 / LAD3 LPC_LAD3 <32,34,39,40>
1 2 PCH_RTCRST# D20
+RTC_CELL RTCRST#
RH22 20K_0402_5%~D D36 LPC_LFRAME# PCH_GPIO33 2 1
SRTCRST# FWH4 / LFRAME# LPC_LFRAME# <32,34,39,40>
1 2 G22 RH355 100K_0402_5%~D
RH23 20K_0402_5%~D SRTCRST#
E36
INTRUDER# LDRQ0# LPC_LDRQ1# IRQ_SERIRQ 2
1 2 K22 K36 1
RTC
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# <39>
RH11 1M_0402_5%~D RH28 8.2K_0402_5%~D
2 1 PCH_INTVRMEN C17 V5 IRQ_SERIRQ
INTVRMEN SERIRQ IRQ_SERIRQ <32,39,40>
@CH100
@ CH100
27P_0402_50V8J~D
1 2 1 2 AM3 PSATA_PRX_DTX_N0_C <27>
1 2 1 2 PCH_AZ_BITCLK SATA0RXN BBS_BIT0_R
<37> PCH_AZ_MDC_BITCLK 1 2 N34 AM1 PSATA_PRX_DTX_P0_C <27> 2 1
RH32 33_0402_5%~D HDA_BCLK SATA0RXP RH52 4.7K_0402_5%~D
AP7 HDD
SATA 6G
SATA0TXN PSATA_PTX_DRX_N0_C <27>
<37> PCH_AZ_MDC_SYNC 1 2PCH_AZ_SYNC_Q PCH_AZ_SYNC L34
HDA_SYNC SATA0TXP
AP5 INTEL feedback 0302
@ @ RH33 33_0402_5%~D PSATA_PTX_DRX_P0_C <27>
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
<29> SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C <28>
1 2 1 2 AM8 SATA_ODD_PRX_DTX_P1_C <28>
CH5 1U_0402_6.3V6K~D CH4 1U_0402_6.3V6K~D PCH_AZ_RST# SATA1RXP
<37> PCH_AZ_MDC_RST# 1 2 K34
HDA_RST# SATA1TXN
AP11
SATA_ODD_PTX_DRX_N1_C <28> ODD/ E Module Bay
CMOS place near DIMM RH34 33_0402_5%~D AP10
C
SATA1TXP SATA_ODD_PTX_DRX_P1_C <28> C
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
<29> PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
AD5
SATA2RXP
<29> PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT <37> PCH_AZ_MDC_SDIN1
PCH_AZ_MDC_SDIN1 G34
HDA_SDIN1 SATA2TXN
AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
+3.3V_ALW_PCH SATA2TXP
<29> PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @ RH35 10K_0402_5%~D
RH26 33_0402_5%~D HDA_SDIN2
1 2 AB8
IHDA
SATA3RXN
<29> PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# @ RH287 1K_0402_1%~D A34
HDA_SDIN3 SATA3RXP
AB10 No Reboot Strap
RH27 33_0402_5%~D 1 2 AF3
<37> PCH_AZ_MDC_SDOUT SATA3TXN
<29> PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK RH36 33_0402_5%~D AF1 Low = Default
PCH_AZ_SDOUT SATA3TXP
1 RH25 33_0402_5%~D <39> ME_FWP 1 2 A36 SPKR
HDA_SDO
RH50 1K_0402_1%~D Y7 ESATA_PRX_DTX_N4_C <36>
High = No Reboot
SATA
@ CH101
@CH101 SATA4RXN
Y5 ESATA_PRX_DTX_P4_C <36>
27P_0402_50V8J~D +3.3V_ALW_PCH PCH_GPIO33 SATA4RXP
2
C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3
ESATA_PTX_DRX_N4_C <36> E-SATA
AD1
SATA4TXP ESATA_PTX_DRX_P4_C <36>
1
@ PCH_GPIO13 N32
RH288 HDA_DOCK_RST# / GPIO13
Y3 SATA_PRX_DKTX_N5_C <38>
SATA5RXN
0_0603_5%~D Y1 SATA_PRX_DKTX_P5_C <38>
SATA5RXP +3.3V_ALW_PCH
SATA5TXN
AB3
SATA_PTX_DKRX_N5_C <38> DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2
JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C <38>
+3.3V_ALW_PCH_JTAG RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN PCH_GPIO13 2 1
JTAG_TMS SATAICOMPO R712 100K_0402_5%~D
JTAG
RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
JTAG_TDO +1.05V_RUN
AB12
SATA3RCOMPO
100_0402_1%~D
100_0402_1%~D
100_0402_1%~D
AB13 SATA3_COMP 1 2
SATA3COMPI
1
RH42 49.9_0402_1%~D
+3.3V_RUN
RH48
RH49
RH47
PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
SPI_CLK SATA3RBIAS RH46 750_0402_1%~D
1
10P_0402_50V8J~D
@ @ @ PCH_SPI_CS0# Y14
2
SPI_CS0#
Follow INTEL CRB 0.7 1 RH30
PCH_SPI_CS1# T1 10K_0402_5%~D
SPI_CS1#
CE15
P3 SATA_ACT#
SPI
@ SATALED# SATA_ACT# <43>
2
2 PCH_SPI_DO V4 V14 HDD_DET#_R 1 2
SPI_MOSI SATA0GP / GPIO21 HDD_DET# <27>
@RH290
@ RH290 0_0402_5%~D
B B
PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3
S
SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# <40>
S
PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC
RF review in 0629 BD82HM77 SLJ8C C1_BGA989~D QH1 BSS138W-7-F_SOT323-3~D
G
2
1 2 QH7
RH31 1M_0402_5%~D SSM3K7002FU_SC70-3~D
G
2
<7,17> PCH_PLTRST#
+5V_RUN BBS_BIT0 - BIOS BOOT STRAP BIT 0
INTEL HDA_SYNC
isolation circuit +3.3V_SPI C746
0.1U_0402_25V6K~D
1 2
+3.3V_SPI C745
1
0.1U_0402_25V6K~D
200 MIL SO8
1
R890 1 2
3.3K_0402_5%~D R891
64Mb Flash ROM 3.3K_0402_5%~D
U52 200 MIL SO8
2
SPI_PCH_CS0# 1 2 SPI_PCH_CS0#_R 1 8 JSPI1
32Mb Flash ROM
2
R935 47_0402_5%~D /CS VCC SPI_PCH_CS1#
1 1 2
SPI_PCH_DIN 1
1 2 SPI_DIN64 2 7 SPI_HOLD# U53 2 PCH_SPI_CS1# RH345 0_0402_5%~D
DO /HOLD SPI_PCH_CS1# 1 2
R894 33_0402_5%~D 2 SPI_PCH_CS1#_R 1 8 3 SPI_PCH_DO 1 2
SPI_WP#_SEL CS# VCC 3
<39> SPI_WP#_SEL 1 2 SPI_WP#_SEL_R 3
/WP CLK
6 SPI_CLK64 1 2 SPI_PCH_CLK R936 47_0402_5%~D 2
DO HOLD#
7 SPI_HOLD#
4
4 PCH_SPI_DO RH346 0_0402_5%~D
@ R898 0_0402_5%~D R899 33_0402_5%~D SPI_PCH_DIN 1 2 SPI_DIN32 3 6 SPI_CLK32 1 2 SPI_PCH_CLK 5 SPI_PCH_DIN 1 2
SPI_DO64 WP# CLK 5
4 5 1 2 SPI_PCH_DO R895 33_0402_5%~D 4 5 R897 33_0402_5%~D 6 PCH_SPI_DIN RH347 0_0402_5%~D
GND DIO SPI_WP#_SEL_R GND DI SPI_DO32 6
R901 33_0402_5%~D 1 2 SPI_PCH_DO 7 SPI_PCH_CLK 1 2
W25Q32BVSSIG_SO8 R900 33_0402_5%~D 7 PCH_SPI_CLK RH348 0_0402_5%~D
8
W25Q64CVSSIG_SO8~D 8 SPI_PCH_CS0#
9 1 2
9 PCH_SPI_CS0# RH349 0_0402_5%~D
10
10
11 +3.3V_SPI
11
12 +3.3V_M_RUN
12
13
13
14 1 2
SPI_CLK64 SPI_CLK32 14 RH360 0_0603_5%~D
15
15 +3.3V_RUN
16
16
1
@ @ 1 2 +3.3V_M_RUN
RE1 RE2 17 RH359 @ 0_0603_5%~D
33_0402_5%~D 33_0402_5%~D G1 +3.3V_M
18
A
G2 A
2
1 2
1 1 RH350 0_0603_5%~D
@ @
CE1 CE2 HRS_FH12-16S-0P5SH(55)~D
27P_0402_50V8J~D 27P_0402_50V8J~D CONN@
2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
PCH (1/8)
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7902P
Date: Wednesday, March 07, 2012 Sheet 14 of 61
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_RUN
QH5A
2
DMN66D0LDW-7_SOT363-6~D
6 1 MEM_SMBCLK MEM_SMBCLK 6 1
<30,40> SIO_LAN_SMBCLK DDR_XDP_WAN_SMBCLK <7,12,13,14,27,34>
QH8A
5
DMN66D0LDW-7_SOT363-6~D
3 4 MEM_SMBDATA MEM_SMBDATA 3 4
<30,40> SIO_LAN_SMBDATA DDR_XDP_WAN_SMBDAT <7,12,13,14,27,34>
QH8B QH5B
D DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D D
UH4B
PCIE_PRX_WANTX_N1 BG34
<34> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 PERN1 PCH_SMB_ALERT#
<34> PCIE_PRX_WANTX_P1 BJ34 E12
PCIE_PTX_WANRX_N1 PERP1 SMBALERT# / GPIO11 +3.3V_ALW_PCH
WWAN (Mini Card 1)---> <34> PCIE_PTX_WANRX_N1
AV32
PETN1
PCIE_PTX_WANRX_P1 AU32 H14 MEM_SMBCLK
<34> PCIE_PTX_WANRX_P1 PETP1 SMBCLK
PCIE_PRX_WLANTX_N2 BE34 C9 MEM_SMBDATA SML1_SMBCLK 1 2
<34> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34 RH298 2.2K_0402_5%~D
<34> PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PERP2 SML1_SMBDATA
WLAN (Mini Card 2)---> <34> PCIE_PTX_WLANRX_N2
BB32
PETN2 1 2
PCIE_PTX_WLANRX_P2 AY32 RH299 2.2K_0402_5%~D
<34> PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH
A12
SMBUS
PCIE_PRX_EXPTX_N3 SML0ALERT# / GPIO60 DDR_HVREF_RST_PCH <7> +3.3V_ALW_PCH
<35> PCIE_PRX_EXPTX_N3 BG36 PERN3
PCIE_PRX_EXPTX_P3 BJ36 C8 SML0CLK
<35> PCIE_PRX_EXPTX_P3 PCIE_PTX_EXPRX_N3 PERP3 SML0CLK
EXPRESS Card---> <35> PCIE_PTX_EXPRX_N3 AV34 PETN3
PCIE_PTX_EXPRX_P3 AU34 G12 SML0DATA DDR_HVREF_RST_PCH 2 1
<35> PCIE_PTX_EXPRX_P3 PETP3 SML0DATA RH300 1K_0402_1%~D
BF36 PCH_GPIO74 2 1
PERN4 RH301 10K_0402_5%~D
BE36 PERP4
AY34 C13 PCH_GPIO74 MEM_SMBCLK 2 1
PETN4 SML1ALERT# / PCHHOT# / GPIO74 RH302 2.2K_0402_5%~D
BB34 PETP4
E14 SML1_SMBCLK MEM_SMBDATA 2 1
PCIE_PRX_WPANTX_N5 SML1CLK / GPIO58 SML1_SMBCLK <30,40> RH303 2.2K_0402_5%~D
BG37
PCI-E*
<34> PCIE_PRX_WPANTX_N5 PCIE_PRX_WPANTX_P5 PERN5 SML1_SMBDATA PCH_SMB_ALERT#
1/2 MINI CARD-3 PCIE <34> PCIE_PRX_WPANTX_P5 BH37 PERP5 SML1DATA / GPIO75 M16 SML1_SMBDATA <30,40> 2 1
PCIE_PTX_WPANRX_N5 AY36 RH304 10K_0402_5%~D
(Mini Card 3)---> <34> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5 BB36
PETN5 PEG_A_CLKRQ# 2 1
<34> PCIE_PTX_WPANRX_P5 PETP5 RH80 10K_0402_5%~D
PCIE_PRX_MMITX_N6 BJ38
<33> PCIE_PRX_MMITX_N6 PCIE_PRX_MMITX_P6 PERN6
<33> PCIE_PRX_MMITX_P6 BG38 PERP6
MMI ---> PCIE_PTX_MMIRX_N6 AU36 M7 PCH_CL_CLK1 +3.3V_ALW_PCH
PCH_CL_CLK1 <34>
Controller
<33> PCIE_PTX_MMIRX_N6 PCIE_PTX_MMIRX_P6 PETN6 CL_CLK1
AV36 PETP6
C <33> PCIE_PTX_MMIRX_P6 C
PCIE_PRX_GLANTX_N7 BG40 T11 PCH_CL_DATA1 SML0CLK 2 1
Link
<30> PCIE_PRX_GLANTX_N7 PERN7 CL_DATA1 PCH_CL_DATA1 <34>
PCIE_PRX_GLANTX_P7 BJ40 RH305 2.2K_0402_5%~D
<30> PCIE_PRX_GLANTX_P7 PCIE_PTX_GLANRX_N7 PERP7 SML0DATA
10/100/1G LAN ---> <30> PCIE_PTX_GLANRX_N7 AY40 PETN7 2 1
PCIE_PTX_GLANRX_P7 BB40 P10 PCH_CL_RST1# RH306 2.2K_0402_5%~D
<30> PCIE_PTX_GLANRX_P7 PETP7 CL_RST1# PCH_CL_RST1# <34> PCH_CL_CLK1
BE38 PERN8
BC38 CLK_PCI_LOOPBACK
PERP8
10P_0402_50V8J~D
10P_0402_50V8J~D
AW38
PETN8 CLK_SMART_48M
AY38 1 1
PETP8
10P_0402_50V8J~D
CE17
CE16
M10 PEG_A_CLKRQ# 1
PCIE_MINI1# PEG_A_CLKRQ# / GPIO47 @ @
2 1 Y40
CLKOUT_PCIE0N
<34> CLK_PCIE_MINI1# 2 2
CE18
@ RH3072 10_0402_5%~D PCIE_MINI1 Y39
<34> CLK_PCIE_MINI1 CLKOUT_PCIE0P
WWAN (Mini Card 1)---> +3.3V_ALW_PCH @ RH3082 10_0402_5%~D CLKOUT_PEG_A_N
AB37 @
2
RH81 10K_0402_5%~D MINI1CLK_REQ# J2 AB38 RF review in 0913
<34> MINI1CLK_REQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P
CLOCKS
RF review in 0629
2 1 PCIE_LAN# AB49 AV22 CLK_CPU_DMI#
<30> CLK_PCIE_LAN# @ RH82 2 PCIE_LAN CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <7>
1 0_0402_5%~D AB47 AU22
<30> CLK_PCIE_LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <7>
10/100/1G LAN ---> @ RH83 0_0402_5%~D
LANCLK_REQ# M1 CLK_BUF_DMI# 1 2
<30> LANCLK_REQ# PCIECLKRQ1# / GPIO18
AM12 CLK_BUF_DMI RH74 1 2 10K_0402_5%~D
CLKOUT_DP_N RH75 10K_0402_5%~D
AM13
PCIE_MMI# CLKOUT_DP_P
2 1 AA48
<33> CLK_PCIE_MMI# PCIE_MMI CLKOUT_PCIE2N CLK_BUF_BCLK
MMI---> <33> CLK_PCIE_MMI
@ RH85 2 1 0_0402_5%~D AA47
CLKOUT_PCIE2P
1 2
@ RH86 1 2 0_0402_5%~D BF18 CLK_BUF_DMI# RH91 10K_0402_5%~D
+3.3V_RUN CLKIN_DMI_N
RH87 10K_0402_5%~D MMICLK_REQ# V10 BE18 CLK_BUF_DMI
<33> MMICLK_REQ# PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
SIO_14M CLK_BUF_DOT96# 1 2
10P_0402_50V8J~D
2 1 PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
<34> CLK_PCIE_MINI3# CLKOUT_PCIE3N CLKIN_GND1_N
PP (Mini Card 3)---> @ RH88 2 1 0_0402_5%~D PCIE_MINI3 Y36 BG30 CLK_BUF_BCLK 1 RH77 10K_0402_5%~D
B <34> CLK_PCIE_MINI3 CLKOUT_PCIE3P CLKIN_GND1_P B
+3.3V_ALW_PCH @ RH90 2 1 0_0402_5%~D
CE19
RH152 10K_0402_5%~D MINI3CLK_REQ# A8 CLK_BUF_CKSSCD# 1 2
<34> MINI3CLK_REQ# PCIECLKRQ3# / GPIO25 CLK_BUF_DOT96# CLK_BUF_CKSSCD
G24 RH78 1 2 10K_0402_5%~D
CLKIN_DOT_96N CLK_BUF_DOT96 2 RH79 10K_0402_5%~D
E24
PCIE_EXP# CLKIN_DOT_96P
<35> CLK_PCIE_EXP# 2 1 Y43
PCIE_EXP CLKOUT_PCIE4N CLK_PCH_14M
Express card---> <35> CLK_PCIE_EXP
@ RH92 2 1 0_0402_5%~D Y45
CLKOUT_PCIE4P 1 2
@ RH93 2 1 0_0402_5%~D AK7 CLK_BUF_CKSSCD# RH183 10K_0402_5%~D
+3.3V_ALW_PCH CLKIN_SATA_N
RH94 10K_0402_5%~D EXPCLK_REQ# L12 AK5 CLK_BUF_CKSSCD
<35> EXPCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
RF review in 1130
2 1 PCIE_MINI2# V45 K45 CLK_PCH_14M
<34> CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
@ RH95 2 1 0_0402_5%~D PCIE_MINI2 V46 CLOCK TERMINATION for FCIM and need close to PCH
<34> CLK_PCIE_MINI2 CLKOUT_PCIE5P
WLAN (Mini Card 2)---> +3.3V_ALW_PCH @ RH96 2 1 0_0402_5%~D
RH97 10K_0402_5%~D MINI2CLK_REQ# L14 H45 CLK_PCI_LOOPBACK
<34> MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK <17>
AB42 V47 XTAL25_IN 2 1
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT @ RH309 0_0402_5%~D
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT
1
+3.3V_ALW_PCH 1 2 PEG_B_CLKRQ# E6 RH99
RH98 10K_0402_5%~D PEG_B_CLKRQ# / GPIO56 1M_0402_5%~D
Y47 XCLK_RCOMP 1 2 YH2
XCLK_RCOMP +1.05V_RUN
V40 RH100 90.9_0402_1%~D 25MHZ_10PF_Q22FA2380049900~D
2
CLKOUT_PCIE6N
V42 3 OUT
CLKOUT_PCIE6P IN 1
10P_0402_50V8J~D
10P_0402_50V8J~D
2 1 PCIECLKRQ6# T13 4 2
+3.3V_ALW_PCH PCIECLKRQ6# / GPIO45 GND GND
RH110 10K_0402_5%~D 2 2
V38 K43 CLK_48M RH322 2 1 22_0402_5%~D
CH19
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_SMART_48M <35>
CH18
V37
FLEX CLOCKS
CLKOUT_PCIE7P SIO_14M RH313
CLKOUTFLEX1 / GPIO65
F47 2 1 22_0402_5%~D CLK_SIO_14M <39>
PCIECLKRQ7# 1 1
+3.3V_ALW_PCH 2 1 K12
PCIECLKRQ7# / GPIO46
RH104 10K_0402_5%~D H47 PCI_TPM_TCM 5@ RH311 2 1 10_0402_1%~D
A CLK_BCLK_ITP# AK14 CLKOUTFLEX2 / GPIO66 CLK_PCI_TPM_TCM <32> A
2 1 RH314 2 1 10_0402_1%~D
<7> CLK_CPU_ITP# CLK_BCLK_ITP AK13 CLKOUT_ITPXDP_N PCLK_80H <34>
@ RH2802 1 0_0402_5%~D K49
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 JETWAY_14M @
@ RH281 0_0402_5%~D RH315 2 1 22_0402_5%~D JETWAY_CLK14M <32>
BD82HM77 SLJ8C C1_BGA989~D
DELL CONFIDENTIAL/PROPRIETARY
PCIE REQ power rail:
Compal Electronics, Inc.
suspend: 0 3 4 5 6 7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
core: 1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (2/8)
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 15 of 61
Rev
1.0
5 4 3 2 1
+3.3V_RUN
+3.3V_ALW_PCH Follow E4
2.2K_0402_5%~D
2.2K_0402_5%~D
1
1
RH316
RH317
RH357 1 2 0_0402_5%~D 1 2 PCH_CRT_BLU
RH131 150_0402_1%~D
1 2 SUS_STAT#/LPCPD# +3.3V_RUN 1 2 PCH_CRT_GRN
@ RH318 10K_0402_5%~D @ CH99 RH132 150_0402_1%~D
2
1 2 1 2 PCH_CRT_RED
1 2 ME_SUS_PWR_ACK RH133 150_0402_1%~D
5
RH144 10K_0402_5%~D @ UC3 0.1U_0402_25V6K~D 1 2 ENVDD_PCH PCH_CRT_DDC_CLK
PCH_CRT_DDC_CLK <23>
1 RH134 100K_0402_5%~D
P
<7,14> XDP_DBRESET# B
1 2 PCH_PCIE_WAKE# 4 SYS_RESET#
D RH142 10K_0402_5%~D O D
2 1 ME_RESET# 2 PCH_CRT_DDC_DAT
PCH_CRT_DDC_DAT <23>
A
G
@ RH141 8.2K_0402_5%~D
1 2 SIO_SLP_LAN# 74AHC1G09GW_TSSOP5~D +3.3V_ALW2
3
@ RH319 10K_0402_5%~D
1 2
1 2 PCH_RI# CH108 0.1U_0402_25V6K~D
RH140 10K_0402_5%~D UH5
5
DSWODVREN - On Die DSW VR Enable TC7SH08FU_SSOP5~D
PCH_DPWROK 1 2 PCH_RSMRST#_R SIO_SLP_A# 1
P
@ RH113 0_0402_5%~D Enabled (DEFAULT) B PM_APWROK_R
4
PM_APWROK O
<40> PM_APWROK 2
A
G
HIGH: RH127 STUFFED,
+3.3V_RUN RH129 UNSTUFFED
3
1 2 CLKRUN# Disabled
RH137 8.2K_0402_5%~D +3.3V_RUN
1 2 ME_RESET# LOW: RH129 STUFFED, 1 2
@ RH138 8.2K_0402_5%~D RH127 UNSTUFFED @ RH118 0_0402_5%~D PCH_SDVO_CTRLCLK 2 1
ME_SUS_PWR_ACK_R 1 2 SUSACK#_R RH351 2.2K_0402_5%~D
@ RH323 0_0402_5%~D PCH_SDVO_CTRLDATA 2 1
RH352 2.2K_0402_5%~D
UH4C
Intel request DDPB can not support eDP
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 UH4D
<6> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1 PANEL_BKEN_PCH J47 AP43
<6> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <6> <24> PANEL_BKEN_PCH L_BKLTEN SDVO_TVCLKINN
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 ENVDD_PCH M45 AP45
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <6> <24,39> ENVDD_PCH L_VDD_EN SDVO_TVCLKINP
DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
<6> DMI_CTX_PRX_N3 DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4 BIA_PWM_PCH P45 AM42
FDI_RXN4 FDI_CTX_PRX_N4 <6> <24> BIA_PWM_PCH L_BKLTCTL SDVO_STALLN
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 AM40
<6> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6> SDVO_STALLP
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 LDDC_CLK_PCH T40
C <6> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <6> <24> LDDC_CLK_PCH L_DDC_CLK C
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 LDDC_DATA_PCH K47 AP39
<6> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <6> <24> LDDC_DATA_PCH L_DDC_DATA SDVO_INTN
DMI_CTX_PRX_P3 BJ20 AP40
<6> DMI_CTX_PRX_P3 DMI3RXP SDVO_INTP
BG14 FDI_CTX_PRX_P0 T45
FDI_RXP0 FDI_CTX_PRX_P0 <6> L_CTRL_CLK
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 P39
<6> DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 FDI_CTX_PRX_P1 <6> L_CTRL_DATA
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 1 2 LVD_IBG AF37 P38 PCH_SDVO_CTRLCLK PCH_SDVO_CTRLCLK <25>
<6> DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P3 <6> LVD_IBG SDVO_CTRLCLK
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 RH344 2.37K_0402_1%~D AF36 M39 PCH_SDVO_CTRLDATA
<6> DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 <6> LVD_VBG SDVO_CTRLDATA PCH_SDVO_CTRLDATA <25>
<6>Minimum speacing of 20mils for LVD_IBG
BG12 FDI_CTX_PRX_P5
DMI
DMI_CRX_PTX_P0 AY24
FDI FDI_RXP5
BJ10 FDI_CTX_PRX_P6
FDI_CTX_PRX_P5
AE48
<6> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6> LVD_VREFH
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 AE47 AT49
<6> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6> LVD_VREFL DDPB_AUXN
DMI_CRX_PTX_P2 AY18 AT47
<6> DMI_CRX_PTX_P2 DMI2TXP DDPB_AUXP
DMI_CRX_PTX_P3 AU18 AT40
<6> DMI_CRX_PTX_P3 DMI3TXP DDPB_HPD HDMIB_PCH_HPD <25>
AW16 FDI_INT LCD_ACLK-_PCH AK39
+1.05V_RUN FDI_INT FDI_INT <6> <24> LCD_ACLK-_PCH LVDSA_CLK#
LCD_ACLK+_PCH AK40 AV42
LVDS
<24> LCD_ACLK+_PCH LVDSA_CLK DDPB_0N TMDSB_PCH_N2 <25>
BJ24 AV12 FDI_FSYNC0 AV40
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6> DDPB_0P TMDSB_PCH_P2 <25>
LCD_A0-_PCH AN48 AV45
<24> LCD_A0-_PCH LVDSA_DATA#0 DDPB_1N TMDSB_PCH_N1 <25>
1 2 DMI_COMP_R BG25 BC10 FDI_FSYNC1 LCD_A1-_PCH AM47 AV46
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6> <24> LCD_A1-_PCH LVDSA_DATA#1 DDPB_1P TMDSB_PCH_P1 <25>
RH111 49.9_0402_1%~D LCD_A2-_PCH AK47 AU48
Digital Display Interface
<24> LCD_A2-_PCH LVDSA_DATA#2 DDPB_2N TMDSB_PCH_N0 <25>
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AJ48 AU47
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6> LVDSA_DATA#3 DDPB_2P TMDSB_PCH_P0 <25>
RH112 750_0402_1%~D AV47
FDI_LSYNC1 LCD_A0+_PCH DDPB_3N TMDSB_PCH_CLK# <25>
BB10 FDI_LSYNC1 <6> <24> LCD_A0+_PCH AN47 AV49 TMDSB_PCH_CLK <25>
FDI_LSYNC1 LCD_A1+_PCH LVDSA_DATA0 DDPB_3P
<24> LCD_A1+_PCH AM49
+RTC_CELL LCD_A2+_PCH LVDSA_DATA1
<24> LCD_A2+_PCH AK49
LVDSA_DATA2
AJ47 P46 PCH_DDPC_CTRLCLK <26>
RH127 1 LVDSA_DATA3 DDPC_CTRLCLK
A18 DSWODVREN 2 330K_0402_1%~D P42 PCH_DDPC_CTRLDATA <26>
DSWVRMEN DDPC_CTRLDATA
@ RH129 1 2 330K_0402_1%~D LCD_BCLK-_PCH AF40
<24> LCD_BCLK-_PCH LVDSB_CLK#
System Power Management
1 2 SUSACK#_R C12 E22 PCH_DPWROK LCD_BCLK+_PCH AF39 AP47
<39> SUSACK# SUSACK# DPWROK PCH_DPWROK <39> <24> LCD_BCLK+_PCH LVDSB_CLK DDPC_AUXN DPC_PCH_DOCK_AUX# <26>
@ RH114 0_0402_5%~D AP49
LCD_B0-_PCH DDPC_AUXP DPC_PCH_DOCK_AUX <26>
<24> LCD_B0-_PCH AH45 AT38 DPC_PCH_DOCK_HPD <38>
SYS_RESET# PCH_PCIE_WAKE# LCD_B1-_PCH LVDSB_DATA#0 DDPC_HPD
K3 B9 PCH_PCIE_WAKE# <40> <24> LCD_B1-_PCH AH47
SYS_RESET# WAKE# LCD_B2-_PCH LVDSB_DATA#1
<24> LCD_B2-_PCH AF49 AY47 DPC_PCH_LANE_N0 <38>
B LVDSB_DATA#2 DDPC_0N B
AF45 AY49 DPC_PCH_LANE_P0 <38>
SYS_PWROK_R CLKRUN# LVDSB_DATA#3 DDPC_0P
<7,39> SYS_PWROK 1 2 P12 N3 CLKRUN# <32,39,40> AY43 DPC_PCH_LANE_N1 <38>
@ RH116 SYS_PWROK CLKRUN# / GPIO32 DDPC_1N
1 2 0_0402_5%~D <24> LCD_B0+_PCH
LCD_B0+_PCH AH43 AY45 DPC_PCH_LANE_P1 <38>
RH321 @ 0_0402_5%~D LCD_B1+_PCH LVDSB_DATA0 DDPC_1P
<24> LCD_B1+_PCH AH49 BA47 DPC_PCH_LANE_N2 <38>
PCH_PWROK SUS_STAT#/LPCPD# T56 PAD~D @ LCD_B2+_PCH LVDSB_DATA1 DDPC_2N
<40> RESET_OUT# 1 2 L22 G8 <24> LCD_B2+_PCH AF47 BA48 DPC_PCH_LANE_P2 <38>
@ RH117 PWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
1 2 0_0402_5%~D AF43 BB47 DPC_PCH_LANE_N3 <38>
RH119 @ 0_0402_5%~D LVDSB_DATA3 DDPC_3N
BB49 DPC_PCH_LANE_P3 <38>
PM_APWROK_R SUSCLK T57 PAD~D @ DDPC_3P
L10 N14
APWROK SUSCLK / GPIO62
T58 PAD~D @ PCH_CRT_BLU N48 M43 PCH_DDPD_CTRLCLK <26>
<23> PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
1 2 PM_DRAM_PWRGD_R B13 D10 SIO_SLP_S5# PCH_CRT_GRN P49 M36
<7> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# <40,42> <23> PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA PCH_DDPD_CTRLDATA <26>
@ RH320 0_0402_5%~D PCH_CRT_RED T49
<23> PCH_CRT_RED CRT_RED
T59 PAD~D @
1 2 PCH_RSMRST#_R C21 H4 SIO_SLP_S4# AT45
<14,41> PCH_RSMRST#_Q RSMRST# SLP_S4# SIO_SLP_S4# <39,42,46> DDPD_AUXN DPD_PCH_DOCK_AUX# <26>
@ RH120 0_0402_5%~D PCH_CRT_DDC_CLK T39 AT43
CRT
PCH_CRT_DDC_DAT CRT_DDC_CLK DDPD_AUXP DPD_PCH_DOCK_AUX <26>
M40 BH41 DPD_PCH_DOCK_HPD <38>
ME_SUS_PWR_ACK_R SIO_SLP_S3# CRT_DDC_DATA DDPD_HPD
<40> ME_SUS_PWR_ACK 1 2 K16 F4 SIO_SLP_S3# <11,27,35,39,42,47,48,49>
@ RH121 0_0402_5%~D SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# RH123 20_0402_1%~D BB43 DPD_PCH_LANE_N0 <38>
DDPD_0N
<7,14> SIO_PWRBTN#_R <23> PCH_CRT_HSYNC 1 2 HSYNC M47 BB45 DPD_PCH_LANE_P0 <38>
SIO_PWRBTN#_R SIO_SLP_A# CRT_HSYNC DDPD_0P
<40> SIO_PWRBTN# 1 2 E20 G10 SIO_SLP_A# <39,42,48> <23> PCH_CRT_VSYNC 1 2 VSYNC M49 BF44 DPD_PCH_LANE_N1 <38>
@ RH122 0_0402_5%~D PWRBTN# SLP_A# RH124 20_0402_1%~D CRT_VSYNC DDPD_1N
BE44 DPD_PCH_LANE_P1 <38>
T62 PAD~D @ DDPD_1P
BF42 DPD_PCH_LANE_N2 <38>
AC_PRESENT SIO_SLP_SUS# CRT_IREF DDPD_2N
<40> AC_PRESENT H20 G16 SIO_SLP_SUS# <39> T43 BE42 DPD_PCH_LANE_P2 <38>
ACPRESENT / GPIO31 SLP_SUS# DAC_IREF DDPD_2P
T42 BJ42 DPD_PCH_LANE_N3 <38>
T63 PAD~D @ CRT_IRTN DDPD_3N
BG42 DPD_PCH_LANE_P3 <38>
DDPD_3P
1
+3.3V_ALW_PCH 1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <7>
RH139 8.2K_0402_5%~D BD82HM77 SLJ8C C1_BGA989~D
RH126
PCH_RI# A10 K14 SIO_SLP_LAN# 1K_0402_0.5%~D
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# <30,39>
2
BD82HM77 SLJ8C C1_BGA989~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (3/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7902P
Date: Wednesday, March 07, 2012 Sheet 16 of 61
5 4
WWW.AliSaler.Com 3 2 1
5 4 3 2 1
+3.3V_RUN
1 2 PCI_PIRQA#
RH324 8.2K_0402_5%~D
UH4E
D PCI_PIRQB# D
1 2 RSVD1
AY7
RH325 8.2K_0402_5%~D AV7
PAD~D T72 @ RSVD2
BG26 AU3
PCI_PIRQC# PAD~D T64 @ TP1 RSVD3
1 2 BJ26 BG4
RH326 8.2K_0402_5%~D PAD~D T73 @ TP2 RSVD4
BH25
PAD~D T65 @ TP3
BJ16 AT10
PCI_PIRQD# PAD~D T74 @ TP4 RSVD5
1 2 BG16 BC8
RH329 8.2K_0402_5%~D PAD~D T66 @ TP5 RSVD6
AH38
PAD~D T67 @ TP6
AH37 AU2
PCI_REQ1# PAD~D T75 @ TP7 RSVD7
1 2 AK43 AT4
RH327 10K_0402_5%~D PAD~D T76 @ TP8 RSVD8
AK45 AT3
PAD~D T77 @ TP9 RSVD9
C18 TP10 RSVD10 AT1
1 2 LCD_CBL_DET# PAD~D T68 @ N30 AY3
RH330 10K_0402_5%~D PAD~D T69 @ TP11 RSVD11
H3 TP12 RSVD12 AT5
PAD~D T78 @ AH12 AV3
CAM_MIC_CBL_DET# PAD~D T79 @ TP13 RSVD13
1 2 AM4 TP14 RSVD14 AV1
RH331 10K_0402_5%~D PAD~D T80 @ AM5 BB1
PAD~D T70 @ TP15 RSVD15
Y13 TP16 RSVD16 BA3
1 2 BT_DET# PAD~D T81 @ K24 BB5
RH328 10K_0402_5%~D PAD~D T71 @ TP17 RSVD17
L24 TP18 RSVD18 BB3
PAD~D T82 @ AB46 BB7
PCH_GPIO3 PAD~D T83 @ TP19 RSVD19
1 2 AB45 TP20 RSVD20 BE8
RH332 10K_0402_5%~D BD4
RSVD
RSVD21
RSVD22 BF6
1 2 PCIE_MCARD2_DET#
RH361 10K_0402_5%~D PAD~D T84 @ B21 AV5
PAD~D T85 @ TP21 RSVD23
M20 TP22 RSVD24 AV10
PAD~D T86 @ AY16
PAD~D T87 @ TP23
BG46 TP24 RSVD25 AT8
RSVD26 AY5
RSVD27 BA2
C C
BE28 USB3Rn1
<36> USB3RN2 BC30 USB3Rn2 RSVD28 AT12
<36> USB3RN3 BE32 USB3Rn3 RSVD29 BF3
<38> USB3RN4 BJ32 USB3Rn4
BC28 USB3Rp1
<36> USB3RP2 BE30 USB3Rp2
BF32
USB30
<36> USB3RP3 USB3Rp3
BG32 C24 USBP0-
<38> USB3RP4 USB3Rp4 USBP0N USBP0- <37>
PCI_GNT3# AV26
USB3Tn1 USBP0P
A24 USBP0+
USBP0+ <37>
----->Back Right--JIO1
BB26 C25 USBP1-
<36> USB3TN2 USB3Tn2 USBP1N USBP1- <36>
<36> USB3TN3 AU28
USB3Tn3 USBP1P
B25 USBP1+
USBP1+ <36> ----->Left Side
1
AY30 C26 USBP2-
<38> USB3TN4 USB3Tn4 USBP2N USBP2- <36>
@ RH333 AU26
USB3TP1 USBP2P
A26 USBP2+
USBP2+ <36>
----->Left side JESA1
1K_0402_1%~D AY26 K28 USBP3-
<36> USB3TP2 USB3Tp2 USBP3N USBP3- <38>
<36> USB3TP3 AV28
USB3Tp3 USBP3P
H28 USBP3+
USBP3+ <38>
----->MLK DOCK
AW30 E28 USBP4-
<38> USB3TP4 USBP4- <34>
2
USB3Tp4 USBP4N USBP4+ ----->WLAN/WIMAX
D28 USBP4+ <34>
USBP4P USBP5-
C28 USBP5- <34>
USBP5N USBP5+ ----->WWAN/UWB
A28 USBP5+ <34>
USBP5P USBP6-
C29 USBP6- <34>
USBP6N USBP6+
PCI_PIRQA# K40
USBP6P
B29
N28 USBP7-
USBP6+ <34> ----->Flash
PIRQA# USBP7N USBP7- <38>
PCI_PIRQB# USBP7+
A16 swap override Strap/Top-Block PCI_PIRQC#
K38
H38
PIRQB# USBP7P
M28
L30 USBP8- USBP7+ <38> ----->DOCK
PCI
PCI_PIRQD# PIRQC# USBP8N USBP8+
Swap Override jumper
G38
PIRQD# USBP8P
K30
G30 USBP9- ----->Non used
USBP9N USBP9- <37>
PCI_REQ1# C46
REQ1# / GPIO50 USBP9P
E30 USBP9+
USBP9+ <37>
----->Right side--JAUD1
C44 C30 USBP10-
USB
<34> PCIE_MCARD2_DET# REQ2# / GPIO52 USBP10N USBP10- <35>
Low = A16 swap <41> BT_DET#
BT_DET# E40
REQ3# / GPIO54 USBP10P
A30 USBP10+
USBP10+ <35>
----->Express Card +3.3V_ALW_PCH
PCI_GNT#3 L32 USBP11-
USBP11N USBP11- <41>
High = Default BBS_BIT1 D47
GNT1# / GPIO51 USBP11P
K32 USBP11+
USBP11+ <41> ----->Blue Tooth RPH1
E42 G32 USBP12- USB_OC2# 4 5
GNT2# / GPIO53 USBP12N USBP12- <24>
B PCI_GNT3# F46
GNT3# / GPIO55 USBP12P
E32 USBP12+
USBP12+ <24>
----->Camera USB_OC1#_R 3 6 B
C32 USBP13- USB_OC6# 2 7
USBP13N USBP13- <32>
USBP13P
A32 USBP13+
USBP13+ <32>
----->BIO USB_OC4#_R 1 8
LCD_CBL_DET# G42
<24> LCD_CBL_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 10K_1206_8P4R_5%~D
CAM_MIC_CBL_DET# PIRQF# / GPIO3 USBRBIAS RPH2
<24> CAM_MIC_CBL_DET# C42 C33 1 2
FFS_PCH_INT PIRQG# / GPIO4 USBRBIAS# RH151 USB_OC5#
<27> HDD_FALL_INT 1 2 D44 4 5
@ RH334 0_0402_5%~D PIRQH# / GPIO5 22.6_0402_1%~D USB_OC3# 3 6
B33 Route single-end 50-ohms and max 500-mils length. SIO_EXT_SMI# 2 7
PAD~D T104 @ USBRBIAS USB_OC0#_R
<33> PLTRST_MMI# 1 2 K10 1 8
<7> PLTRST_XDP#
@ RH3361 2 0_0402_5%~D
PME# Minimum spacing to other signals: 15 mils
RH3371 2 0_0402_5%~D PCH_PLTRST# C6 A14 USB_OC0#_R 1 2 10K_1206_8P4R_5%~D
<30> PLTRST_LAN# PLTRST# OC0# / GPIO59 USB_OC1#_R USB_OC0# <36,37>
@ RH338 0_0402_5%~D K20 @ RH3391 2 0_0402_5%~D
OC1# / GPIO40 USB_OC2# USB_OC1# <36>
B17 @ RH341 0_0402_5%~D
OC2# / GPIO41 USB_OC2# <14>
2 1 PCI_5048 H49 C16 USB_OC3#
<39> CLK_PCI_5048 CLKOUT_PCI0 OC3# / GPIO42 USB_OC3# <14>
RH160 2 1 22_0402_5%~D PCI_MEC H43 L16 USB_OC4#_R 1 2
<40> CLK_PCI_MEC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <37>
RH102 2 1 22_0402_5%~D PCI_DOCK J48 A16 USB_OC5# @ RH356 0_0402_5%~D
<38> CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# USB_OC5# <14>
RH103 22_0402_5%~D K42 D14
PCI_LOOPBACKOUT CLKOUT_PCI3 OC6# / GPIO10 SIO_EXT_SMI# USB_OC6# <14>
<15> CLK_PCI_LOOPBACK 2 1 H40 C14 SIO_EXT_SMI# <14,40>
CLKOUT_PCI4 OC7# / GPIO14
Reserve for ESD in 6/22 RH105 22_0402_5%~D
USB_OC0#_R <14>
PCH_PLTRST# BD82HM77 SLJ8C C1_BGA989~D
USB_OC1#_R <14>
USB_OC4#_R <14>
1
CE10 +3.3V_RUN CH102
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
2 @ 1 2
Boot BIOS Strap
5
A A
UH3 SATA_SLPD
PCH_PLTRST# 1 BBS_BIT1 (BBS_BIT0) Boot BIOS Location
P
<7,14> PCH_PLTRST# B PCH_PLTRST#_EC BBS_BIT1
O 4 PCH_PLTRST#_EC <32,34,35,39,40>
2 A
G
0 0 LPC
DELL CONFIDENTIAL/PROPRIETARY
1
TC7SH08FU_SSOP5~D
3
@ RH342
0 1 Reserved (NAND) 1K_0402_1%~D Compal Electronics, Inc.
Title
2
1 0 PCI PCH (4/8)
5 4
WWW.AliSaler.Com
* 1 1 SPI
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 17 of 61
Rev
1.0
5 4 3 2 1
+3.3V_ALW_PCH +3.3V_RUN
2
RH53 CONTACTLESS_DET# 2 1
4.7K_0402_5%~D RH256 10K_0402_5%~D
D D
1
SLP_ME_CSW_DEV# UH4F
<14> SIO_EXT_SCI#_R
1
SIO_EXT_SCI# 1 2 T7 C40 CONTACTLESS_DET#
<40> SIO_EXT_SCI# BMBUSY# / GPIO0 TACH4 / GPIO68
RH353 @ RH259 0_0402_5%~D
1K_0402_1%~D PCH_GPIO1 A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69
@
IO_LOOP# H36 C41 PCIE_MCARD3_DET# PCH_GPIO69 1 2
PCIE_MCARD3_DET# <34>
2
TACH2 / GPIO6 TACH6 / GPIO70 RH260 1.5K_0402_1%~D
LED_B_DET# E38 A40
TACH3 / GPIO7 TACH7 / GPIO71 USB_MCARD2_DET# <34>
<39> SIO_EXT_WAKE# C10 GPIO8
Note: PCH has internal pull up 20k ohm on vPro only--- PM_LANPHY_ENABLE C4 LAN_PHY_PWR_CTRL / GPIO12
E3_PAID_TS_DET# (GPIO27) <14> PCH_GPIO15
PCH_GPIO15 G2 P4 SIO_A20GATE
SIO_A20GATE <40>
GPIO15 A20GATE
PECI AU16
PCH_GPIO16 U2
<14> PCH_GPIO16 SATA4GP / GPIO16 SIO_RCIN#
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE P5 SIO_RCIN# <40>
RCIN# +3.3V_RUN
PCH_GPIO17 D40 AY11 H_CPUPWRGD +1.05V_RUN_VTT
GPIO
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <7>
ENABLED - HIGH DEFAULT
CPU/MISC
DISABLED - LOW MEDIA_DET# T5 AY10 PCH_THRMTRIP#_R 2 1 SIO_A20GATE 2 1
<37> MEDIA_DET# SCLOCK / GPIO22 THRMTRIP# RH262 56_0402_5%~D RH158 10K_0402_5%~D
E8 T14 INIT3_3V# PAD~D T106 1 SIO_RCIN# 2 1
<34> PCIE_MCARD1_DET# GPIO24 INIT3_3V# @ RH203 10K_0402_5%~D
PCH_GPIO27 E16 AY1 DF_TVS CH97
+3.3V_ALW_PCH GPIO27 DF_TVS 0.1U_0402_25V6K~D
SLP_ME_CSW_DEV# 2 SIO_EXT_SCI#
<14,39> SLP_ME_CSW_DEV# P8 GPIO28
1 2
AH8 RH263 10K_0402_5%~D
SIO_EXT_WAKE# PCH_GPIO34 TS_VSS1 PCH_GPIO1
2 1 K1 1 2
C RH177 10K_0402_5%~D STP_PCI# / GPIO34 RH164 100K_0402_5%~D C
TS_VSS2 AK11
1 2 PCH_GPIO15 USB_MCARD1_DET# K4
<14,34> USB_MCARD1_DET# GPIO35
RH354 1K_0402_1%~D AH10
PCH_GPIO36 TS_VSS3
<14> PCH_GPIO36 V8 SATA2GP / GPIO36
2 1 PM_LANPHY_ENABLE AK10
RH179 10K_0402_5%~D PCH_GPIO37 TS_VSS4
<14> PCH_GPIO37 M5 SATA3GP / GPIO37
TPM_ID0 N2 P37 NC_1 PAD~D T108 @
PCH_GPIO27 SLOAD / GPIO38 NC_1
2 1
RH180 10K_0402_5%~D TPM_ID1 M3
SDATAOUT0 / GPIO39
FFS_INT2 V13 BG2 VSS_NCTF_15
<27> FFS_INT2 SDATAOUT1 / GPIO48 VSS_NCTF_15
TEMP_ALERT# V3 BG48 VSS_NCTF_16
<14,39> TEMP_ALERT# SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
KB_DET# D6 BH3 VSS_NCTF_17 Layout note:
<41> KB_DET# GPIO57 VSS_NCTF_17
BH47 VSS_NCTF_18 Trace wide 10mil & length 30mil
VSS_NCTF_18
VSS_NCTF_1 VSS_NCTF_19
All NCTF pins should have thick
A4 BJ4
VSS_NCTF_1 VSS_NCTF_19 traces at 45°from the pad.
VSS_NCTF_2 A44 BJ44 VSS_NCTF_20
VSS_NCTF_2 VSS_NCTF_20
VSS_NCTF_3 A45 BJ45 VSS_NCTF_21
VSS_NCTF_3 VSS_NCTF_21
2 1 PCH_GPIO36
RH174 10K_0402_5%~D VSS_NCTF_4 A46 BJ46 VSS_NCTF_22
NCTF
VSS_NCTF_4 VSS_NCTF_22
2 1 PCH_GPIO37
RH172 10K_0402_5%~D VSS_NCTF_5 A5 BJ5 VSS_NCTF_23
VSS_NCTF_5 VSS_NCTF_23
2 1 PCH_GPIO17
@ RH273 1K_0402_1%~D VSS_NCTF_6 A6 BJ6 VSS_NCTF_24
VSS_NCTF_6 VSS_NCTF_24
2 1 PCH_GPIO16
@ RH265 10K_0402_5%~D VSS_NCTF_7 B3 C2 VSS_NCTF_25
B VSS_NCTF_7 VSS_NCTF_25 B
VSS_NCTF_8 B47 C48 VSS_NCTF_26
VSS_NCTF_8 VSS_NCTF_26
Layout note: VSS_NCTF_9 BD1 D1 VSS_NCTF_27
VSS_NCTF_9 VSS_NCTF_27
Trace wide 10mil & length 30mil VSS_NCTF_10 BD49 D49 VSS_NCTF_28 PLACE RH150 CLOSE TO THE BRANCHING POINT
VSS_NCTF_10 VSS_NCTF_28
All NCTF pins should have thick VSS_NCTF_11 VSS_NCTF_29
( TO CPU and NVRAM CONNECTOR)
BE1 E1
traces at 45°from the pad. VSS_NCTF_11 VSS_NCTF_29
VSS_NCTF_12 BE49 E49 VSS_NCTF_30
VSS_NCTF_12 VSS_NCTF_30 +VCCDFTERM
VSS_NCTF_13 BF1 F1 VSS_NCTF_31
VSS_NCTF_13 VSS_NCTF_31
RH149 need to close to CPU
VSS_NCTF_14 BF49 F49 VSS_NCTF_32
VSS_NCTF_14 VSS_NCTF_32
1
+3.3V_ALW_PCH
RH149
2 1 KB_DET# BD82HM77 SLJ8C C1_BGA989~D 2.2K_0402_5%~D
RH170 10K_0402_5%~D
2
1 2 DF_TVS_R 1 2 DF_TVS
<7> H_SNB_IVB#
@RH150
@ RH150 0_0402_5%~D RH358 1K_0402_1%~D
+3.3V_RUN
2 1 PCH_GPIO36
@ RH171 10K_0402_5%~D
2 1 PCH_GPIO37 +3.3V_RUN +3.3V_RUN
@ RH173 1K_0402_1%~D
1 2 PCH_GPIO16 DMI & FDI Termination Voltage
RH272 10K_0402_5%~D
2
2 1 TEMP_ALERT#
RH266 10K_0402_5%~D 1@ RH267 3@ RH268 Set to Vss when LOW
2 1 MEDIA_DET# 10K_0402_5%~D 20K_0402_5%~D TPM_ID0 TPM_ID1 DF_TVS
A A
RH181 10K_0402_5%~D Set to Vcc when HIGH
2 1 LED_B_DET# China TPM 0 0
1
RH178 10K_0402_5%~D
1 2 PCH_GPIO17 TPM_ID0 TPM_ID1 No TPM, No China TPM 0 1
RH269 8.2K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2
1 2 IO_LOOP# TBD
RH163 10K_0402_5%~D 2@ RH270 4@ RH271
2 1 PCH_GPIO34
10K_0402_5%~D 2.2K_0402_5%~D TPM 1 1 Compal Electronics, Inc.
RH182 10K_0402_5%~D Title
1
PCH (5/8)
Intel review feedback in 0701
5 4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 18 of 61
Rev
1.0
5 4 3 2 1
+3.3V_RUN
LH1
PCH Power Rail Table
+1.05V_RUN UH4G POWER +VCCADAC 2 1 S0 Iccmax
1UH_GLFR1608T1R0M-LR_20%~D Voltage Rail Voltage Current (A)
0.01U_0402_16V7K~D
0.1U_0402_10V7K~D
10U_0603_6.3V6M~D
AA23 VCCCORE[1] VCCADAC U48 1 1 1
AC23 VCCCORE[2]
V_PROC_IO 1.05 0.001
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
CH34
CH35
CH36
1 1 1 1 AD21 VCCCORE[3]
CRT
AD23 U47
VCCCORE[4] VSSADAC 2 2 2
CH30
CH32
CH33
CH31
AF21
VCCCORE[5]
V5REF 5 0.001
VCC CORE
AF23 +3.3V_RUN
D 2 2 2 2 VCCCORE[6] D
AG21
VCCCORE[7]
AG23
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 AK36
VCCCORE[9] VCCALVDS
AG26
VCCCORE[10] +1.8V_RUN
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.288
AG29 LH8
VCCCORE[12] 100NH_HK1608R10J-T_5%_0603~D
AJ23
VCCCORE[13] +1.8V_RUN_LVDS
AJ26 AM37 2 1 VccADAC3 3.3 0.063
LVDS
VCCCORE[14] VCCTX_LVDS[1]
22U_0805_6.3V6M~D
AJ27 1 1 1 0.1uH inductor, 200mA
VCCCORE[15]
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
CH105
AJ29 AM38
VCCCORE[16] VCCTX_LVDS[2]
CH103
CH104
AJ31 CPN: SHI0110BJ0L VccADPLLA 1.05 0.08
+1.05V_RUN VCCCORE[17]
VCCTX_LVDS[3] AP36
2 2 2
VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.08
AN19 VCCIO[28]
+1.05V_RUN
VccCore 1.05 1.7
1 2 +VCCAPLLEXP BJ22
@ RH247 VCCAPLLEXP
1UH_LB2012T1R0M_20%~D
10U_0603_6.3V6M~D
1 VCC3_3[6] V33 +3.3V_RUN VccDMI 1.05 0.047
@ AN16
HVCMOS
VCCIO[15]
1
CH40
AN17 VCCIO[16]
VccIO 1.05 3.711
2 V34 CH43
VCC3_3[7]
0.1U_0402_10V7K~D
AN21 2 VccASW 1.05 0.903
VCCIO[17]
AN26 +1.05V_+1.5V_1.8V_RUN
VCCIO[18]
VccSPI 3.3 0.01
AN27 VCCIO[19] VCCVRM[3] AT16
+1.05V_RUN
AP21 VCCIO[20]
VccDSW3_3 3.3 0.001
C C
AP23 VCCIO[21] VCCDMI[1] AT20 +1.05V_RUN_VTT
VCCDFTERM 1.8 0.002
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1 1 1 1 1 AP24 1 2 CH49
DMI
VCCIO[22] 1U_0402_6.3V6K~D
VCCIO
CH44
CH45
CH46
CH47
CH48
AP26 AB36 +1.05V_RUN_VCCCLKDMI 2 1 VccRTC 3.3 6uA
VCCIO[23] VCCCLKDMI +1.05V_RUN
10U_0603_6.3V6M~D
1 1 @ @ RH205 0_0603_5%~D
2 2 2 2 2
AT24
VCCIO[24]
CH106
CH50 VccSus3_3 3.3 0.126
1U_0402_6.3V6K~D
AN33 2 2 INTEL feedback 0302
VCCIO[25]
VccSusHDA 3.3 0.01
AN34 AG16
+3.3V_RUN VCCIO[26] VCCDFTERM[1] +VCCDFTERM
VccVRM 1.8 / 1.5 0.167
BH29 AG17 2 1 +3.3V_RUN
VCC3_3[3] VCCDFTERM[2] @ RH276 0_0805_5%~D
DFT / SPI
0.1U_0402_10V7K~D
1 @PJP66
@ PJP66 VccClkDMI 1.05 0.07
+1.05V_+1.5V_1.8V_RUN AJ16 1 1 2 +1.8V_RUN
VCCDFTERM[3]
CH51
AP16
VCCVRM[2]
CH52 PAD-OPEN1x1m VccSSC 1.05 0.095
2 AJ17 0.1U_0402_10V7K~D short
VCCDFTERM[4] 2
+VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL
+1.05V_RUN AP17
VCCIO[27]
VccALVDS 3.3 0.001
V1 +VCCSPI 2 1 +3.3V_M
VCCSPI
FDI
@ RH202 0_0603_5%~D
+1.05V_RUN_VTT AU20
VCCDMI[2]
VccTX_LVDS 1.8 0.04
1 2 1 +3.3V_RUN
@ RH204 0_0603_5%~D
B BD82HM77 SLJ8C C1_BGA989~D CH54 B
1U_0402_6.3V6K~D INTEL feedback 0307
2
+1.05V_RUN
1 2 +VCCAPLL_FDI
@ RH195 0.022_0805_1%
+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
2 1
@ RH197 0_0603_5%~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (6/8)
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 19 of 61
Rev
1.0
5 4 3 2 1
+PWR_SRC_S +5V_ALW +5V_ALW_PCH
QH4
+1.05V_RUN SSM3K7002FU_SC70-3~D
1
1 2 +VCCACLK 1 3
S
+3.3V_ALW_PCH
20K_0402_5%~D
0.1U_0402_10V7K~D
@ RH200 0.022_0805_1%
UH4J POWER RH279
1
+3.3V_ALW2 1 2 100K_0402_5%~D 1
G
2
RH278
RH201 0_0402_5%~D 1 AD49 N26 +1.05V_RUN
2
VCCACLK VCCIO[29]
3300P_0402_50V7K~D
CH98
1 2 5V_ALW_PCH_ENABLE
@ RH253 0_0402_5%~D CH55 P26 1 1
VCCIO[30]
1
0.1U_0402_10V7K~D +VCCDSW3_3 D 2
T16
2
D 2 VCCDSW3_3
CH107
CH56 QH6 D
P28 <42> ALW_ON_3.3V# 2
VCCIO[31] 1U_0402_6.3V6K~D G SSM3K7002FU_SC70-3~D
+PCH_VCCDSW V12 T27 2 S 2
3
+1.05V_RUN @ LH3 DCPSUSBYP VCCIO[32]
1
10UH_LBR2012T100M_20%~D T29
VCCIO[33]
@
1 2 CH57 +3.3V_RUN_VCC_CLKF33 T38
VCC3_3[5]
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D +3.3V_ALW_PCH
2
0.1U_0402_10V7K~D
1 T23
+1.05V_RUN +VCCAPLL_CPY_PCH VCCSUS3_3[7]
BH23 1
@ VCCAPLLDMI2
T24 +3.3V_ALW_PCH
VCCSUS3_3[8] +5V_ALW_PCH +3.3V_ALW_PCH
0.1U_0402_10V7K~D
CH59
AL29
2 VCCIO[14]
CH58
VCCSUS3_3[9] V23 1
2
USB
2
CH60
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] RH208 DH2
1 2
P24 10_0402_1%~D RB751S40T1_SOD523-2~D
VCCSUS3_3[6]
@
CH61
1U_0402_6.3V6K~D AA19
1
2 VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26 +1.05V_RUN
AA21 VCCASW[2] 1
AA24 M26 +PCH_V5REF_SUS CH63
VCCASW[3] V5REF_SUS
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1 1 +3.3V_ALW_PCH 0.1U_0402_10V7K~D
2
CH64
CH65
0.1U_0402_10V7K~D
AA26 VCCASW[4]
Clock and Miscellaneous
AN23 +VCCA_USBSUS 1
DCPSUS[4]
AA27 VCCASW[5]
2 2
CH66
VCCSUS3_3[1] AN24
AA29 VCCASW[6] 2
+1.05V_M AA31 +5V_RUN +3.3V_RUN
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] V5REF
2
C C
1 1U_0402_6.3V6K~D 1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
AC27 RH213 DH3
CH67 VCCASW[9]
CH68
CH69
N20 +3.3V_ALW_PCH 10_0402_1%~D RB751S40T1_SOD523-2~D
VCCSUS3_3[2]
AC29 1
PCI/GPIO/LPC
2 2 2 VCCASW[10]
N22
1
VCCSUS3_3[3] CH70 +PCH_V5REF_RUN
AC31 VCCASW[11]
P20 1U_0603_10V7K~D +3.3V_RUN
VCCSUS3_3[4] 2
AD29 1
VCCASW[12]
P22
+3.3V_RUN VCCSUS3_3[5] CH71
AD31 1
VCCASW[13] 1U_0603_10V7K~D
W21 AA16 CH72 2
VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
W23 W16 2 +3.3V_RUN
VCCASW[15] VCC3_3[8]
1 2 +3.3V_RUN_VCC_CLKF33 W24 T34
VCCASW[16] VCC3_3[4]
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
RH215 0.022_0805_1% 1 1 1
W26 +VCCA_USBSUS
VCCASW[17]
CH74
@ CH75
W29 +3.3V_RUN 0.1U_0402_10V7K~D
2 2 VCCASW[18] 2 1
CH73
W31 AJ2 @CH62
@CH62
VCCASW[19] VCC3_3[2] 1U_0402_6.3V6K~D
1 2
W33
VCCASW[20] CH76
AF13 +1.05V_RUN
VCCIO[5] 0.1U_0402_10V7K~D
2 1
+VCCRTCEXT N16
DCPRTC CH77
1 AH13
+1.05V_+1.5V_1.8V_RUN VCCIO[12] 1U_0402_6.3V6K~D
CH78 Y49 AH14 2
0.1U_0402_10V7K~D VCCVRM[4] VCCIO[13]
2
B +1.05V_RUN AF14 LH5 @ B
+1.05V_RUN_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D
BD47
VCCADPLLA +VCCSATAPLL
AK1 1 2 +1.05V_RUN
SATA
+1.05V_RUN_VCCA_B_DPL VCCAPLLSATA +1.05V_+1.5V_1.8V_RUN
1 BF47 1
VCCADPLLB @ CH80
CH79 AF11 10U_0603_6.3V6M~D
1U_0402_6.3V6K~D VCCVRM[1]
AF17
2 VCCIO[7] 2
AF33
VCCDIFFCLKN[1]
AF34 AC16 +1.05V_RUN
VCCDIFFCLKN[2] VCCIO[2]
1 2 CH81 AG34
VCCDIFFCLKN[3]
1U_0402_6.3V6K~D AC17 1
VCCIO[3]
1 AG33 AD17 CH82
VCCSSC VCCIO[4] 1U_0402_6.3V6K~D
+1.05V_M CH96 2
1U_0402_6.3V6K~D +VCCSST V16 +1.05V_M
2 DCPSST
1 2 +1.05V_M_VCCSUS
@ RH248 0.022_0805_1% 1 +1.05V_M_VCCSUS
1 T17 T21
CH84 DCPSUS[1] VCCASW[22]
V19
0.1U_0402_10V7K~D CH83 @ DCPSUS[2]
MISC
+1.05V_RUN_VTT 2 1U_0402_6.3V6K~D V21
2 VCCASW[23]
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
BJ8
CPU
V_PROC_IO
1 1 1 T19
VCCASW[21]
+RTC_CELL
CH86
CH87
CH85
4.7U_0603_6.3V6K~D
2 2 2 A22 P32
VCCRTC VCCSUSHDA +3.3V_ALW_PCH
RTC
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
HDA
1 1 1 1
LH6 BD82HM77 SLJ8C C1_BGA989~D
A +1.05V_RUN A
CH88
CH89
10UH_LBR2012T100M_20%~D CH90 CH91
1 2 +1.05V_RUN_VCCA_A_DPL 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D
2 2 2 2
1 2 +1.05V_RUN_VCCA_B_DPL
220U_B2_2.5VM_R35M~D
220U_B2_2.5VM_R35M~D
LH7
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
10UH_LBR2012T100M_20%~D 1 1
1 1 Compal Electronics, Inc.
CH94
CH92
CH95
CH93
+ +
Title
2 2 2 2 PCH (7/8)
5 4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 20 of 61
Rev
1.0
5 4 3 2 1
UH4I
AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 K46
D VSS[163] VSS[263] D
B15 K7
UH4H VSS[164] VSS[264]
B19 L18
VSS[165] VSS[265]
H5 B23 L2
VSS[0] VSS[166] VSS[266]
B27 L20
VSS[167] VSS[267]
AA17 AK38 B31 L26
VSS[1] VSS[80] VSS[168] VSS[268]
AA2 AK4 B35 L28
VSS[2] VSS[81] VSS[169] VSS[269]
AA3 AK42 B39 L36
VSS[3] VSS[82] VSS[170] VSS[270]
AA33 AK46 B7 L48
VSS[4] VSS[83] VSS[171] VSS[271]
AA34 AK8 F45 M12
VSS[5] VSS[84] VSS[172] VSS[272]
AB11 AL16 BB12 P16
VSS[6] VSS[85] VSS[173] VSS[273]
AB14 AL17 BB16 M18
VSS[7] VSS[86] VSS[174] VSS[274]
AB39 VSS[8] VSS[87] AL19 BB20 VSS[175] VSS[275] M22
AB4 VSS[9] VSS[88] AL2 BB22 VSS[176] VSS[276] M24
AB43 VSS[10] VSS[89] AL21 BB24 VSS[177] VSS[277] M30
AB5 VSS[11] VSS[90] AL23 BB28 VSS[178] VSS[278] M32
AB7 VSS[12] VSS[91] AL26 BB30 VSS[179] VSS[279] M34
AC19 VSS[13] VSS[92] AL27 BB38 VSS[180] VSS[280] M38
AC2 VSS[14] VSS[93] AL31 BB4 VSS[181] VSS[281] M4
AC21 VSS[15] VSS[94] AL33 BB46 VSS[182] VSS[282] M42
AC24 VSS[16] VSS[95] AL34 BC14 VSS[183] VSS[283] M46
AC33 VSS[17] VSS[96] AL48 BC18 VSS[184] VSS[284] M8
AC34 VSS[18] VSS[97] AM11 BC2 VSS[185] VSS[285] N18
AC48 VSS[19] VSS[98] AM14 BC22 VSS[186] VSS[286] P30
AD10 VSS[20] VSS[99] AM36 BC26 VSS[187] VSS[287] N47
AD11 VSS[21] VSS[100] AM39 BC32 VSS[188] VSS[288] P11
AD12 VSS[22] VSS[101] AM43 BC34 VSS[189] VSS[289] P18
AD13 VSS[23] VSS[102] AM45 BC36 VSS[190] VSS[290] T33
AD19 VSS[24] VSS[103] AM46 BC40 VSS[191] VSS[291] P40
AD24 VSS[25] VSS[104] AM7 BC42 VSS[192] VSS[292] P43
AD26 VSS[26] VSS[105] AN2 BC48 VSS[193] VSS[293] P47
AD27 VSS[27] VSS[106] AN29 BD46 VSS[194] VSS[294] P7
AD33 VSS[28] VSS[107] AN3 BD5 VSS[195] VSS[295] R2
C C
AD34 VSS[29] VSS[108] AN31 BE22 VSS[196] VSS[296] R48
AD36 VSS[30] VSS[109] AP12 BE26 VSS[197] VSS[297] T12
AD37 VSS[31] VSS[110] AP19 BE40 VSS[198] VSS[298] T31
AD38 VSS[32] VSS[111] AP28 BF10 VSS[199] VSS[299] T37
AD39 VSS[33] VSS[112] AP30 BF12 VSS[200] VSS[300] T4
AD4 VSS[34] VSS[113] AP32 BF16 VSS[201] VSS[301] W34
AD40 VSS[35] VSS[114] AP38 BF20 VSS[202] VSS[302] T46
AD42 AP4 BF22 T47
VSS[36] VSS[115] VSS[203] VSS[303]
AD43 AP42 BF24 T8
VSS[37] VSS[116] VSS[204] VSS[304]
AD45 AP46 BF26 V11
VSS[38] VSS[117] VSS[205] VSS[305]
AD46 AP8 BF28 V17
VSS[39] VSS[118] VSS[206] VSS[306]
AD8 AR2 BD3 V26
VSS[40] VSS[119] VSS[207] VSS[307]
AE2 AR48 BF30 V27
VSS[41] VSS[120] VSS[208] VSS[308]
AE3 AT11 BF38 V29
VSS[42] VSS[121] VSS[209] VSS[309]
AF10 AT13 BF40 V31
VSS[43] VSS[122] VSS[210] VSS[310]
AF12 AT18 BF8 V36
VSS[44] VSS[123] VSS[211] VSS[311]
AD14 AT22 BG17 V39
VSS[45] VSS[124] VSS[212] VSS[312]
AD16 AT26 BG21 V43
VSS[46] VSS[125] VSS[213] VSS[313]
AF16 AT28 BG33 V7
VSS[47] VSS[126] VSS[214] VSS[314]
AF19 AT30 BG44 W17
VSS[48] VSS[127] VSS[215] VSS[315]
AF24 AT32 BG8 W19
VSS[49] VSS[128] VSS[216] VSS[316]
AF26 AT34 BH11 W2
VSS[50] VSS[129] VSS[217] VSS[317]
AF27 AT39 BH15 W27
VSS[51] VSS[130] VSS[218] VSS[318]
AF29 AT42 BH17 W48
VSS[52] VSS[131] VSS[219] VSS[319]
AF31 AT46 BH19 Y12
VSS[53] VSS[132] VSS[220] VSS[320]
AF38 AT7 H10 Y38
VSS[54] VSS[133] VSS[221] VSS[321]
AF4 AU24 BH27 Y4
VSS[55] VSS[134] VSS[222] VSS[322]
AF42 AU30 BH31 Y42
VSS[56] VSS[135] VSS[223] VSS[323]
AF46 AV16 BH33 Y46
VSS[57] VSS[136] VSS[224] VSS[324]
AF5 AV20 BH35 Y8
VSS[58] VSS[137] VSS[225] VSS[325]
AF7 AV24 BH39 BG29
VSS[59] VSS[138] VSS[226] VSS[328]
AF8 AV30 BH43 N24
B VSS[60] VSS[139] VSS[227] VSS[329] B
AG19 AV38 BH7 AJ3
VSS[61] VSS[140] VSS[228] VSS[330]
AG2 AV4 D3 AD47
VSS[62] VSS[141] VSS[229] VSS[331]
AG31 AV43 D12 B43
VSS[63] VSS[142] VSS[230] VSS[333]
AG48 AV8 D16 BE10
VSS[64] VSS[143] VSS[231] VSS[334]
AH11 AW14 D18 BG41
VSS[65] VSS[144] VSS[232] VSS[335]
AH3 AW18 D22 G14
VSS[66] VSS[145] VSS[233] VSS[337]
AH36 AW2 D24 H16
VSS[67] VSS[146] VSS[234] VSS[338]
AH39 AW22 D26 T36
VSS[68] VSS[147] VSS[235] VSS[340]
AH40 AW26 D30 BG22
VSS[69] VSS[148] VSS[236] VSS[342]
AH42 AW28 D32 BG24
VSS[70] VSS[149] VSS[237] VSS[343]
AH46 AW32 D34 C22
VSS[71] VSS[150] VSS[238] VSS[344]
AH7 AW34 D38 AP13
VSS[72] VSS[151] VSS[239] VSS[345]
AJ19 AW36 D42 M14
VSS[73] VSS[152] VSS[240] VSS[346]
AJ21 AW40 D8 AP3
VSS[74] VSS[153] VSS[241] VSS[347]
AJ24 AW48 E18 AP1
VSS[75] VSS[154] VSS[242] VSS[348]
AJ33 AV11 E26 BE16
VSS[76] VSS[155] VSS[243] VSS[349]
AJ34 AY12 G18 BC16
VSS[77] VSS[156] VSS[244] VSS[350]
AK12 AY22 G20 BG28
VSS[78] VSS[157] VSS[245] VSS[351]
AK3 AY28 G26 BJ28
VSS[79] VSS[158] VSS[246] VSS[352]
G28
BD82HM77 SLJ8C C1_BGA989~D VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A
BD82HM77 SLJ8C C1_BGA989~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (8/8)
5 4
WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 21 of 61
Rev
1.0
5 4 3 2 1
Follow CONN List_0609A
JFAN1
+FAN1_VOUT FAN1_DET# 1 +3.3V_ALW
1
Place under CPU 2 2
RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3
Place C266 close to the Q12 as possible 3
22U_0805_6.3V6M~D
4 BC_INT#_EMC4022 2 1
4
1
1 5 R386 10K_0402_5%~D
G5
D2
C219
REM_DIODE1_P_4022 6 @
G6
1
@ 2 C ACES_50273-0040N-001
D C266 2 +3.3V_RUN +3.3V_M D
2
2
100P_0402_50V8J~D B
CONN@
E Q12
3
1 MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4022 BC_INT#_EMC4022 2 1
R385 10K_0402_5%~D
@
2 1 FAN1_TACH_FB 2 1
R430 10K_0402_5%~D R426 10K_0402_5%~D
+5V_RUN FAN1_DET# 2 1
R402 10K_0402_5%~D
GPIO3 power rail is RTC so
10U_0805_10V6K~D
0.1U_0402_25V6K~D
1 1
+3.3V_ALW
C276
C275
double check Pull up or
2 2
+3.3V_RUN use 5048 contrl
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
1 1 U9 FAN1_DET# 2 1
C305
C738
@ R408 10K_0402_5%~D
2 VDD_H
2 2 +3.3V_M 3 VDD_H THERMATRIP2#
6 VDD_L THERMTRIP2# 17
(1) DP3/DN3 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14 1 2 VDD_PWRGD 13 VDD_PWRGD
R389 10K_0402_5%~D 18
(2) DP5/DN5 for Skin on Q13, place Q13 close to Vcore VR choke. N/C
1 2 REM_DIODE1_N_4022 23
C270 2200P_0402_50V7K~D REM_DIODE1_P_4022 DN1/THERM
24 DP1/VREF_T SYS_SHDN# 19 THERM_STP# <45>
REM_DIODE2_P_4022
100P_0402_50V8J~D
2 1 REM_DIODE2_N_4022 26 20 POWER_SW# 1 2
DN2/DP4 POWER_SW# +RTC_CELL
1 1 C279 2200P_0402_50V7K~D REM_DIODE2_P_4022 27 @R390
@ R390 47K_0402_1%~D
DP2/DN4
1
E
C @
C277
C @C272
@ C272
B C
2 2 30 N/C ACAVAIL_CLR 21 ACAV_IN <40,52,53>
100P_0402_50V8J~D B Q13 29 9 BC_INT#_EMC4022
2 E 2 C
MMBT3904WT1G_SC70-3~D N/C ATF_INT#/BC_IRQ# BC_INT#_EMC4022 <40>
3
Q14 REM_DIODE2_N_4022
MMBT3904WT1G_SC70-3~D 2 1 R387 VCP2 31
<52> MAX8731_IINP VCP
4.7K_0402_5%~D VCP_4021 25 VIN
FAN_OUT 5 +FAN1_VOUT
VSET_4021 28 4
VSET FAN_OUT
Test3
0 = 4021 SMSC request
1 = 4022 8 BC_CLK_EMC4022 <40>
FAN1_TACH_FB SMCLK/BC_CLK
10 7 BC_DAT_EMC4022 <40>
+3.3V_M @ R407 2 TACH/GPIO1 SMDATA/BC_DATA
+3.3V_M 1 10K_0402_5%~D
R404 2 1 10K_0402_5%~D 11
TEST3
1
FAN1_DET# 1 2 FAN1_DET#_R 15
<39> FAN1_DET# GPIO3/PWM/THERMTRIP_SIO +3.3V_M
R395 @ R806 0_0402_5%~D
8.2K_0402_5%~D
1
2
+1.05V_RUN_VTT THERMATRIP2# 1 2 3V_PWROK# 12 R388
<40> PCH_PWRGD# 3V_PWROK#
R399 R391 1K_0402_1%~D 22_0402_5%~D
1
0.1U_0402_25V6K~D
2.2K_0402_5%~D C 1
C278
1 2 2 1 +VCC_4022
2
B VDD +ADDR_XEN
32 1 2 +VCC_4022
ADDR_MODE/XEN
0.1U_0402_25V6K~D
1U_0402_6.3V6K~D
Q16 E 4.7K_0402_5%~D R393 1 1
3
PMST3904_SOT323-3~D 2 14
TEST1
C273
C1179
<7> H_THERMTRIP# 22
TEST2
+RTC_CELL 16 33
RTC_PWR3V VSS 2 2
1
1U_0402_6.3V6K~D
B EMC4021-1-EZK-TR_QFN32_5X5~D R403 B
1
10K_0402_5%~D
C274
SMSC request
2
2
SMSC review in 6/22
2 1 VCP_4021
R429 10K_0402_5%~D
+RTC_CELL
VSET_4021
0.1U_0402_25V6K~D
1 2
C281 0.1U_0402_25V6K~D
1
5
1 U10
R406 TC7SH08FU_SSOP5~D 1
P
B DOCK_PWR_SW# <40>
C282
1.24K_0402_1%~D POWER_SW# 4 O
2 POWER_SW_IN# <40>
A
G
2
2
3
Rest=1.24k, Tp=92degree
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 22 of 61
Rev
1.0
2 1
B
SW for MB/DOCK B
+5V_RUN +3.3V_RUN
U18
PCH_CRT_RED 1 16
<16> PCH_CRT_RED PCH_CRT_GRN R 5V VDD
<16> PCH_CRT_GRN 2 G
PCH_CRT_BLU 5 4
<16> PCH_CRT_BLU PCH_CRT_HSYNC B VDD
<16> PCH_CRT_HSYNC 6 H_SOURCE VDD 23
PCH_CRT_VSYNC 7 32
<16> PCH_CRT_VSYNC PCH_CRT_DDC_DAT V_HOURCE VDD
<16> PCH_CRT_DDC_DAT 9 SDA_SOURCE
PCH_CRT_DDC_CLK 10 27 RED_CRT
<16> PCH_CRT_DDC_CLK SCL_SOURCE R1 RED_CRT <37>
25 GREEN_CRT
+3.3V_RUN G1 BLUE_CRT GREEN_CRT <37>
B1 22
CRT_SWITCH HSYNC_BUF BLUE_CRT <37>
<39> CRT_SWITCH 30 SEL H1_OUT 20
VSYNC_BUF HSYNC_BUF <37>
V1_OUT 18
DAT_DDC2_CRT VSYNC_BUF <37>
SDA1 12
CLK_DDC2_CRT DAT_DDC2_CRT <37>
29 TEST SCL1 14 CLK_DDC2_CRT <37>
1 2 8 26 RED_DOCK
+3.3V_RUN Reserved R2 RED_DOCK <38>
R556 4.7K_0402_5%~D 24 GREEN_DOCK
G2 BLUE_DOCK GREEN_DOCK <38>
3 21
GND B2 HSYNC_DOCK BLUE_DOCK <38>
11 19
GND H2_OUT VSYNC_DOCK HSYNC_DOCK <38>
28 17
GND V2_OUT DAT_DDC2_DOCK VSYNC_DOCK <38>
31 13
GND SDA2 CLK_DDC2_DOCK DAT_DDC2_DOCK <38>
33 15
GPAD SCL2 CLK_DDC2_DOCK <38>
PI3V713-AZLEX_TQFN32_6X3~D
Change P/N to TI (SA00004RS0L) 12/13
+3.3V_RUN +5V_RUN
SEL1/SEL2 Chanel Source
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0 A=B1 MB
1 1 1 1 1 1
1 A=B2 APR/SPR @ @
C332
C333
C334
C335
C336
C339
2 2 2 2 2 2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
CRT/Video switch
2
WWW.AliSaler.Com 1
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012 Sheet 23 of 61
Rev
1.0
5 4 3 2 1
DMIC0 Q18
Follow CONN List_0824 LCD Power SI3456DDV-T1-GE3_TSOP6~D
+BL_PWR_SRC +CAMERA_VDD +3.3V_RUN +PWR_SRC_S +LCDVDD +3.3V_ALW
100P_0402_50V8K~D
100P_0402_50V8K~D
DMIC_CLK0 1 @ 1 @
D
+LCDVDD
S
6
+3.3V_ALW
C1217
C1218
1 2 LDDC_CLK_PCH 4 5
0.1U_0402_25V6K~D
JLVDS1 R159 2.2K_0402_5%~D 2
1
1 2 2 1 2 LDDC_DATA_PCH R412 1
1
10K_0402_5%~D
2 DMIC0 R160 2.2K_0402_5%~D 470K_0402_5%~D
G
2 1
C292
3 R413
3
3
R414
4 DMIC_CLK0 Place near to JLVDS1 130_0402_1%~D
2
4 +LCVDVDD_CHG
5
2
5 2
DMN66D0LDW-7_SOT363-6~D
0.022U_0402_25V7K~D
6 USBP12_D-
6
4.7M_0402_5%~D
7 USBP12_D+
2
7
3
8 CAM_MIC_CBL_DET# 1
8 CAM_MIC_CBL_DET# <17>
1
D D
9
9
Q19B
C293
10 Q19A
10
R1632
11 DMN66D0LDW-7_SOT363-6~D 2 5
11 DISP_ON 2
12
12
1
13 1 2 BIA_PWM_LVDS
2
13 LE92 BLM18BB221SN1D_2P~D D6
14 LCD_CBL_DET# <17>
14
15
15
16 LCD_BCLK+_PCH <16> <39> LCD_VCC_TEST_EN 2
16 EN_LCDPWR
17 LCD_BCLK-_PCH <16> 1 2
17
5P_0402_50V8C~D
5P_0402_50V8C~D
18
18
19 LCD_B2+_PCH <16> 1 1 <16,39> ENVDD_PCH 3
19 @ @ Q20
20 20 LCD_B2-_PCH <16>
C40
C
C41
21 PDTC124EU_SC70-3~D
40
LCD_B1+_PCH <16>
3
21 BAT54CW_SOT323-3~D
22 22 LCD_B1-_PCH <16>
23 2 2
23 LCD_B0+_PCH <16>
24 24 LCD_B0-_PCH <16>
25 25
26 26 LCD_ACLK+_PCH <16>
27 27 LCD_ACLK-_PCH <16>
28 28
29 29 LCD_A2+_PCH <16>
5P_0402_50V8C~D
5P_0402_50V8C~D
30 1 1 Q21
30 LCD_A2-_PCH <16>
31 @ @ FDC654P-G_SSOT-6~D
31 LCD_A1+_PCH <16>
C42
C43
+PWR_SRC
32 32 LCD_A1-_PCH <16> 40mil
40mil
D
33 33 LCD_A0+_PCH <16> 6
2 2
S
34 34 LCD_A0-_PCH <16> 4 5 +BL_PWR_SRC
35 LDDC_DATA_PCH 2
35 LDDC_CLK_PCH LDDC_DATA_PCH <16> +LCDVDD +3.3V_RUN +BL_PWR_SRC
41 G1 36 36 LDDC_CLK_PCH <16> 1
0.1U_0603_50V7K~D
1000P_0402_50V7K~D
G
42 37 LCD_TST
G2 37 LCD_TST <39>
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
43 38 +3.3V_RUN 1
3
G3 38
1
44 G4 39 39 1
45 40 +LCDVDD 1 1 1 R422 C296
G5 40
C298
C243
C246
C297
C 100K_0402_5%~D C
0.1U_0603_50V7K~D
STARC_111H40-100000-G4-R 2
CONN@ 2
2
2 2 2
PWR_SRC_ON
Q22
Close to JLVDS1.39,40 Close to JLVD1.38 Close to JLVD1.9 SSM3K7002FU_SC70-3~D
1 2 1 3
S
R423 47K_0402_5%~D
D66 D67
RB751VM-40TE-17_SOD323-2~D RB751VM-40TE-17_SOD323-2~D
G
2
BIA_PWM_LVDS 1 2 DISP_ON 1 2
BIA_PWM_PCH <16> PANEL_BKEN_PCH <16>
1
1
EN_INVPWR
<40> EN_INVPWR
R1137 D68 R1138 D69 FDC654P: P CHANNAL
10K_0402_5%~D RB751VM-40TE-17_SOD323-2~D 100K_0402_5%~D RB751VM-40TE-17_SOD323-2~D
1 2 BIA_PWM_EC <40> 1 2 PANEL_BKEN_EC <39>
Panel backlight power control by EC
2
For Webcam
B B
DMIC_CLK0
+CAMERA_VDD Q23 DMIC_CLK0 <29>
PMV65XP_SOT23-3~D DMIC0
DMIC0 <29>
3
1 3
D
+3.3V_RUN
0.1U_0402_25V6K~D
10U_0805_10V6K~D
PESD5V0U2BT_SOT23-3~D
D8
0.1U_0402_25V6K~D
1 1
G
2
C299
C300
1
C301
2 2
2
1
Change CIS symbol_ 12/07
CCD_OFF
<39> CCD_OFF
L10
USBP12+ 4 3 USBP12_D+
<17> USBP12+ 4 3
Webcam PWR CTRL
USBP12- 1 2 USBP12_D-
<17> USBP12- 1 2
3
OCF2012181YZF_4P
PESD5V0U2BT_SOT23-3~D
D9
1 2
@ R427 0_0402_5%~D
A A
1 2
@ R428 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
1
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LVDS & CAM Conn
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 24 of 61
5 4 3 2 1
2 1
+5V_RUN
BAT1000-7-F_SOT23-3~D
2
3 NC
D4
Note:
AOI found open soldering is
due to the difference between
1
+VDISPLAY_VCC
Main and 2nd on PAD dimension.
L99 F2 change to 2nd source
1 2 "SP040003H0L (F_MF-MSMF050-2)"
10U_0805_10V6K~D
9NH_0402HS-9N0EJTS_5%~D PCB Footprint +5V_RUN_HDMI
0.5A_15V_SMD1812P050TF
0.1U_0402_10V7K~D
@ L19
@L19 1 1
C338
2 1 TMDSB_PCH_CLK#_C 4 4 3 TMDSB_CON_CLK#
<16> TMDSB_PCH_CLK# 3
2
0_1206_5%~D
C337
C353 0.1U_0402_10V7K~D @
2 2
3.9P_0402_50V8C
3.9P_0402_50V8C
+3.3V_RUN
R5
2 1 TMDSB_PCH_CLK_C 1 2 TMDSB_CON_CLK
<16> TMDSB_PCH_CLK 1 2
F2
C352 0.1U_0402_10V7K~D 1 1 CONN list 0624C
C1209
C1210
DLW21SN900HQ2L_0805_4P~D
1
L100
HDMI_CEC 2 1 1 2
DC232001000
R1165 10K_0402_5%~D 9NH_0402HS-9N0EJTS_5%~D 2 2
B JHDMI1 B
L101 HDMIB_PCH_HPD_R 19 HP_DET
1 2 18 +5V
9NH_0402HS-9N0EJTS_5%~D 17
PCH_SDVO_CTRLDATA_R DDC/CEC_GND
16 SDA
@L20
@ L20 PCH_SDVO_CTRLCLK_R 15
TMDSB_PCH_P0_C TMDSB_CON_P0 SCL
<16> TMDSB_PCH_P0 2 1 1 1 2 14
C351 0.1U_0402_10V7K~D 2 HDMI_CEC Reserved
13 CEC
TMDSB_CON_CLK# 12 20
CK- GND
3.9P_0402_50V8C
3.9P_0402_50V8C
TMDSB_PCH_P2_C R452 1 2 604_0402_1% HDMI_OB 2 1 TMDSB_PCH_N0_C 4 3 TMDSB_CON_N0 11 21
TMDSB_PCH_N2_C <16> TMDSB_PCH_N0 4 3 TMDSB_CON_CLK CK_shield GND
R450 1 2 604_0402_1% C350 0.1U_0402_10V7K~D 1 1 10 22
CK+ GND
C1211
C1212
TMDSB_PCH_P1_C R448 1 2 604_0402_1% DLW21SN900HQ2L_0805_4P~D TMDSB_CON_N0 9 23
TMDSB_PCH_N1_C R449 604_0402_1% L102 D0- GND
1 2 8 D0_shield
TMDSB_PCH_P0_C R454 1 2 604_0402_1% 1 2 TMDSB_CON_P0 7
TMDSB_PCH_N0_C R453 604_0402_1% 9NH_0402HS-9N0EJTS_5%~D 2 2 TMDSB_CON_N1 D0+
1 2 6 D1-
TMDSB_PCH_CLK_C R456 1 2 604_0402_1% 5
TMDSB_PCH_CLK#_C R455 604_0402_1% L103 TMDSB_CON_P1 D1_shield
1 2 4 D1+
1 2 TMDSB_CON_N2 3
9NH_0402HS-9N0EJTS_5%~D D2-
2 D2_shield
1
D TMDSB_CON_P2 1 D2+
+3.3V_RUN R458 1 2 10K_0402_5%~D 2 @L22
@ L22
G 2 1 TMDSB_PCH_P1_C 1 1 2 TMDSB_CON_P1 HONGL_13-13201904CP
<16> TMDSB_PCH_P1 2
Q26 S C347 0.1U_0402_10V7K~D
3
SSM3K7002FU_SC70-3~D CONN@
3.9P_0402_50V8C
3.9P_0402_50V8C
2 1 TMDSB_PCH_N1_C 4 3 TMDSB_CON_N1
<16> TMDSB_PCH_N1 4 3
C346 0.1U_0402_10V7K~D 1 1
C1213
C1214
DLW21SN900HQ2L_0805_4P~D
L104
1 2
9NH_0402HS-9N0EJTS_5%~D 2 2
L105
1 2
9NH_0402HS-9N0EJTS_5%~D
@L21
@ L21
2 1 TMDSB_PCH_P2_C 1 1 2 TMDSB_CON_P2
<16> TMDSB_PCH_P2 2
C349 0.1U_0402_10V7K~D
3.9P_0402_50V8C
3.9P_0402_50V8C
2 1 TMDSB_PCH_N2_C 4 3 TMDSB_CON_N2
<16> TMDSB_PCH_N2 4 3
C348 0.1U_0402_10V7K~D 1 1
C1215
C1216
DLW21SN900HQ2L_0805_4P~D
L106
1 2
9NH_0402HS-9N0EJTS_5%~D 2 2
+5V_RUN
+3.3V_RUN
2
@ D65
RB751VM-40TE-17_SOD323-2~D R1163
0_0402_5%~D
Q120A
1
2
2
DMN66D0LDW-7_SOT363-6~D
1 6 PCH_SDVO_CTRLCLK_R 1 2 +5V_HDMI_DDC
<16> PCH_SDVO_CTRLCLK
R1153 2.2K_0402_5%~D
5
A A
4 3 PCH_SDVO_CTRLDATA_R 1 2
<16> PCH_SDVO_CTRLDATA
R1152 2.2K_0402_5%~D
Q120B
DMN66D0LDW-7_SOT363-6~D
+3.3V_RUN
1M_0402_5%~D
2
R1168
2
G
1
3 1 HDMIB_PCH_HPD_R 1 2
<16> HDMIB_PCH_HPD R1128 20K_0402_5%~D HDMI 46@
S
Q121
Part Number Description
DELL CONFIDENTIAL/PROPRIETARY
RO0000002HM HDMI W/Logo:RO0000002HM
SSM3K7002FU_SC70-3~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI port
2
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
Sheet 25 of 61
Rev
1.0
5 4 3 2 1
+3.3V_RUN
AUX/DDC SW for DPC to E-DOCK 1 2
C356
0.1U_0402_25V6K~D
C357 U20
D 0.1U_0402_10V7K~D D
1 BE0 VCC
14
2 1 DPC_AUX_C 2 13
<16> DPC_PCH_DOCK_AUX A0 BE3
DPC_DOCK_AUX 3 12
<38> DPC_DOCK_AUX B0 A3 PCH_DDPC_CTRLCLK <16>
4 BE1 B3
11
2 1 DPC_AUX#_C 5 10
<16> DPC_PCH_DOCK_AUX# A1 BE2
C360 0.1U_0402_10V7K~D
DPC_DOCK_AUX# 6 9
<38> DPC_DOCK_AUX# B1 A2 PCH_DDPC_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
+5V_RUN
2 1
C365
0.1U_0402_25V6K~D
5
1
U21
P
NC
DPC_CA_DET 2 4 DPC_CA_DET#
<38> DPC_CA_DET A Y
G
TC7SET04FU_SSOP5~D
3
C C
Note:When implement 2nd source, please check Vil and Vih spec is meet main source spec
There is a new die for PI3C3125. Sample availabe on May.
+3.3V_RUN
AUX/DDC SW for DPD to E-DOCK 1 2
C366
0.1U_0402_25V6K~D
C367 U23
0.1U_0402_10V7K~D 1 14
DPD_AUX_C BE0 VCC
<16> DPD_PCH_DOCK_AUX 2 1 2
A0 BE3 13
DPD_DOCK_AUX 3 12
<38> DPD_DOCK_AUX B0 A3 PCH_DDPD_CTRLCLK <16>
4 11
DPD_AUX#_C BE1 B3
<16> DPD_PCH_DOCK_AUX# 2 1 5 10
C368 0.1U_0402_10V7K~D A1 BE2
DPD_DOCK_AUX# 6 9
<38> DPD_DOCK_AUX# B1 A2 PCH_DDPD_CTRLDATA <16>
7 8
GND B2
PI3C3125LEX_TSSOP14~D
B B
+5V_RUN
2 1
C369
0.1U_0402_25V6K~D
5
U24
P
NC
DPD_CA_DET 2 4 DPD_CA_DET#
<38> DPD_CA_DET A Y
G
TC7SET04FU_SSOP5~D
3
Note:When implement 2nd source, please check Vil and Vih spec is meet main source spec
+3.3V_RUN
1 2 PCH_DDPC_CTRLCLK
R487 2.2K_0402_5%~D Intel WW18 Strapping option
1 2 PCH_DDPC_CTRLDATA
R488 2.2K_0402_5%~D
1 2 PCH_DDPD_CTRLCLK
A R489 2.2K_0402_5%~D A
PCH_DDPD_CTRLDATA
Intel WW18 Strapping option
1 2
R490 2.2K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
1 2 DPD_CA_DET
R491
1
1M_0402_5%~D
2 DPC_CA_DET Compal Electronics, Inc.
R492 1M_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP SW
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 26 of 61
Rev
1.0
5 4 3 2 1
D D
+5V_ALW
+PWR_SRC_S
+3.3V_ALW2
1
@ R499
1
2
5
6
100K_0402_5%~D
1
D @ Q27
@ R500 G
2
100K_0402_5%~D HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
S
DMN66D0LDW-7_SOT363-6~D
+3.3V_RUN +5V_HDD +5V_RUN
4
3
@ @ PJP3
1M_0402_5%~D
0.1U_0603_50V7K~D
@ 1 1 2
2
1
Q28B
10U_0805_10V6K~D
@
1
R517
5 1 1 JUMP_43X79
1
C393
PJP53 short
6
DMN66D0LDW-7_SOT363-6~D
C394
PAD-OPEN1x1m @
4
short R504
2
2 2
Q28A
100K_0402_5%~D
<35,39,42,47,48> RUN_ON 1 2 2
2
2
@ R1621 0_0402_5%~D
+3.3V_RUN_FFS 1 2
<11,16,35,39,42,47,48,49> SIO_SLP_S3#
1
1
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
@ R1624 0_0402_5%~D
@R505
@ R505
1 1 100K_0402_5%~D
U88
C388
C387
LNG3DM
2
C C
RES 10
2 2 1 13
VDD_IO RES
14 VDD RES 15
RES 16
HDD_FALL_INT 11
<17> HDD_FALL_INT FFS_INT2 INT 1
9 INT 2 GND 5
GND 12
7
SDO/SA0
<7,12,13,14,15,34> DDR_XDP_WAN_SMBDAT 6
SDA / SDI / SDO
<7,12,13,14,15,34> DDR_XDP_WAN_SMBCLK 4
SCL/SPC
2
NC
8 3
CS NC
LNG3DMTR_LGA16_3X3~D
+3.3V_RUN JSATA1
1
GND
1 2 DDR_XDP_WAN_SMBDAT <14> PSATA_PTX_DRX_P0_C 2 1 SATA_PTX_DRX_P0 2
R501 10K_0402_5%~D C383 2 SATA_PTX_DRX_N0 A+
<14> PSATA_PTX_DRX_N0_C 1 0.01U_0402_16V7K~D 3
A-
1 2 DDR_XDP_WAN_SMBCLK C384 0.01U_0402_16V7K~D 4
R502 10K_0402_5%~D SATA_PRX_DTX_N0 GND
2 1 5
B-
<14> PSATA_PRX_DTX_N0_C
1 2 HDD_FALL_INT <14> PSATA_PRX_DTX_P0_C
C385 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6
B+
R503 100K_0402_5%~D C386 0.01U_0402_16V7K~D 7
GND
Note : Short PJP64 for SSD HDD issue PJP64
B B
8
+3.3V_RUN_HDD V33
+3.3V_RUN 1 2 9
+5V_HDD @ V33
10
PAD-OPEN1x1m V33
11
HDD_DET# GND
12
<14> HDD_DET# GND
1
13
+3.3V_RUN @ R506 GND
+5V_HDD 14
100K_0402_5%~D V5
15
+5V_HDD V5
16
V5
1
17
2
R508 FFS_INT2_Q FFS_INT2_Q GND
18
Reserved
DMN66D0LDW-7_SOT363-6~D
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
100K_0402_5%~D 19 23
GND GND
3
20 24
V12 GND
1 1 21
2
V12
Q29B
22
V12
C396
C395
5
6
2 2
DMN66D0LDW-7_SOT363-6~D
SANTA_198202-1
4
Q29A
CONN@
FFS_INT2 2
<18> FFS_INT2
1
+3.3V_RUN_HDD
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
A A
1 1
C402
C399
2 2
Compal Electronics, Inc.
Title
HDD CONNECTOR
5 4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 27 of 61
Rev
1.0
5 4 3 2 1
For ODD
D D
SP010018DCL
+5VMOD Source
JSATA2 +PWR_SRC_S +5V_ALW
1 GND
2 1 SATA_ODD_PTX_DRX_P1 2
<14> SATA_ODD_PTX_DRX_P1_C RX+
1
C407 2 1 0.01U_0402_16V7K~D SATA_ODD_PTX_DRX_N1 3 +3.3V_ALW2
<14> SATA_ODD_PTX_DRX_N1_C RX-
C406 0.01U_0402_16V7K~D 4 R507
SATA_ODD_PRX_DTX_N1 GND 470K_0402_5%~D
<14> SATA_ODD_PRX_DTX_N1_C 2 1 5 TX-
1
2
5
6
C405 2 1 0.01U_0402_16V7K~D SATA_ODD_PRX_DTX_P1 6
<14> SATA_ODD_PRX_DTX_P1_C C404 0.01U_0402_16V7K~D TX+ R509 D Q30
7
2
GND 100K_0402_5%~D G
8 2 MOD_EN 3 SI3456DDV-T1-GE3_TSOP6~D
<40> DEVICE_DET# DP S
+5V_MOD +5V_MOD 9
2
+5V
3
DMN66D0LDW-7_SOT363-6~D
10 +5V_MOD +5V_RUN
4
+5V
0.022U_0402_25V7K~D
PAD~D T88 @ TEST POINT 11 @ PJP4
MD
1000P_0402_50V7K~D
0.1U_0402_25V6K~D
Q31B
4.7M_0402_5%~D
+3.3V_RUN 2 1 12 GND GND1 14 1 1 2 2
10U_0805_10V6K~D
1 1 R1125 100K_0402_5%~D 13 15 MODC_EN# 5 1 open
GND GND2
1
R518
1 JUMP_43X79
C398
6
C397
DMN66D0LDW-7_SOT363-6~D
C400
SANTA_205902-1~D R511
C401
100K_0402_5%~D
2 2 2
Q31A
CONN@
2
2 2
<39> MODC_EN
2
1
1
C R512 C
100K_0402_5%~D
2
Pleace near ODD CONN
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD CONNECTOR
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 28 of 61
5 4 3 2 1
2 1
L77 +5V_RUN
Internal Speakers Header place close to pin27
+VDDA_AVDD
BLM21PG600SN1D_0805~D
1 2 +5V_RUN
1
0.1U_0402_25V6K~D
10U_0805_10V6K~D
0_0805_5%~D
+3.3V_RUN +3.3V_RUN_DVDD +3.3V_RUN_DVDD
1U_0603_10V7K~D
15 mils trace DVDD_IO should match 1 1 1
R1095
with HDA Bus level
C957
C956
C955
JSPK1 @ PJP60
INT_SPK_L+ L91 1 2 BLM18PG121SN1D_0603 INT_SPKL_L+ 1 1 2 +DVDD_CORE
2
1 2 2 2
1U_0603_10V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0805_10V6K~D
INT_SPK_L- L92 1 2 BLM18PG121SN1D_0603 INT_SPKR_L- 2 short 1 1 1 1
INT_SPK_R+ L93 BLM18PG121SN1D_0603 INT_SPKR_R+ 2
1 2 3
3
C952
C994
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
INT_SPK_R- L94 1 2 BLM18PG121SN1D_0603 INT_SPKR_R- 4 PAD-OPEN1x1m
4
C953
C954
10U_0805_10V6K~D
10U_0805_10V6K~D
Change L91~L94 5 2 2 2 2 U72 Place C994, C952~C957 close to Codec C957 place close to pin38
1 1 1 1
GND
C958
C959
C960
C961
part number to 6 1 27
GND DVDD_CORE AVDD1
C973
C974
C975
C976
38
2A _9/13 AVDD2 2 2 2 2
1 1 1 1 ACES_50279-0040N-001
CONN@ 3 45 +VDDA_PVDD
DVDD_IO PVDD
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D +VREFOUT
39
PVDD
2 2 2 2
Follow CONN List_0609A
1U_0603_10V7K~D
9 13 AUD_SENSE_A 1
DVDD SENSE_A
2
PESD5V0U2BT_SOT23-3~D
PESD5V0U2BT_SOT23-3~D
14 AUD_SENSE_B
SENSE_B
C1180
DE2
DE1
28 MIC_IN_L 1 2
PORTA_L MIC_IN_R <37> 2
3.3_0402_5%~D
3.3_0402_5%~D
3.3_0402_5%~D
3.3_0402_5%~D
PCH_AZ_CODEC_BITCLK 6 29 MIC_IN_R C1163 2.2U_0603_6.3V6K~D
<14> PCH_AZ_CODEC_BITCLK
2
BITCLK PORTA_R
R169
R170
R171
R172
23 +VREFOUT +VREFOUT
PCH_AZ_CODEC_SDOUT VrefOut_A
<14> PCH_AZ_CODEC_SDOUT 5 1 2
SDATA_OUT AUD_HP_OUT_L R1143 2.2K_0402_5%~D
31 AUD_HP_OUT_L <37>
PORTB_L AUD_HP_OUT_R
<14> PCH_AZ_CODEC_SYNC 10 32 AUD_HP_OUT_R <37>
SYNC PORTB_R
Place R1096 close to codec
1
1
1 2 PCH_AZ_SDIN0_R 8 40 INT_SPK_L+
B <14> PCH_AZ_CODEC_SDIN0 R1096 33_0402_5%~D SDATA_IN PORTD_+L INT_SPK_L- B
41
PCH_AZ_CODEC_RST# PORTD_-L
<14> PCH_AZ_CODEC_RST# 11
RESET# IDT review in 0624 to remove C54~C57
44 INT_SPK_R+
PORTD_+R
Place closed U72 PORTD_-R
43 INT_SPK_R-
IDT review in 0624 to add R169~R172 I2S_MCLK 1 2 I2S_MCLK_R 15
I2S_MCLK MONO_OUT
25 AUD_PC_BEEP 2 1 1 2 SPKR <14>
IDT suggest exchange location R169~R172 & C973~C976._09/13 @ R167 0_0402_5%~D C1105 0.1U_0402_25V6K~D R1119 100K_0402_5%~D
I2S_BCLK 1 2 I2S_BCLK_R 16 12 2 1 1 2
I2S_SCLK PC_BEEP BEEP <40>
@ R168 0_0402_5%~D C1106 0.1U_0402_25V6K~D R1120 100K_0402_5%~D
I2S_DO 1 2 I2S_DO_R 17 DMIC_CLK_L 1 2
I2S_DOUT DMIC_CLK0 <24>
Reserve for ESD review in 6/22 R1097 33_0402_5%~D
DMIC_CLK/GPIO 1
2 LE3 BLM18BB221SN1D_2P~D
I2S_LRCLK Place R1097 close to codec 18 4 1 2 1 2
+3.3V_RUN I2S_LRCLK DMIC_0/GPIO 2 LE4 BLM18BB221SN1D_2P~D DMIC_CLK1 <43> @ R1141 10K_0402_5%~D
46 DMIC0 <24>
I2S_DI# DMIC1/GPIO0/SPDIFOUT1
24 48 DMIC1 <43> 1 2
I2S_DIN SPDIFOUT0//GPIO3/Aux_Out @ R1142 10K_0402_5%~D
Close to U72 pin5 Close to U72 pin6
BCLK: Audio serial data bus bit clock 36 1 2 EN_I2S_NB_CODEC#
1
CAP+ R1641 0_0402_5%~D
R1084
input/output 1
C962
Place LE3/LE4 close to codec
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK
LRCK: Audio serial data bus word clock 19
No Connect Check to change LE3,LE4 to 22 ohm
4.7K_0402_5%~D 4.7U_0603_6.3V6K~D
@ input/output 20 Place C962 close to Codec
No Connect
1
35 2
2
@ R1077 @ R1076 CAP-
47_0402_5%~D 10_0402_1%~D PCH_AZ_CODEC_RST# CODEC_VREF
Place C963~C966 close to Codec
47 21
EAPD VREFFILT CODEC_CAP2
<39> AUD_NB_MUTE# 22
CAP2 CODEC_VN
34
2
+3.3V_RUN V- CODEC_VREG
1 1 1 7 37
DVSS Vreg
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
1U_0603_10V7K~D
10U_0805_10V6K~D
1 1 1 1
@C978
@C978 @ C977 @ C984 42 26
PVSS AVSS1
C963
C964
C965
C966
0.1U_0402_10V7K~D 10P_0402_50V8J~D 10P_0402_50V8J~D 1 2 30
2 2 2 R1099 10K_0402_5%~D AVSS place at AGND and DGND plane
49 33
GND AVSS 2 2 2 2
92HD93B2X5NLGXWBX8_QFN48_7X7~D 1 2
C985
+VDDA_AVDD place at AGND and DGND plane 0.1U_0402_25V6K~D
Notes:
Place closely to Pin 13. R1083
1 2
2.49K_0402_1%~D
1 2 Keep PVDD supply and speaker traces routed on the DGND plane. C986
AUD_SENSE_A 2 1 @ C981 Keep away from AGND and other analog signals 0.1U_0402_25V6K~D
0.1U_0402_25V6K~D 1 2
1
0.1U_0402_10V7K~D
1 2 place at Codec bottom side
R1086 +3.3V_RUN C987
1
20K_0402_1%~D C982 @ PJP62 @ PJP63 0.1U_0402_25V6K~D
C980
0.1U_0402_25V6K~D 1 2 1 2
1 2
2
2
R1087 @ C983 PAD-OPEN1x1m PAD-OPEN1x1m +3.3V_RUN +3.3V_RUN
100K_0402_5%~D 0.1U_0402_25V6K~D short short
6
0.1U_0402_10V7K~D
2
2
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
DA204U_SOT323-3~D
2 5 AUD_HP_NB_SENSE <37,39> 2
C1103
@ D54
@ D55
@ D56
@ D57
1
Q107A Q107B
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D @ C967 @
0.1U_0402_25V6K~D 1 U73
2 R162, R163, R164, R165,R166 CO-lay with U73
DMIC0 Camera/B 16
1
VCC
DAI_BCLK# 1 2 I2S_BCLK 2 3 DAI_BCLK#
1A 1Y# DAI_BCLK# <38>
Add for solve pop noise and detect issue DMIC1 Power/B R162 22_0402_5%~D
DAI_LRCK# 1 2 I2S_LRCLK 4 5 DAI_LRCK#
R163 0_0402_5%~D 2A 2Y# DAI_LRCK# <38>
DAI_DO# 1 2 I2S_DO 6 7 DAI_DO#
A 3A 3Y# DAI_DO# <38> A
R164 0_0402_5%~D
Resistor SENSE_A SENSE_B DAI_12MHZ# 1 2 I2S_MCLK 10 9 DAI_12MHZ#
R165 22_0402_5%~D 4A 4Y# DAI_12MHZ# <38>
Place closely to Pin 14 +VDDA_AVDD 12 11
R1078 5A 5Y# +3.3V_RUN
39.2K PORT A PORT E
2.49K_0402_1%~D 14 13 I2S_DI# 1 2 DAI_DI
AUD_SENSE_B 6A 6Y# R166 0_0402_5%~D
2 1
20K PORT B PORT F EN_I2S_NB_CODEC# 1
<39> EN_I2S_NB_CODEC# OE1#
2
1000P_0402_50V7K~D
1 2 1 15 8
@ R1540 OE2# GND @ D58
1
+3.3V_RUN
C979
10K NA DMIC0 1K_0402_1%~D DA204U_SOT323-3~D
R1079 R1080 +3.3V_RUN CD74HC366M96_SO16~D
39.2K_0402_1%~D 20K_0402_1%~D 2
1
5.11K SPDIFOUT0 SPDIFOUT1 (DMIC1)
1
1
R1081
2
100K_0402_5%~D R1082 DAI_DI
100K_0402_5%~D DAI_DI <38>
2.49K Pull-up to AVDD
2
PORT A External MIC
<39> DOCK_HP_DET 2 5 DOCK_MIC_DET <39> DELL CONFIDENTIAL/PROPRIETARY
Q106A Q106B PORT B HeadPhone Out Compal Electronics, Inc.
1
DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
PORT C Dock Audio
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Azalia (HD) Codec
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
PORT D Internal SPK LA-7902P
Date: Wednesday, March 07, 2012 Sheet 29 of 61
2
WWW.AliSaler.Com 1
5 4 3 2 1
UL1A
BCM5761
CL4 2 1 0.1U_0402_10V7K~D PCIE_PRX_GLANTX_P7_C A10 K2 LAN_TX0+
<15> PCIE_PRX_GLANTX_P7 PCIE_TXDP TRD0+ +3.3V_LAN
K1 LAN_TX0-
CL1 PCIE_PRX_GLANTX_N7_C TRD0-
<15> PCIE_PRX_GLANTX_N7 2 1 0.1U_0402_10V7K~D B10 PCIE_TXDN
J2 LAN_TX1+
CL2 PCIE_PTX_GLANRX_P7_C TRD1+ LAN_TX1-
<15> PCIE_PTX_GLANRX_P7 1 2 0.1U_0402_10V7K~D A6 PCIE_RXDP TRD1- J1
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
Media
1
CL3 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_N7_C B6 H2 LAN_TX2+
<15> PCIE_PTX_GLANRX_N7 PCIE_RXDN TRD2+
@
PCI-E
H1 LAN_TX2-
TRD2-
2 RL15
2 RL16
2 RL17
2 RL18
2 RL19
RL20
CLK_PCIE_LAN A8
<15> CLK_PCIE_LAN REFCLK+ LAN_TX3+
G2
CLK_PCIE_LAN# TRD3+ LAN_TX3-
<15> CLK_PCIE_LAN# B8 G1
2
REFCLK- TRD3-
D RL1 NV_STRAP1 D
+3.3V_RUN 1 2 10K_0402_5%~D 10K_0402_5%~D 2 1 RL2 +3.3V_LAN
@ RL3 1 2 0_0402_5%~D LANCLK_REQ#_R J9 J8 ENERGYDET 0_0402_5%~D 2 1 RL4 @ NV_STRAP0
<15> LANCLK_REQ# CLKREQ# ENERGYDET LOM_ENERGY_DET <39>
LAN_SO
PLTRST_LAN# J10 G7 LOM_VAUXPRSNT RL5 2 1 1K_0402_1%~D LAN_SI
<17> PLTRST_LAN# PERST# VAUXPRSNT +3.3V_LAN
LAN_CS#
<34,35,40> PCIE_WAKE# PCIE_WAKE# K7 B1 LOM_VMAINPRSNT RL6 2 1 1K_0402_1%~D LAN_SCLK
WAKE# VMAINPRSNT +3.3V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D
F10 LOM_LOW_PWR_R @ RL7 2 1 0_0402_5%~D
LOW_PWR LOM_LOW_PWR <39>
1
@
@
LAN_SMB_CLK H5
SMB_CLK
2 RL24
2 RL25
2 RL26
2 RL27
LAN_SMB_DATA J6 E5 GPIO1 @ RL8 2 1 1K_0402_1%~D
+3.3V_LAN SMB_DATA GPIO1/SERIAL_DI +3.3V_LAN
SMBUS
LAN_APE_SMB_CLK0 L10 J7 GPIO2 @ RL9 2 1 1K_0402_1%~D
LAN_APE_SMB_DATA0 APE_SMB_CLK0 GPIO2/SERIAL_DO
L9 APE_SMB_DATA0
D2 GPIO0 @ TL1 PAD~D
Misc
QL2A LAN_APE_SMB_CLK1 GPIO0
L8 APE_SMB_CLK1
2
RL50 1 2 0_0402_5%~D DMN66D0LDW-7_SOT363-6~D LAN_APE_SMB_DATA1 L7 RL12 2 1 4.7K_0402_5%~D
<15,40> SIO_LAN_SMBCLK APE_SMB_DATA1 +3.3V_LAN
L3 APE_GPIO0 @ TL2 PAD~D
@ RL49 1 LAN_APE_SMB_CLK0 APE_GPIO0 LOM_SMB_ALERT#
<15,40> SML1_SMBCLK 2 0_0402_5%~D 6 1 APE_GPIO1 L4 LOM_SMB_ALERT# <39>
L5 APE_GPIO2 @ TL3 PAD~D +3.3V_LAN
APE_GPIO2
USB
1 2 F11 L6 APE_GPIO3 @ TL4 PAD~D
RL51 0_0402_5%~D @RL10
@ RL10 0_0402_5%~D HUSB_DP APE_GPIO3 APE_GPIO5 @ TL5 PAD~D LAN_SMB_CLK
E11 HUSB_DN APE_GPIO5 L2 2 1
5
1 2 L1 APE_GPIO6 @ TL6 PAD~D 2.2K_0402_5%~D RL28
<15,40> SIO_LAN_SMBDATA APE_GPIO6 LAN_SMB_DATA 2 1
1 2 3 4 LAN_APE_SMB_DATA0 C1 APE_GPIO4 RL13 1 @ 2 0_0402_5%~D 2.2K_0402_5%~D RL29
<15,40> SML1_SMBDATA NV_STRAP1 APE_GPIO4
C10 NV_STRAP1
@ RL48 0_0402_5%~D QL2B NV_STRAP0 D10 LAN_APE_SMB_CLK0 2 1
NV_STRAP0
NVRAM
1 2 DMN66D0LDW-7_SOT363-6~D B2 LAN_PWR_DOWN RL14 1 2 4.7K_0402_5%~D 2.2K_0402_5%~D RL30
@ RL11 0_0402_5%~D LAN_SO PWR_DOWN LAN_APE_SMB_DATA0
G5 SO
2 1
LAN_SI J3 2.2K_0402_5%~D RL31
LAN_CS# SI
K3 CS#
C +3.3V_LAN LAN_SCLK J4 G10 LAN_TMS @ TL7 PAD~D LAN_APE_SMB_CLK1 2 1 C
+3.3V_LAN SCLK TMS LAN_TDO @ TL8 PAD~D 2.2K_0402_5%~D RL32
TDO K6
0.1U_0402_25V6K~D
F9 LAN_TDI @ TL9 PAD~D LAN_APE_SMB_DATA1 2 1
TEST
UL2 TDI LAN_TCK @ TL10 PAD~D 2.2K_0402_5%~D RL33
TCK H7
8 1 LAN_CS# 1 LOM_SPD10LED_GRN# K5 K9 LAN_TRST# @ TL11 PAD~D
VCC S# LAN_SI LOM_SPD100LED_ORG# LINKLED# TRST#
7 RESET# Q 2 CL7 place J5 SPD100LED# +3.3V_LAN
LED
CL7
LAN_SCLK 6 3 PAD~D TL12 @ K4 E2 GPHY_TVCOI RL21 1 2 4.7K_0402_5%~D
LAN_SO C W# close to UL2 SPD1000LED# GPHY_TVCOI
5 4
D VSS 2 LOM_ACTLED_YEL# @
H6
TRAFFICLED#
1
M25PE80-VMN6TP_SO8N8
R549
10K_0402_5%~D
Clock
RL22 1 2 200_0402_1%~D XTALO A4
Bias
XTALO RDAC RL23 1
F1 2 1.2K_0402_1%~D
2
+3.3V_LAN YL1 XTALI RDAC LOM_LOW_PWR_R
B4
@ 25MHZ_10PF_X3G025000FA1H~D XTALI
1
1 IN
UL3 OUT 3 R557
12P_0402_50V8J~D
12P_0402_50V8J~D
8 1 LAN_CS# 2 4 10K_0402_5%~D
VCC S# LAN_SI GND GND BCM5761B0KFBGH_FBGA121~D @
7 2 1 1
LAN_SCLK RESET# Q
6 3
2
C W#
CL5
CL6
LAN_SO 5 4 @
D VSS
M25PE80-VMW6TP_SO8W8 2 2 +3.3V_LAN C478
0.1U_0402_10V7K~D
co-lay with UL2 1 2
+3.3V_M
5
LOM_SPD100LED_ORG# 1
P
B
+3.3V_LAN 4
O WLAN_LAN_DISB# <39>
2
LOM_SPD10LED_GRN# 2
A
G
B @ R563 B
C472
1
C473
1
C474
1 LAN ANALOG TC7SH08FU_SSOP5~D 0_1206_5%~D
3
U15
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D SWITCH @
1
2 2 2 Q34
39
30
21
14
8
4
1
U32 +3.3V_ALW +3.3V_LAN
SI3456DDV-T1-GE3_TSOP6~D
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW_LAN_TX0+ +PWR_SRC_S
B0+ SW_LAN_TX0+ <37>
D
37 SW_LAN_TX0- 6
S
B0- SW_LAN_TX0- <37>
LAN_TX0+ 1 2 LAN_TX0+R 2 +3.3V_ALW2 5 4
A0+
1
L30 0_0603_5%~D 34 SW_LAN_TX1+ 2
B1+ SW_LAN_TX1+ <37>
10U_0603_6.3V6M~D
0.1U_0402_10V7K~D
LAN_TX0- 1 2 LAN_TX0-R 3 33 SW_LAN_TX1- R564 1 1 1
A0- B1- SW_LAN_TX1- <37>
L31 0_0603_5%~D 100K_0402_5%~D
C475
C476
29 SW_LAN_TX2+ TO
3
B2+ SW_LAN_TX2+ <37>
1
LAN_TX1+ 1 2 LAN_TX1+R 6 28 SW_LAN_TX2-
2
L33 0_0603_5%~D A1+ B2- SW_LAN_TX2- <37> DOCK R565 ENAB_3VLAN 2 2
LAN_TX1- 1 2 LAN_TX1-R 7 25 SW_LAN_TX3+ 100K_0402_5%~D
A1- B3+ SW_LAN_TX3+ <37>
3
DMN66D0LDW-7_SOT363-6~D
1M_0402_5%~D
2200P_0402_50V7K~D
L32 0_0603_5%~D 24 SW_LAN_TX3-
B3- SW_LAN_TX3- <37>
1
2
Q35B
R1638
LAN_TX2+ 1 2 LAN_TX2+R 9 17 LAN_ACTLED_YEL# 1
A2+ LEDB0 LAN_ACTLED_YEL# <37>
L34 0_0603_5%~D 18 LED_100_ORG# 5
LEDB1 LED_100_ORG# <37>
C477
LAN_TX2- 1 2 LAN_TX2-R 10 41 LED_10_GRN#
A2- LEDB2 LED_10_GRN# <37>
6
DMN66D0LDW-7_SOT363-6~D
L35 0_0603_5%~D @RL46
@RL46 1 2 0_0402_5%~D
<40> AUX_ON
2
36 DOCK_LOM_TRD0+ 2
C0+ DOCK_LOM_TRD0+ <38>
Q35A
LAN_TX3+ 1 2 LAN_TX3+R 11 35 DOCK_LOM_TRD0-
A3+ C0- DOCK_LOM_TRD0- <38>
L36 0_0603_5%~D 1 2 2
LAN_TX3- LAN_TX3-R DOCK_LOM_TRD1+ <16,39> SIO_SLP_LAN#
1 2 12 32 @ RL47 0_0402_5%~D
A3- C1+ DOCK_LOM_TRD1- DOCK_LOM_TRD1+ <38>
L37 0_0603_5%~D 31 DOCK_LOM_TRD1- <38>
1
C1-
DOCKED 13 27 DOCK_LOM_TRD2+
<39> DOCKED SEL C2+ DOCK_LOM_TRD2- DOCK_LOM_TRD2+ <38>
26
C2- DOCK_LOM_TRD2- <38>
A LOM_ACTLED_YEL# DOCK_LOM_TRD3+ A
15 LEDA0 C3+ 23 DOCK_LOM_TRD3+ <38>
LOM_SPD100LED_ORG# 16 22 DOCK_LOM_TRD3-
LOM_SPD10LED_GRN# LEDA1 C3- DOCK_LOM_TRD3- <38>
Layout Notice : Place as 42 LEDA2
19 DOCK_LOM_ACTLED_YEL#
close PI3L500 as possible LEDC0 DOCK_LOM_SPD100LED_ORG# DOCK_LOM_ACTLED_YEL# <38>
5 20
PD LEDC1
LEDC2 40 DOCK_LOM_SPD10LED_GRN# DOCK_LOM_SPD100LED_ORG# <38>
DOCK_LOM_SPD10LED_GRN# <38>
DELL CONFIDENTIAL/PROPRIETARY
43 PAD_GND
1: TO DOCK
Compal Electronics, Inc.
FROM NIC DOCKED PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
0: TO RJ45 PI3L720ZHEX_TQFN42_9X3P5~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LAN (1/2) BCM5761
5
Change P/N to TI (SA00003LD0L) 12/13
4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 30 of 61
Rev
1.0
5 4 3 2 1
+3.3V_LAN
+3.3V_LAN_VDDIO
1 1
D D
CL8 CL9 UL1B
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
2 2 BCM5761
H8 H9
+1.2V_LAN VDDC_H08 VSS_H09
H4
+1.2V_LAN VSS_H04
G9 G11
LL1 VDDC_G09 VSS_G11
G6
+1.2V_LAN_PCIE_SDSVDDL VSS_G06
1 2 G8
VDDC_G08 VSS_G04
G4
BLM18AG601SN1D_0603~D 1 1 F8
VSS_F08
E10 F7
CL10 CL11 VDDC_E10 VSS_F07
VSS_F06 F6
Power
Digital
4.7U_0603_6.3V6K~D 0.1U_0402_25V6K~D C9 E8
2 2 VDDC_C09 VSS_E08
E7
GND
VSS_E07
VSS_E06 E6
2 1 LAN_VDDP F4 E4
+3.3V_LAN CL12 1U_0603_10V7K~D VDDP VSS_E04
VSS_D04 D4
LL2 D3
+3.3V_LAN_XTALVDDH +3.3V_LAN_VDDIO VSS_D03
1 2 K8 VDDIO_K08 VSS_C06 C6
BLM18AG601SN1D_0603~D 1 B11
VSS_B11
H10 VDDIO_H10 VSS_B07 B7
CL13 A11
0.1U_0402_25V6K~D VSS_A11
C2 VDDIO_C02 VSS_A09 A9
2 A7
VSS_A07
A3 VDDIO_A03 VSS_A02 A2
+3.3V_LAN
LL3 +1.2V_LAN_PCIE_SDSVDDL B9
+3.3V_LAN_BIASVDDH PCIE_SDSVDDL LAN_TP_D07 RL34 10K_0402_5%~D
1 2 TP_D07 D7 2 1
BLM18AG601SN1D_0603~D D6 LAN_TP_D06 RL35 2 1 10K_0402_5%~D +3.3V_LAN
1 TP_D06
+3.3V_LAN_XTALVDDH A5 D5 LAN_TP_D05 RL36 2 1 10K_0402_5%~D
CL14 XTALVDDH TP_D05 LAN_TP_C05 RL37 10K_0402_5%~D
TP_C05 C5 2 1
C 0.1U_0402_25V6K~D LAN_TP_F05 RL38 10K_0402_5%~D C
TP_F05 F5 2 1
2 C3 LAN_TP_C03 RL39 2 1 10K_0402_5%~D
TP_C03
Power
Bias
B5 LAN_TP_B05 RL40 2 1 10K_0402_5%~D
+3.3V_LAN_BIASVDDH TP_B05
F2 BIASVDDH
+1.2V_LAN
LL4 C4
+1.2V_LAN_AVDDL NC_C04 LAN_NC_L11 @ TL13 PAD~D
1 2 L11
BLM18AG601SN1D_0603~D NC_L11 LAN_NC_K11 @ TL14 PAD~D
1 1 K11
NC_K11 LAN_NC_J11 @ TL15 PAD~D
J11
Others
CL15 CL16 +1.2V_LAN_AVDDL NC_J11 LAN_NC_H11 @ TL16 PAD~D
E3 H11
AVDDL_E03 NC_H11
Power
Analog
4.7U_0603_6.3V6K~D 0.1U_0402_25V6K~D
2 2 F3 @
AVDDL_F03 LAN_NC_K10 RL41 1
NC_K10
K10 2 4.7K_0402_5%~D
D11
+3.3V_LAN +3.3V_LAN_AVDDH DC_D11
G3 B3
LL5 AVDDH_G03 NC_B03 +3.3V_LAN
1 2 +3.3V_LAN_AVDDH H3 @
BLM18AG601SN1D_0603~D AVDDH_H03 LAN_DC_D09 RL42 2
1 1 D9 1 4.7K_0402_5%~D
DC_D09
CL17 CL18 E9
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D DC_E09
C8
2 2 DC_C08
+1.2V_LAN_PCIE_PLLVDDL C7 D8 LAN_TP_D08 RL43 1 2 4.7K_0402_5%~D
PCIE_PLLVDDL TP_D08
+1.2V_LAN
Power
PLL
LL6 +3.3V_LAN
+1.2V_LAN_PCIE_PLLVDDL +1.2V_LAN_GPHY_PLLVDDL
Regulator
1 2 E1
BLM18AG601SN1D_0603~D GPHY_PLLVDDL LAN_REGCTL12
D1
Voltage
1 1 REGCTL12
4.7U_0603_6.3V6K~D
CL19 CL20 +1.2V_LAN
1.5_1206_5%
4.7U_0603_6.3V6K~D 0.1U_0402_25V6K~D +1.2V_LAN_PLLVDDL C11 A1 LAN_REGOUT25 1 2 LAN_VDDP 1
2 2 USB_PLLVDDL REGOUT25 RL44 0_0402_5%~D
B B
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
RL45
CL21
Cvddp must have 1 1 1 1
LL7 ESR < 1 Ohm. 2
2
1 2 +1.2V_LAN_GPHY_PLLVDDL BCM5761B0KFBGH_FBGA121~D
CL22
CL23
CL24
CL25
BLM18AG601SN1D_0603~D 1 1
QL1 2 2 2 2
3
CL26 CL27 PBSS5540Z_SOT223-3~D
4.7U_0603_6.3V6K~D 0.1U_0402_25V6K~D
2 2 LAN_REGCTL12 1
0.047U_0402_16V4Z~D
LL8 @ 1
2
4
1 2 +1.2V_LAN_PLLVDDL
10U_0805_10V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
BLM18AG601SN1D_0603~D 1 1 CL29
2 1 1 1 1 1
CL30 CL28
4.7U_0603_6.3V6K~D 0.1U_0402_25V6K~D
2 2
CL31
CL32
CL33
CL34
CL35
2 2 2 2 2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LAN (2/2) BCM5761
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 31 of 61
Rev
1.0
5 4 3 2 1
short
D +3.3V_RUN +3.3V_RUN_TPM D
PJP61 +3.3V_SB3V
1 2
@
PAD-OPEN1x1m
0.1U_0402_25V6K~D
4700P_0402_25V7K~D
+3.3V_RUN_TPM
1@ C44
1@ C45
+3.3V_SB3V +3.3V_RUN_TPM
1 1
ATMEL TPM for E4
1 2
2 2
2200P_0402_50V7K~D
2200P_0402_50V7K~D
2200P_0402_50V7K~D
0.1U_0402_25V6K~D
1@ R873 0_0402_5%~D Change CONN to pitch 1.0 _0815
5@ C550
5@ C551
5@ C552
5@ C553
1@ U39 1 1 1 1
+3.3V_RUN_TPM
VCC_0 10
5 19 +3.3V_RUN
SB3V VCC_1 2 2 2 2 JBIO1
1 2 VCC_2 24
@R1663
@ R1663 10K_0402_5%~D 1 1
0.1U_0402_25V6K~D
1 2 2 2
R1662 0_0402_5%~D USBP13_R_D- 3
5@ USBP13_R_D+ 3
1 4 4
C51
1 2 SP_TPM_LPC_EN_R 28 12 NC_12 5 7
<39> SP_TPM_LPC_EN LPCPD# V_BAT JETWAY_CLK14M 5 G1
@ D87 RB751S40T1_SOD523-2~D 13 6 8
NBO_13 JETWAY_CLK14M <15> 6 G2
3
LPC_LAD0 26 14 NC_P 1 2
<14,34,39,40> LPC_LAD0 LAD0 NBO_14 2
PESD5V0U2BT_SOT23-3~D
D73
LPC_LAD1 23 C554 1U_0402_6.3V6K~D PS_HPF10052-061000R
<14,34,39,40> LPC_LAD1 LPC_LAD2 LAD1
20 4@ CONN@
<14,34,39,40> LPC_LAD2 LPC_LAD3 LAD2
<14,34,39,40> LPC_LAD3 17 LAD3
6 NC_6
GPIO6
CLK_PCI_TPM_TCM 21 9 TCM_BA0
<15> CLK_PCI_TPM_TCM LPC_LFRAME# LCLK TESTBI
<14,34,39,40> LPC_LFRAME# 22 LFRAME# TESTI 8
C PCH_PLTRST#_EC +3.3V_RUN_TPM C
<17,34,35,39,40> PCH_PLTRST#_EC 16
1
IRQ_SERIRQ LRESET#
<14,39,40> IRQ_SERIRQ 27 SERIRQ
CLKRUN# 15
<16,39,40> CLKRUN# CLKRUN# PP
NC_7 7 1 2
@ R656 4.7K_0402_5%~D
1 ATEST_1 GND_4 4
2 ATEST_2 GND_11 11
CLK_PCI_TPM_TCM TCM_BA1 3 18
ATEST_3 GND_18
25
GND_25
1
Change CIS symbol_ 12/07
@ RE5 AT97SC3204-X2A18-AB_TSSOP28
33_0402_5%~D
L52
4 3 USBP13_R_D-
<17> USBP13-
2
4 3
1
@ 1 2 USBP13_R_D+
<17> USBP13+ 1 2
CE3
2
27P_0402_50V8J~D Co-lay U37 and U39 OCF2012181YZF_4P
1 2
@ R741 0_0402_5%~D
LPC layout: Place TCM first and then end LPC with TPM.
1 2
@ R742 0_0402_5%~D
China TCM: NationZ & Jetway co-lay
+3.3V_RUN_TPM
B LOW:Power Down Mode B
High:Working Mode 4@ U37
10
VDD_0
19
VDD_1
24
VDD_2
SP_TPM_LPC_EN_R 28
+3.3V_RUN_TPM LPC_LAD0 LPCPD#
26 11
LPC_LAD1 LAD0 GND_11
23 18
LPC_LAD2 LAD1 GND_18
20 25
LPC_LAD3 LAD2 GND_25
17 4
LAD3 GND_4
1
+3.3V_SB3V
@ R657 @ R658
10K_0402_5%~D 10K_0402_5%~D
CLK_PCI_TPM_TCM 21 5 JETWAY_CLK14M
LPC_LFRAME# LCLK NC_5 NC_12
22 12
2
LFRAME# NC_12
1
PCH_PLTRST#_EC 16 13 JETWAY_CLK14M
TCM_BA0 IRQ_SERIRQ LRESET# NC_13 @
27
TCM_BA1 CLKRUN# SERIRQ RE6
15 1
PP CLKRUN# NC_1 33_0402_5%~D
7 2
TCM_BA1 PP NC_2 NC_6
3 6
2
TCM_BA0 BA_1 NC_6
9 8
BA_0 NC_8
1
14 NC_P 1
5@ R659 5@ R660 NC_P @
10K_0402_5%~D 10K_0402_5%~D CE4
27P_0402_50V8J~D
2
2
SSX44-B-D-T1_TSSOP28~D
A A
Compal Electronics, Inc.
Title
TPM/TCM/BIO Conn
5 4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 32 of 61
Rev
1.0
A B C D E
1 1
Vendor review in 6/22 and change C576 to 0.01uF
+3.3V_RUN
L45
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
BLM18PG471SN1D_2P~D
4.7U_0603_6.3V6K~D
0.01U_0402_16V7K~D
1 2 1 1
+1.5V_RUN
0.1U_0402_25V6K~D
1 1 1
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
C559
C560
L47
C577
C576
C575
1 2 1 1 2 2
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
BLM18BD601SN1D_0603~D
2 2 2
C563
C564
1 1
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
U38
2 2
C561
C562
1 1
+3.3VDDH 16 10 +OZ_DVDD
2 2 3.3VDDH DVDD +3.3V_RUN_CARD
C565
C566
+VDDH_SD 9 8 +OZ_AVDD
+PE_VDDH VDDH AVDD
1 2 32 PE_VDDH
L44 BLM18BD601SN1D_0603~D 2 2
2 1 17 +SKT_VCC
+PE_VDDH C578 4.7U_0603_6.3V6K~D SKT_VCC
MMI_VCC_OUT 15
0.1U_0402_25V6K~D
0.01U_0402_16V7K~D
<15> CLK_PCIE_MMI 2 PE_REFCLKP
1 1 1 28 SD/MMCDAT1_R R663 1 2 33_0402_5%~D SD/MMCDAT1
<15> CLK_PCIE_MMI# PE_REFCLKM SD_D1
26 SD/MMCDAT2_R R664 1 2 33_0402_5%~D SD/MMCDAT2
SD_D2
C573
C574
29 SD/MMCDAT0_R R665 1 2 33_0402_5%~D SD/MMCDAT0
C569 0.1U_0402_10V7K~D PCIE_PRX_MMITX_P6_C MMI_D0
1 2 6 PE_TXP MS_D1 27
2 2 <15> PCIE_PRX_MMITX_P6 C571 0.1U_0402_10V7K~D PCIE_PRX_MMITX_N6_C
1 2 7 PE_TXM MS_D2 25
<15> PCIE_PRX_MMITX_N6 C567 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_P6_C SD/MMCDAT3_R R668 33_0402_5%~D SD/MMCDAT3
<15> PCIE_PTX_MMIRX_P6 1 2 5 24 1 2
C568 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_N6_C PE_RXP MMI_D3 SD/MMCDAT4_R R669 33_0402_5%~D SD/MMCDAT4
<15> PCIE_PTX_MMIRX_N6 1 2 4 PE_RXM MMI_D4 23 1 2
1 2 3 22 SD/MMCDAT5_R R670 1 2 33_0402_5%~D SD/MMCDAT5
2 R677 191_0402_1%~D PE_REXT MMI_D5 SD/MMCDAT6_R R672 33_0402_5%~D SD/MMCDAT6 2
MMI_D6 21 1 2
33 20 SD/MMCDAT7_R R673 1 2 33_0402_5%~D SD/MMCDAT7
GPAD MMI_D7
13 PE_RST# MS_CD# 11
place close to pin U38.32 19 SD/MMCCMD_R R674 1 2 33_0402_5%~D SD/MMCCMD
<17> PLTRST_MMI# SD_CMD/MS_BS SD/MMCCLK_R SD/MMC_CLK
MMI_CLK 18 1 2
14 12 SD/MMCCD# R676 10_0402_5%~D
MULTI-IO1 SD_CD# SDWP
31 30
<15> MMICLK_REQ# MULTI-IO2 SD_WPI
OZ600FJ0LN_QFN32_5X5~D
Note: The trace need to route as
daisy-chain and the trace of SD signals
need to route as short as possible
SP071106270
JSD1
Vendor review in 6/22 and reserve for SD3.0 UHS-I 200MHz transfer +3.3V_RUN_CARD
3 SD/MMCDAT3 3
14
SD/MMCCMD DAT3/SD1
12
CMD/SD2
EMI request 10
9
VSS1/SD3
SD/MMCDAT0 SD/MMCDAT1 SD/MMCDAT2 SD/MMCDAT3 SD/MMCCMD SD/MMC_CLK VCC/SD4
8
CLK/SD5
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
SD/MMC_CLK 6
GND/VSSS2/SD6
1
10K_0402_5%~D
1 1 SD/MMCDAT0 4
SD/MMCDAT1 DAT0/SD7
1 1 1 1 1 3
DAT1/SD8
C570
C572
R826
@ C775 @C776
@ C776 @ C777 @ C779 @ C780 SD/MMCDAT2 15
DAT2/SD9
2
10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D @ RE678 2 2 SD/MMCDAT4 13
2
2 2 2 2 2 SD/MMCDAT5 DAT4/MMC10
33_0402_5%~D 11
SD/MMCDAT6 DAT5/MMC11
7
SD/MMCDAT7 DAT6/MMC12
5
1
DAT7/MMC13
1 19
@ CE757 CD_WP_SW/GND
20
CD_WP_SW/GND
10P_0402_50V8J~D
2 SD/MMCCD# 17
SDWP CD_SW/SD
18
SD/MMCCD# WP_SW/SD
2
SDWP CD_SW_TAISOL/SD
1
WP/SW_TAISOL/SD
Place closed R676 pin 2 16
GND_SW
T-SOL_156-4000000601_NR
CONN@
4
only for MMC/SD 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader OZ600FJ0
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 33 of 61
A B C D E
5 4 3 2 1
+3.3V_PCIE_WWAN +3.3V_ALW_PCH
+3.3V_RUN 1
@ R693
2
0_0402_5%~D
Mini WLAN/WIMAX H=6.7 PCIE_MCARD1_DET# 1
R692
2
100K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
USB_MCARD2_DET# 2 1
1
@ R1159
@ R1160
R694 100K_0402_5%~D 1 2 WLAN_RADIO_DIS#_R USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET#
<39> WLAN_RADIO_DIS#
@ R698 0_0402_5%~D
D31 RB751S40T1_SOD523-2~D
Follow CONN List_0609A +3.3V_RUN
2
2 1 WWAN_SMBCLK +3.3V_WLAN +3.3V_WLAN PCIE_MCARD1_DET# 1 2
<7,12,13,14,15,27> DDR_XDP_WAN_SMBCLK
@ R1157 0_0402_5%~D @ R699 100K_0402_5%~D
2 1 WWAN_SMBDAT JMINI2 +1.5V_RUN USB_MCARD1_DET# 1 2
<7,12,13,14,15,27> DDR_XDP_WAN_SMBDAT
@ R1158 0_0402_5%~D <30,35,40> PCIE_WAKE# PCIE_WAKE# 1 2 R701 100K_0402_5%~D
D COEX2_WLAN_ACTIVE 1 2 D
<41> COEX2_WLAN_ACTIVE 1 2 3
3 4
4
COEX1_BT_ACTIVE @ R700 1 20_0402_5%~D 5 6
Mini WWAN/GPS/LTE/UWB H=6.7 <41> COEX1_BT_ACTIVE
<15> MINI2CLK_REQ#
@ R702 0_0402_5%~D 7
9
5
7
9
6
8
10
8
10 1 2
Follow CONN List_0609A <15> CLK_PCIE_MINI2# 11
11 12
12
13 14 MSDATA C595 4700P_0402_25V7K~D
<15> CLK_PCIE_MINI2 13 14
+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN 15 16
15 16 HOST_DEBUG_TX <40>
JMINI1 17 18
PCIE_WAKE# <40> HOST_DEBUG_RX 17 18 WLAN_RADIO_DIS#_R
1 2 19 20
1 2 <40> MSCLK 19 20
3 4 21 22 2 1 PCH_PLTRST#_EC
3 4 PCIE_PRX_WLANTX_N2 21 22 @ R703 0_0402_5%~D
5 6 +1.5V_RUN_WWAN 23 24
MINI1CLK_REQ# 5 6 <15> PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 23 24
7 7 8 8 +SIM_PWR 25 25 26 26
<15> MINI1CLK_REQ# UIM_DATA <15> PCIE_PRX_WLANTX_P2
9 9 10 10 UIM_DATA <37> 27 27 28 28
CLK_PCIE_MINI1# 11 12 UIM_CLK C596 0.1U_0402_10V7K~D 29 30
<15> CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12 UIM_RESET UIM_CLK <37> 29 30
13 13 14 14 UIM_RESET <37> <15> PCIE_PTX_WLANRX_N2 1 2 PCIE_PTX_WLANRX_N2_C 31 31 32 32
<15> CLK_PCIE_MINI1 UIM_VPP
15 15 16 16 UIM_VPP <37> <15> PCIE_PTX_WLANRX_P2 1 2 PCIE_PTX_WLANRX_P2_C 33 33 34 34
17 18 C598 0.1U_0402_10V7K~D 35 36 USBP4-
17 18 PCIE_MCARD1_DET# 35 36 USBP4+ USBP4- <17>
19 19 20 20 WWAN_RADIO_DIS# <39> 37 37 38 38 USBP4+ <17>
<18> PCIE_MCARD1_DET# USB_MCARD1_DET#
21 21 22 22 1 2 PCH_PLTRST#_EC <17,32,35,39,40> 39 39 40 40 USB_MCARD1_DET# <14,18>
PCIE_PRX_WANTX_N1 23 24 @ R704 0_0402_5%~D 41 42 WIMAX_LED#
<15> PCIE_PRX_WANTX_N1 PCIE_PRX_WANTX_P1 23 24 41 42 WLAN_LED#
<15> PCIE_PRX_WANTX_P1 25 25 26 26 43 43 44 44
27 27 28 28 <15> PCH_CL_CLK1 45 45 46 46
C597 0.1U_0402_10V7K~D 29 30 WWAN_SMBCLK 47 48 1 2 MSDATA
PCIE_PTX_WANRX_N1_C 29 30 WWAN_SMBDAT <15> PCH_CL_DATA1 47 48 MSDATA <40>
1 2 31 32 1 2 49 50 @ R706 0_0402_5%~D
<15> PCIE_PTX_WANRX_N1 PCIE_PTX_WANRX_P1_C 31 32 <15> PCH_CL_RST1# 49 50
1 2 33 34 @ R707 0_0402_5%~D 51 52
<15> PCIE_PTX_WANRX_P1 33 34 51 52
C599 0.1U_0402_10V7K~D USBP5- WIMAX_LED# STUDY FOR DEBUG
1 2 PCIE_MCARD2_DET#_R
35
37
35 36 36
38 USBP5+ USBP5- <17> check 53 54 +3.3V_WLAN
<17> PCIE_MCARD2_DET# 37 38 USB_MCARD2_DET# USBP5+ <17> GNDGND
@ R725 0_0402_5%~D 39 40
39 40 LED_WWAN_OUT# USB_MCARD2_DET# <18>
41 41 42 42 ACES_51711-0520W-001
43 43 44 44
+1.5V_RUN
100K_0402_5%~D
100K_0402_5%~D
45 46 +3.3V_WLAN CONN@
45 46
2
47 47 48 48
C
R718
R705
C
49 49 50 50
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
51 52 COEX2_WLAN_ACTIVE
<39> HW_GPS_DISABLE2# 51 52
5
DMN66D0LDW-7_SOT363-6~D
@ C603
53 54 USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET# 1 1 1 1 1 1 2 2 1
1
GNDGND @ R697 0_0402_5%~D
C601
C602
C604
C605
C606
C607
C608
@ C600 WIMAX_LED# 4 3 WIRELESS_LED#
ACES_51711-0520W-001
33P_0402_50V8J~D
CONN@ +3.3V_PCIE_WWAN 2 2 2 2 2 2 1 1 2 Q124B
2
DMN66D0LDW-7_SOT363-6~D
WLAN_LED# 1 6
100K_0402_5%~D
Q124A
2
R719
+3.3V_PCIE_WWAN
1/2 Minicard Pink Pather/60GHz Card H=6.7
2
G
1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
22U_0805_6.3V6M~D
33P_0402_50V8J~D
330U_6.3V_M
330U_6.3V_M
1 1 LED_WWAN_OUT# 3 1 Follow CONN List_0609A
WIRELESS_LED# <39,43> USB_MCARD3_DET#
@ 2 PCIE_MCARD3_DET#
S
1 1 1 1 1 1
C615
C1176
+ + @R708
@ R708 0_0402_5%~D
C610
C611
C612
C613
C614
Q77 +3.3V_PCIE_FLASH
SSM3K7002FU_SC70-3~D +3.3V_PCIE_FLASH
2 2 2 2 2 2 2
JMINI3
PCIE_WAKE# 1 2
COEX2_WLAN_ACTIVE 1 2
1 2 3
3 4
4
Primary Power Aux Power @ R709 0_0402_5%~D 5
5 6
6 +1.5V_RUN
PWR Voltage MINI3CLK_REQ# 7 8 LPC_LFRAME#
<15> MINI3CLK_REQ# 7 8 LPC_LAD3 LPC_LFRAME# <14,32,39,40>
9 10
Rail Tolerance Peak Normal Normal CLK_PCIE_MINI3# 11
9 10
12 LPC_LAD2
LPC_LAD3 <14,32,39,40>
B <15> CLK_PCIE_MINI3# 11 12 LPC_LAD2 <14,32,39,40> B
CLK_PCIE_MINI3 13 14 LPC_LAD1
<15> CLK_PCIE_MINI3 13 14 LPC_LAD0 LPC_LAD1 <14,32,39,40>
15 16 LPC_LAD0 <14,32,39,40>
PCH_PLTRST#_EC 15 16
+1.5V_RUN +1.5V_RUN_WWAN
+3.3V +-9% 1000 750 17
17 18
18
PCLK_80H 19 20
<15> PCLK_80H 19 20
250 (Wake enable) 21 22 1 2 PCH_PLTRST#_EC
PCIE_PRX_WPANTX_N5 21 22
2 1 +3.3Vaux +-9% 330 250 5 (Not wake enable) <15> PCIE_PRX_WPANTX_N5
23
23 24
24 @ R710 0_0402_5%~D
R727 0_0805_5%~D PCIE_PRX_WPANTX_P5 25 26
<15> PCIE_PRX_WPANTX_P5 25 26
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
27 28
27 28
RF review in 0629 +1.5V +-5% 500 375 NA C617 0.1U_0402_10V7K~D 29
29 30
30
1 1 1 2 PCIE_PTX_WPANRX_N5_C 31 32
<15> PCIE_PTX_WPANRX_N5 PCIE_PTX_WPANRX_P5_C 31 32
<15> PCIE_PTX_WPANRX_P5 1 2 33 34
33 34
C593
C594
C618 0.1U_0402_10V7K~D 35 36 USBP6-
PCIE_MCARD3_DET# 35 36 USBP6+ USBP6- <17>
37 38 USBP6+ <17>
2 2 <18> PCIE_MCARD3_DET# 37 38 NC_USB_MCARD3_DET#
39 40
39 40
+3.3V_RUN 1 2 41
41 42
42
R711 100K_0402_5%~D 43 44
43 44
45 46
45 46
47 48
47 48
49 50
49 50
51 52
51 52
53
GNDGND
54 WPAN Noise
USB_MCARD3_DET#
+1.5V_RUN ACES_51711-0520W-001
+3.3V_PCIE_FLASH
CONN@ 1
@ C627
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
4.7U_0603_6.3V6K~D
0.1U_0402_25V6K~D
4700P_0402_25V7K~D
2
@ C621
1 1 1 1 1 2 2 1
C619
C620
C622
C623
C624
C625
C626
A A
2 2 2 2 2 1 1 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 34 of 61
Rev
1.0
5 4 3 2 1
Power Control for Mini card2 +3.3V_SUS
Express/Smart Card Conn.
+3.3V_ALW
Q38 +3.3V_WLAN
+PWR_SRC_S SP021106240 +3.3V_SUS
2.2K_0402_5%~D
2.2K_0402_5%~D
+3.3V_ALW SI3456DDV-T1-GE3_TSOP6~D +1.5V_RUN +3.3V_RUN +5V_RUN
1
D D
D
100K_0402_5%~D
R731
R732
6
S
1
100K_0402_5%~D
5 4
R714
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
2 +3.3V_RUN
+3.3V_SUS
R713
1 +1.5V_RUN +5V_RUN
2
JEXP1 1 1 1 1
1
2 1
3
2 1
C635
C634
C633
C645
R715 CARD_SMBCLK 4 3
2
4 3
DMN66D0LDW-7_SOT363-6~D
20K_0402_5%~D CARD_SMBDAT 6 5
6 5
3
2 2 2 2
4700P_0402_25V7K~D
8 7
8 7
1 <17> USBP10+ 10 9
2
10 9
Q39B
1M_0402_5%~D
<17> USBP10- 12 12 11 11
C632
5 14 14 13 13
R1620
<15> CLK_PCIE_EXP# 16 16 15 15
6
Q39A 2 18 17
4 <15> CLK_PCIE_EXP 18 17
DMN66D0LDW-7_SOT363-6~D 20 19
20 19
<15> PCIE_PRX_EXPTX_N3 22 21
2
22 21
<39> AUX_EN_WOWL 2 <15> PCIE_PRX_EXPTX_P3 24 24 23 23
C647 0.1U_0402_10V7K~D 26 25 EXPRESS_DET#
26 25 EXPRESS_DET# <39>
1
<15> PCIE_PTX_EXPRX_N3 1 2 PCIE_PTX_EXPRX_N3_C 28 27 0_0402_5%~D 2 1 R734 @ SIO_SLP_S3# <11,16,27,39,42,47,48,49>
1
28 27
<15> PCIE_PTX_EXPRX_P3 1 2 PCIE_PTX_EXPRX_P3_C 30 29 EXPRCRD_STBY_R# 2 1 RUN_ON <27,39,42,47,48>
R716 C648 0.1U_0402_10V7K~D 30 29 0_0402_5%~D R717 @
32 32 31 31
CARD_SMBCLK SMART_DET# EXPCLK_REQ# <15>
100K_0402_5%~D Remove Express card PCIE TX cap <40> CARD_SMBCLK 34 34 33 33
SMART_DET# <39>
CARD_SMBDAT 36 35 PCH_PLTRST#_EC <17,32,34,39,40>
<40> CARD_SMBDAT
2
36 35
38 38 37 37
<34,40> PCIE_WAKE# 40 40 39 39 CLK_SMART_48M <15>
42 G2 G1 41
Reserve for ESD in 1130
E&T_1001K-F40C-03L
C Power Control for Mini card1 CONN@ C
+PCIE_WWAN +3.3V_PCIE_WWAN PCH_PLTRST#_EC EXPCLK_REQ#
+3.3V_ALW
Q40 1 1
+3.3V_ALW +PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D short
CE14 CE20
470K_0402_5%~D
6 PJP9 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D
S
1
2 2
100K_0402_5%~D
5 4 1 2 @ @
1
R722
2
R721
1 PAD-OPEN 1x3m
1
G
RF review in 0629 R723 EXPRESS_DET#
2
1K_0402_1%~D
2
DMN66D0LDW-7_SOT363-6~D
1
3
220P_0402_50V8J~D
2
CE22
1 4.7M_0402_5%~D
1
Q41B
0.1U_0402_25V6K~D
+3.3V_WWAN_CHG
2
R1625
C644
MCARD_WWAN_PWREN# 5 @
2
6
Q41A
4
DMN66D0LDW-7_SOT363-6~D
2
<39> MCARD_WWAN_PWREN 2
1
R726
1
D
SSM3K7002FU_SC70-3~D
100K_0402_5%~D
Q73
2 MCARD_WWAN_PWREN#
G
2
S
3
B B
Power Control for Mini card3
+3.3V_ALW
Q42 +3.3V_PCIE_FLASH
+3.3V_ALW +PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D
470K_0402_5%~D
6
S
1
100K_0402_5%~D
5 4
1
R729
2
R728
1
1
G
R730
2
20K_0402_5%~D
2
DMN66D0LDW-7_SOT363-6~D
3
220P_0402_50V8J~D
2
1 4.7M_0402_5%~D
1
Q43B
R1628
C650
5
2
6
Q43A
4
DMN66D0LDW-7_SOT363-6~D
2
<39> MCARD_MISC_PWREN 2
1
R733
A 100K_0402_5%~D A
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MINI CARD PWR/EXP_SC
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 35 of 61
Rev
1.0
5 4 3 2 1
L95 DLW21SN900SQ2L_0805_4P~D
USB3RN2 1 2 USB3RN2_D- USBP1- 1 USBP1_R_D-
<17> USB3RN2 1 2 <36> USBP1- 1 2 2
USB3RP2 4 3 USB3RP2_D+ USBP1+ 4 3 USBP1_R_D+ CONN list 0627B
<17> USB3RP2 4 3 <36> USBP1+ 4 3
DLW21SN900HQ2L_0805_4P~D L51 +5V_USB_PWR
1 2 1 2 JUSB1
@ R1605 0_0402_5%~D @ R736 0_0402_5%~D 1
USBP1_R_D- VBUS
2
D-
150U_D2_6.3VY_R15M~D
0.1U_0402_25V6K~D
1 2 1 2 1 USBP1_R_D+ 3
@ R1604 0_0402_5%~D @ R740 0_0402_5%~D D+
1 4
GND
C651
D + USB3RN2_D- 5 D
StdA-SSRX-
2
C654
USB3RP2_D+ 6 10
StdA-SSRX+ GND
PESD5V0U2BT_SOT23-3~D
D72
7 11
2 2 USB3TN2_D- GND-DRAIN GND
8 12
L96 D78 USB3TP2_D+ StdA-SSTX- GND
9 13
USB3TN2 USB3T_N2 USB3TN2_D- USB3TP2_D+ USB3TP2_D+ StdA-SSTX+ GND
<17> USB3TN2 2 1 1
1 2
2 1 10
C412 .1U_0402_16V7K~D LOTES_AUSB0015-P001A
USB3TN2_D- 2 9 USB3TN2_D- CONN@
USB3TP2 2 1 USB3T_P2 4 3 USB3TP2_D+
<17> USB3TP2 4 3
C413 .1U_0402_16V7K~D USB3RP2_D+ 4 7 USB3RP2_D+
1
DLW21SN900HQ2L_0805_4P~D
1 2 USB3RN2_D- 5 6 USB3RN2_D-
@ R1606 0_0402_5%~D
3
1 2
@ R1603 0_0402_5%~D 8
IP4292CZ10-TB_XSON10U10~D
+5V_USB_PWR
+5V_ALW
U48 +SATA_SIDE_PWR
1 GND FAULT1# 10 USB_OC0# <17,37>
2 IN OUT1 9
10U_0805_10V6K~D
0.1U_0402_25V6K~D
3 IN OUT2 8
<39> ESATA_USB_PWR_EN# 4 EN1# ILIM 7
1 1 5 EN2# FAULT#2 6 USB_OC1# <17>
C C
T-PAD 11
1
C676
C675
TPS2560DRCR-PG1.1_SON10_3X3~D R748
2 2 24.9K_0402_1%~D
2
+SATA_SIDE_PWR
0.1U_0402_25V6K~D
150U_D2_6.3VY_R15M~D
1
1
C667
C668
+
2 2
L97 D79 TEMP: DC231106170
B USB3T_N3 USB3TN3_D- USB3TP3_D+ USB3TP3_D+ B
<17> USB3TN3 2 1 1
1 2
2 1 10
C414 .1U_0402_16V7K~D
USB3TN3_D- 2 9 USB3TN3_D- JESA1
2 1 USB3T_P3 4 3 USB3TP3_D+ 1
<17> USB3TP3 4 3 VBUS
C415 .1U_0402_16V7K~D USB3RP3_D+ 4 7 USB3RP3_D+ USBP2_D- 2
DLW21SN900HQ2L_0805_4P~D USBP2_D+ D- USB2.0
3
USB3RN3_D- USB3RN3_D- D+
1 2 5 6 4
@R1609
@ R1609 0_0402_5%~D GND
3
1 2 ESATA_PTX_DRX_P4_C 1 2 SATA_PTX_DRX_P4 5
<14> ESATA_PTX_DRX_P4_C GND
@R1612
@ R1612 0_0402_5%~D 8 C671 0.01U_0402_16V7K~D 6
ESATA_PTX_DRX_N4_C A+
<14> ESATA_PTX_DRX_N4_C 1 2 SATA_PTX_DRX_N4 7
IP4292CZ10-TB_XSON10U10~D C672 0.01U_0402_16V7K~D A- ESATA
8
ESATA_PRX_DTX_N4_C GND
1 2 SATA_PRX_DTX_N4 9
<14> ESATA_PRX_DTX_N4_C C673 0.01U_0402_16V7K~D B-
10
ESATA_PRX_DTX_P4_C B+
1 2 SATA_PRX_DTX_P4 11
<14> ESATA_PRX_DTX_P4_C C674 0.01U_0402_16V7K~D GND
USB3RN3_D- 12
USB3RP3_D+ SSRX-
13
SSRX+
14
USB3TN3_D- GND
15
L98 L90 USB3TP3_D+ SSTX- USB3.0
16
USB3RN3_D- USBP2_D- SSTX+
<17> USB3RN3 1 2 <17> USBP2- 1 2
1 2 1 2
17
USB3RP3_D+ USBP2_D+ GND
<17> USB3RP3 4 3 <17> USBP2+ 4 3 18
4 3 4 3 GND
19
DLW21SN900HQ2L_0805_4P~D DLW21SN900SQ2L_0805_4P~D GND
20
GND
1 2 1 2
3
@R1607
@ R1607 0_0402_5%~D @ R1150 0_0402_5%~D TAIWI_EU147-165CRL-TW
A CONN@ A
1 2 1 2
@R1608
@ R1608 0_0402_5%~D @ R1151 0_0402_5%~D
D74
PESD5V0U2BT_SOT23-3~D
1
Compal Electronics, Inc.
Title
Place D74 close to JESATA1 USB2.0/3.0 ESATA
5 4
WWW.AliSaler.Com 3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 36 of 61
Rev
1.0
5 4 3 2 1
AUDIO BOARD
Pitch=0.5 IO BOARD
Pitch=0.5
Follow CONN List_1130A
Follow CONN List_0609A
D JIO1 D
JAUD1 +5V_ALW 1 2 +SIM_PWR
1 2
1 3 4 UIM_CLK <34>
AUD_HP_OUT_R 1 3 4
<29> AUD_HP_OUT_R 2 5 6 UIM_RESET <34>
2 5 6
3 7 8 UIM_VPP <34>
AUD_HP_OUT_L 3 7 8
<29> AUD_HP_OUT_L 4 9 10 UIM_DATA <34>
4 <17,36> USB_OC0# 9 10
5 <39> USB_SIDE_EN# 11 12
MIC_IN_R 5 11 12
6 13 14 +3.3V_ALW_PCH
<29> MIC_IN_R 6 13 14
7 <17> USBP0- 15 16
AUD_HP_NB_SENSE 7 15 16
8 <17> USBP0+ 17 18 PCH_AZ_MDC_SDIN1 <14>
<29,39> AUD_HP_NB_SENSE 8 17 18
9 19 20 PCH_AZ_MDC_SYNC <14>
<17> USB_OC4# 9 SW_LAN_TX0- 19 20
<39> USB_SIDE_EN# 10 10 <30> SW_LAN_TX0- 21 21 22 22 PCH_AZ_MDC_SDOUT <14>
11 SW_LAN_TX0+ 23 24 PCH_AZ_MDC_RST1#
+5V_ALW 11 <30> SW_LAN_TX0+ 23 24
12 12 25 25 26 26 PCH_AZ_MDC_BITCLK <14>
Change CIS symbol_ 12/07 13 SW_LAN_TX1- 27 28
13 <30> SW_LAN_TX1- SW_LAN_TX1+ 27 28 RED_CRT
14 14 <30> SW_LAN_TX1+ 29 29 30 30 RED_CRT <23>
15 31 32 GREEN_CRT
15 31 32 GREEN_CRT <23>
L107 16 SW_LAN_TX2- 33 34 BLUE_CRT
16 <30> SW_LAN_TX2- 33 34 BLUE_CRT <23>
USBP9+ 1 2 USBP9_D+ 17 SW_LAN_TX2+ 35 36
<17> USBP9+ 1 2 USBP9_D+ 17 <30> SW_LAN_TX2+ 35 36 HSYNC_BUF
18 18 37 37 38 38 HSYNC_BUF <23>
USBP9_D- 19 SW_LAN_TX3- 39 40 VSYNC_BUF VSYNC_BUF <23>
USBP9- USBP9_D- 19 <30> SW_LAN_TX3- SW_LAN_TX3+ 39 40 DAT_DDC2_CRT
<17> USBP9- 4 4 3 3 20 20 <30> SW_LAN_TX3+ 41 41 42 42 DAT_DDC2_CRT <23>
21 43 44 CLK_DDC2_CRT
GND 43 44 CLK_DDC2_CRT <23>
OCF2012181YZF_4P 1 22 45 46
GND <30> LAN_ACTLED_YEL# 45 46
1 2 C1186 47 48 +5V_RUN
<30> LED_100_ORG# 47 48
R1656 0_0402_5%~D ACES_51522-0200N-P01 49 50 +3.3V_LAN
<30> LED_10_GRN# 49 50
@ 0.1U_0402_16V4Z~D
1 2 2
CONN@
R1657 0_0402_5%~D 51 52
@ G1 G2
E&T_1000K-F50E-04R
CONN@
C C
+3.3V_LAN +5V_RUN +3.3V_ALW_PCH +5V_ALW
0.1U_0402_25V6K~D
1 3 PCH_AZ_MDC_RST1#
S
<14> PCH_AZ_MDC_RST#
0.1U_0402_10V7K~D
0.1U_0402_25V6K~D
+5V_ALW Q44 1 1
C482
1 1
G
2
C1001
SSM3K7002FU_SC70-3~D C1185
C998
0.1U_0402_16V4Z~D
1
R752 R751 2 2
100K_0402_5%~D 2 2
10K_0402_5%~D
2
Place close Place close Place close to Place close to
2
<39> MDC_RST_DIS# to JIO1.20,22 to JIO1.14,16 JIO1.18 JIO1.6,8,10,12
Follow CONN List_0616E
B +3.3V_ALW B
MEDIA BOARD Sniffer Switch Hall Sensor
SF1
2
1 U8 1
1
Follow CONN List_0621A C1184
VDD
WIRELESS_ON#/OFF 2 0.1U_0402_16V4Z~D
<39> WIRELESS_ON#/OFF 2
JMED1
MEDIA_DET# 1 3 LID_CL# 3 2
<18> MEDIA_DET# VOL_MUTE 1 3 <39,43> LID_CL# OUTPUT
2
<40> VOL_MUTE VOL_DOWN 2
3
GND
<40> VOL_DOWN VOL_UP 3
4
<40> VOL_UP 4 SC12P-C-V-TR_3P
5 7
5 G1 S-5712ACDL1-M3T1U_SOT23-3
6 8
1
6 G2
PS_HPF10052-061000R
Defult on,
CONN@ WIRELESS_ON/OFF#: Follow E4
LOW: ON
HIGH: OFF
Follow E4
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, IO/AUDIO/MEDIA/SNF
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 37 of 61
Rev
1.0
5 4 3 2 1
TEMP: DC061106200
JDOCK1
DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF <39,53>
3 3 4 4
<30> DOCK_LOM_SPD10LED_GRN# DPD_CA_DET DPC_CA_DET DOCK_LOM_SPD100LED_ORG# <30>
5 6
<26> DPD_CA_DET 5 6 DPC_CA_DET <26>
7 8
C690 DPD_DOCK_LANE_P0 7 8 DPC_DOCK_LANE_P0
<16> DPD_PCH_LANE_P0 2 1 0.1U_0402_10V7K~D 9
9 10
10 C691 2 1 0.1U_0402_10V7K~D
D C679 DPD_DOCK_LANE_N0 DPC_DOCK_LANE_N0 DPC_PCH_LANE_P0 <16> D
<16> DPD_PCH_LANE_N0 2 1 0.1U_0402_10V7K~D 11
11 12
12 C680 2 1 0.1U_0402_10V7K~D DPC_PCH_LANE_N0 <16>
13 14
C681 DPD_DOCK_LANE_P1 13 14 DPC_DOCK_LANE_P1
<16> DPD_PCH_LANE_P1 2 1 0.1U_0402_10V7K~D 15
15 16
16 C682 2 1 0.1U_0402_10V7K~D
C683 DPD_DOCK_LANE_N1 DPC_DOCK_LANE_N1 DPC_PCH_LANE_P1 <16>
<16> DPD_PCH_LANE_N1 2 1 0.1U_0402_10V7K~D 17 18 C684 2 1 0.1U_0402_10V7K~D
17 18 DPC_PCH_LANE_N1 <16>
19 20
C692 DPD_DOCK_LANE_P2 19 20 DPC_DOCK_LANE_P2 DPC_PCH_DOCK_HPD
<16> DPD_PCH_LANE_P2 2 1 0.1U_0402_10V7K~D 21
21 22
22 C693 2 1 0.1U_0402_10V7K~D DPC_PCH_LANE_P2 <16>
C685 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_N2 23 24 DPC_DOCK_LANE_N2 C686 2 1 0.1U_0402_10V7K~D
<16> DPD_PCH_LANE_N2 23 24 DPC_PCH_LANE_N2 <16>
25 26
C687 DPD_DOCK_LANE_P3 25 26 DPC_DOCK_LANE_P3
<16> DPD_PCH_LANE_P3 2 1 0.1U_0402_10V7K~D 27
27 28
28 C688 2 1 0.1U_0402_10V7K~D
DPC_PCH_LANE_P3 <16>
1
C689 2 1 0.1U_0402_10V7K~D DPD_DOCK_LANE_N3 29 30 DPC_DOCK_LANE_N3 C694 2 1 0.1U_0402_10V7K~D
<16> DPD_PCH_LANE_N3 29 30 DPC_PCH_LANE_N3 <16>
31 32
DPD_DOCK_AUX 31 32 DPC_DOCK_AUX R758
<26> DPD_DOCK_AUX 33 33 34 34 DPC_DOCK_AUX <26>
DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# 100K_0402_5%~D
<26> DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# <26>
37 38
2
DPD_PCH_DOCK_HPD 37 38 DPC_PCH_DOCK_HPD
<16> DPD_PCH_DOCK_HPD 39 39 40 40 DPC_PCH_DOCK_HPD <16>
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <53>
0.033U_0402_16V7K~D
0.033U_0402_16V7K~D
1 43 43 44 44 1
BLUE_DOCK 45 46
<23> BLUE_DOCK 45 46 DAT_DDC2_DOCK <23>
C695
C696
47 47 48 48 CLK_DDC2_DOCK <23>
2
49 49 50 50
2
Close to DOCK
51 51 52 52 Its for Enhance ESD on dock issue.
RED_DOCK 53 54 SATA_PRX_DKTX_P5 2 1
<23> RED_DOCK 53 54 SATA_PRX_DKTX_N5 SATA_PRX_DKTX_P5_C <14>
Close to DOCK 55 55 56 56 C697 2 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_N5_C <14>
57 58 C698 0.01U_0402_16V7K~D
Its for Enhance ESD on dock issue. GREEN_DOCK 59
57 58
60 SATA_PTX_DKRX_P5 1 2
<23> GREEN_DOCK 59 60 SATA_PTX_DKRX_P5_C <14>
61 62 SATA_PTX_DKRX_N5 C699 1 2 0.01U_0402_16V7K~D
61 62 SATA_PTX_DKRX_N5_C <14>
63 63 64 64 C700 0.01U_0402_16V7K~D Change CIS symbol_ 12/07
65 66 USBP7_D+ 3 4
<23> HSYNC_DOCK 65 66 USBP7_D- 3 4 USBP7+ <17>
<23> VSYNC_DOCK 67 67 68 68
69 69 70 70
DPD_PCH_DOCK_HPD 71 72 2 1
<40> CLK_MSE 71 72 USBP3+ <17> 2 1 USBP7- <17>
<40> DAT_MSE 73 73 74 74 USBP3- <17>
C @ L108 OCF2012181YZF_4P C
75 75 76 76
<29> DAI_BCLK# 77 77 78 78 CLK_KBD <40>
1
79 80 R1672 2 1 0_0402_5%~D
<29> DAI_LRCK# 79 80 DAT_KBD <40>
81 81 82 82
R757 83 84 R1673 2 1 0_0402_5%~D
<29> DAI_DI 83 84 USB3RN4 <17>
100K_0402_5%~D 85 86
<29> DAI_DO# 85 86 USB3RP4 <17>
87 88 EMI solution for E-Docking USB
2
87 88
<29> DAI_12MHZ# 89 90 USB3TN4 <17>
89 90
91 92 USB3TP4 <17>
91 92
93 94
93 94
95 96
95 96
<39> D_LAD0 97 98
97 98 BREATH_LED# <39,43>
<39> D_LAD1 99 100
99 100 DOCK_LOM_ACTLED_YEL# <30>
101 102
101 102
<39> D_LAD2 103 104
103 104 DOCK_LOM_TRD0+ <30>
<39> D_LAD3 105 106
105 106 DOCK_LOM_TRD0- <30>
107 108
107 108 +3.3V_ALW
<39> D_LFRAME# 109 110
109 110 DOCK_LOM_TRD1+ <30> +LOM_VCT
<39> D_CLKRUN# 111 112
111 112 DOCK_LOM_TRD1- <30>
113 114
113 114 DOCK_DET#
<39> D_SERIRQ 115 116 1 1 2
115 116 @ R755 10K_0402_5%~D
<39> D_DLDRQ1# 117 118 +LOM_VCT
117 118 C701
119 120
119 120 1U_0402_6.3V6K~D
<17> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <30>
121 122 2
123 124 DOCK_LOM_TRD2- <30>
123 124
125 126
125 126
<40> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <30>
127 128
<40> DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- <30>
129 130
131 132
131 132
<39,53> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <52>
133 134
<44> DOCK_PSID 135 136 DOCK_DCIN_IS- <52>
135 136
137 138
B 137 138 D32 B
<40> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <40>
139 140 RB751S40T1_SOD523-2~D
141 142
SLICE_BAT_PRES# 141 142 DOCK_DET_R#
<39,53> SLICE_BAT_PRES# 143 144 1 2 DOCK_DET# <39>
143 144
145 149 +DOCK_PWR_BAR
GND1 PWR2
+DOCK_PWR_BAR 146 150
PWR1 PWR2
0.1U_0603_50V7K~D
147 151
PWR1 PWR2
3
PESD24VS2UT_SOT23-3~D
0.1U_0603_50V7K~D
D33
148 152
PWR1 GND2
4.7U_0805_25V6K~D
C703
1 @ 1 153 159
Shield_G Shield_G
C702
154 160
Shield_G Shield_G
CE6
155 161
Shield_G Shield_G 2
156 162
1
2 2 Shield_G Shield_G
157 163
Shield_G Shield_G
158 164
Shield_G Shield_G
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
JAE_WD2F144WB6-DT
1
CONN@
@ RE11 @ RE12 R756
10_0402_1%~D 10_0402_1%~D 33_0402_5%~D
2
1 1 1
@CE8
@CE8 @CE9
@CE9 C704
4.7P_0402_50V8C~D 4.7P_0402_50V8C~D 12P_0402_50V8J~D
2 2 2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING CONN
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 38 of 61
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
1 2 DYN_TURB_PWR_ALRT#
R796 10K_0402_5%~D
1 2 HW_GPS_DISABLE2#
R798 100K_0402_5%~D
+3.3V_ALW
10U_0603_6.3V6M~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_10V7K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
1 2 PROCHOT_GATE
R761 100K_0402_5%~D
1 2 CPU_DETECT# 1 1 1 1 1 1
R763 100K_0402_5%~D
C705
C706
C707
C708
C709
C710
1 2 SLICE_BAT_PRES#
R760 20K_0402_5%~D 2 2 2 2 2 2
D D
1 2 WWAN_RADIO_DIS#
A17
B30
A43
A54
R774 100K_0402_5%~D
B5
1 2 USB_PWR_SHR_EN# U46 +3.3V_ALW
R776 100K_0402_5%~D @ C711 0.1U_0402_25V6K~D
VCC1
VCC1
VCC1
VCC1
VCC1
1 2 USB_SIDE_EN# A23 1 2
CRT_SWITCH GPIOI0 SIO_SLP_A# ACAV_IN_NB <40,52,53>
R768 10K_0402_5%~D <23> CRT_SWITCH B52 B63
GPIOA0 GPIOI1 SIO_SLP_A# <16,42,48>
5
1 2 ESATA_USB_PWR_EN# MDC_RST_DIS# A49 A60 0.75V_DDR_VTT_ON
<37> MDC_RST_DIS# MCARD_MISC_PWREN GPIOA1 GPIOI2/TACH0 0.75V_DDR_VTT_ON <46>
R769 100K_0402_5%~D B53 A61 1
P
<35> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <16,42,46> B
1 2 USB_PWR_SHR_VBUS_EN PROCHOT_GATE A50 B65
O 4D34 2@
<52> PROCHOT_GATE SIO_SLP_S3# <11,16,27,35,42,47,48,49> 1
R778 100K_0402_5%~D LID_CL_SIO# GPIOA3 GPIOI4 DOCK_AC_OFF <38,53>
B54 A62 IMVP_PWRGD <51> 2
GPIOA4 GPIOI5 A
G
1 2 DOCK_SMB_ALERT# DOCK_SMB_ALERT# A51 B66 1 2 RB751S40T1_SOD523-2~D
<38,53> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <51>
1
R762 10K_0402_5%~D B55 A63 @
@R765
R765 0_0402_5%~D U47 @
3
WIRELESS_ON#/OFF GPIOA6 GPIOI7 DOCK_AC_OFF_EC TC7SH08FU_SSOP5~D R770 @
1 2 A52
R771 100K_0402_5%~D GPIOA7 DOCK_AC_OFF_EC <53> 33K_0402_5%~D
GPIOJ0 B67
USB_SIDE_EN# AUX_EN_WOWL <35>
<37> USB_SIDE_EN# EN_I2S_NB_CODEC#
A33 GPIOB0 GPIOJ1/TACH1 A64
SIO_SLP_LAN# WLAN_LAN_DISB# <30> ---vPro only
<29> EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN# <16,30>
2
GPIOB1 GPIOJ2/TACH2 SIO_SLP_SUS#
A34 GPOC2 GPIOJ3 B6 SIO_SLP_SUS# <16>
<53> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6
PANEL_BKEN_EC GPOC3 GPIOJ4 MODC_EN GPIO_PSID_SELECT <44>
<24> PANEL_BKEN_EC A35 GPOC4 GPIOJ5 B7 MODC_EN <28>
Check card side pull up resistor ENVDD_PCH B38 A7 DOCK_HP_DET
<16,24> ENVDD_PCH LCD_TST GPOC5 GPIOJ6 DOCK_MIC_DET DOCK_HP_DET <29>
<24> LCD_TST A36 GPOC6/TACH4 GPIOJ7 B8 DOCK_MIC_DET <29>
+3.3V_RUN PSID_DISABLE# A37
<44> PSID_DISABLE# PBAT_PRES# GPIOC7 ME_FWP
<44,53> PBAT_PRES# B40 GPIOD0 GPIOK0 A8 ME_FWP <14>
1 2 EXPRESS_DET# DOCKED A38 B9 MASK_SATA_LED#
<30> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <43>
R460 100K_0402_5%~D DOCK_DET# B41 B10
SMART_DET# <38> DOCK_DET# AUD_NB_MUTE# GPIOC0 GPIOK2 LED_SATA_DIAG_OUT# 1.8V_RUN_PWRGD <47>
1 2 A39 GPIOB7 GPIOK3 A10 LED_SATA_DIAG_OUT# <43>
<29> AUD_NB_MUTE# MCARD_WWAN_PWREN TEMP_ALERT#_R
R461 100K_0402_5%~D B42 GPIOB6 GPIOK4 B11 1 2 TEMP_ALERT# TEMP_ALERT# <14,18>
PCMCIA_DET# <35> MCARD_WWAN_PWREN LCD_VCC_TEST_EN RUN_ON @ R738 0_0402_5%~D +3.3V_RUN
1 2 <24> LCD_VCC_TEST_EN A40 GPIOB5 GPIOK5 A11 RUN_ON <27,35,42,47,48>
R463 100K_0402_5%~D CCD_OFF B43 B12
<24> CCD_OFF GPIOB4 GPIOK6
1 2 MCARD_PCIE_SATA# AUD_HP_NB_SENSE A41 A12
<29,37> AUD_HP_NB_SENSE ESATA_USB_PWR_EN# GPIOB3 GPIOK7 SPI_WP#_SEL <14> D_CLKRUN#
R457 100K_0402_5%~D B44 2 1
C WIRELESS_ON#/OFF <36> ESATA_USB_PWR_EN# GPIOB2 SUS_ON C
1 2 B60 R777 100K_0402_5%~D
GPIOL0/PWM7 SUS_ON <42> D_SERIRQ
@ R766 100K_0402_5%~D A57 2 1
SP_TPM_LPC_EN GPIOL1/PWM8 BAT1_LED# R780 100K_0402_5%~D
1 2 B32 B64 BAT1_LED# <43>
@ R772 10K_0402_5%~D SLICE_BAT_ON GPIOD1 GPIOL2/PWM0 D_DLDRQ1#
<53> SLICE_BAT_ON A31 GPIOD2 GPIOL3/PWM1 B68 2 1
SLICE_BAT_PRES# B33 A9 BAT2_LED# R782 100K_0402_5%~D
LCD_TST <38,53> SLICE_BAT_PRES# EXPRESS_DET# GPIOD3 GPIOL4/PWM3 BAT2_LED# <43>
1 2 B15 GPIOD4 GPIOL5/PWM2 B1
R767 100K_0402_5%~D <35> EXPRESS_DET# SMART_DET# USH_PWR_ON
A15 GPIOD5 GPIOL6 A18 PAD~D T117 @
<35> SMART_DET# PCMCIA_DET# B16 A44
SYS_LED_MASK# GPIOD6 GPIOL7/PWM5 RUN_ON
1 2 A16 2 1
R775 10K_0402_5%~D GPIOD7 HW_GPS_DISABLE2# R786 100K_0402_5%~D
B34 HW_GPS_DISABLE2# <34>
DGPU_PWR_EN GPIOM1 BREATH_LED#
1 2 B39 BREATH_LED# <38,43>
R1582 100K_0402_5%~D GPIOM3/PWM4 CPU_VTT_ON
A1 B51 2 1
GFX_MEM_VTT_ON USB_PWR_SHR_EN# GPIOE0/RXD GPIOM4/PWM6 R789 100K_0402_5%~D
1 2 B2
GPIOE1/TXD
R1583 100K_0402_5%~D GFX_MEM_VTT_ON A2
CHARGE_EN MCARD_PCIE_SATA# GPIOE2/RTS# LPC_LAD0 0.75V_DDR_VTT_ON 2
1 2 B3
GPIOE3/DSR# LAD0
A27 LPC_LAD0 <14,32,34,40> 1
R3 100K_0402_5%~D CPU_DETECT# A3 A26 LPC_LAD1 R790 100K_0402_5%~D
<7> CPU_DETECT# DGPU_PWR_EN GPIOE4/CTS# LAD1 LPC_LAD2 LPC_LAD1 <14,32,34,40> SLICE_BAT_ON
B45 B26 LPC_LAD2 <14,32,34,40> 2 1
SIO_FAN1_DET# GPIOE5/DTR# LAD2 LPC_LAD3 R791 100K_0402_5%~D
A42 B25 LPC_LAD3 <14,32,34,40>
DP_HDMI_HPD GPIOE6/RI# LAD3 LPC_LFRAME# SUS_ON
@ T116 PAD~D B4 A21 LPC_LFRAME# <14,32,34,40> 2 1
GPIOE7/DCD# LFRAME# PCH_PLTRST#_EC R878 100K_0402_5%~D
B22 PCH_PLTRST#_EC <17,32,34,35,40>
LRESET# CLK_PCI_5048
A28 CLK_PCI_5048 <17>
+3.3V_ALW ZODD_WAKE# PCICLK CLKRUN#
A59 B20 CLKRUN# <16,32,40>
LOM_SMB_ALERT# GPIOF0 CLKRUN#
<30> LOM_SMB_ALERT# B62
GPIOF1 LPC_LDRQ1#
<16> SUSACK# A58 A22 LPC_LDRQ1# <14>
GPIOF2 LDRQ1#
1 2 SIO_FAN1_DET# <30> LOM_ENERGY_DET
LOM_ENERGY_DET B61 B21 IRQ_SERIRQ
IRQ_SERIRQ <14,32,40>
DGPU_PWROK GPIOF3/TACH8 SER_IRQ CLK_SIO_14M
R1183 10K_0402_5%~D @ T110 PAD~D A56
GPIOF4/TACH7 14.318MHZ/GPIOM0
A32 CLK_SIO_14M <15> Reserve for ESD in 6/22
1 2 ZODD_WAKE# VGA_ID B59 B35 EC_32KHZ_ECE5048 <40> Place closed U46
R516 10K_0402_5%~D 3.3V_RUN_GFX_ON GPIOF5 CLK32/GPIOM2
@ T109 PAD~D A55
SLP_ME_CSW_DEV# GPIOF6
<14,18> SLP_ME_CSW_DEV# B58
GPIOF7 D_LAD0 PCH_PLTRST#_EC
B29
R801 1 @ DLAD0 D_LAD1 D_LAD0 <38>
<22> FAN1_DET# 2 0_0402_5%~D DLAD1
B28
LOM_LOW_PWR D_LAD2 D_LAD1 <38>
<30> LOM_LOW_PWR B47 A25 1
B CHARGE_EN GPIOG0/TACH5 DLAD2 D_LAD3 D_LAD2 <38> B
A45 A24
SIO_FAN1_DET# SYS_LED_MASK# GPIOG1 DLAD3 D_LFRAME# D_LAD3 <38> CE11
<43> SYS_LED_MASK# B48 B23 D_LFRAME# <38>
DYN_TURB_PWR_ALRT# GPIOG2 DLFRAME# D_CLKRUN# 0.1U_0402_25V6K~D
A46 A19 D_CLKRUN# <38>
GPIOG3 DCLKRUN# D_DLDRQ1# 2
<18> SIO_EXT_WAKE# @ R797 1 2 0_0402_5%~D B49
GPIOG4 DLDRQ1#
B24 D_DLDRQ1# <38>
@
WIRELESS_LED# A47 A20 D_SERIRQ
+3.3V_ALW <34,43> WIRELESS_LED# USB_PWR_SHR_VBUS_EN GPIOG5 DSER_IRQ D_SERIRQ <38>
B4 non used B50
GPIOG6
WLAN_RADIO_DIS# A48
<34> WLAN_RADIO_DIS# GPIOG7/TACH6 BC_INT#_ECE5048
A29 BC_INT#_ECE5048 <40>
BC_INT# BC_DAT_ECE5048
B31 BC_DAT_ECE5048 <40>
WIRELESS_ON#/OFF BC_DAT BC_CLK_ECE5048
<37> WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5048 <40>
VGA_ID BT_RADIO_DIS# GPIOH0 BC_CLK
1 2 <41> BT_RADIO_DIS# A13
R800 100K_0402_5%~D WWAN_RADIO_DIS# GPIOH1
<34> WWAN_RADIO_DIS# A53
SYS_PWROK SYSOPT1/GPIOH2 RUNPWROK
<7,16> SYS_PWROK B57 A4
DGPU_SELECT# SYSOPT0/GPIOH3 PWRGD RUNPWROK <7,40>
@ T114 PAD~D B14
GPIOH4 SP_TPM_LPC_EN
A14 B56 SP_TPM_LPC_EN <32>
CPU_VTT_ON GPIOH5 OUT65 +3.3V_ALW
<49> CPU_VTT_ON B17
GPIOH6
<16> PCH_DPWROK 1 2 B18
VGA_ID @R802
@ R802 0_0402_5%~D GPIOH7
1 2 B19 1 2
@R803
@ R803 100K_0402_5%~D TEST_PIN R804 1K_0402_1%~D +CAP_LDO trace width 20 mils
1
B46 +CAP_LDO
CAP_LDO CLK_SIO_14M CLK_PCI_5048 R805
1
B27 100K_0402_5%~D
VSS C714
C1
EP
1
4.7U_0603_6.3V6K~D
2
DB Version 0.4 2 @R794
@ R794 @ R795
VGA_ID0 ECE5048-LZY_DQFN132_11X11~D 10_0402_1%~D 10_0402_1%~D LID_CL_SIO# 2 1 LID_CL# <37,43>
R807 10_0402_1%~D
Discrete 0 1
2
UMA 1 1 1 C716
0.047U_0402_16V4Z~D
@ C712 @ C713 2
A 4.7P_0402_50V8C~D 4.7P_0402_50V8C~D A
2 2
ME_FWP PCH has internal 20K PD.
(suspend power rail)
ME_FWP DELL CONFIDENTIAL/PROPRIETARY
1
@ R793 Compal Electronics, Inc.
1K_0402_1%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5048
WWW.AliSaler.Com
2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7902P
Date: Wednesday, March 07, 2012 Sheet 39 of 61
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW +RTC_CELL
C720
0.1U_0402_25V6K~D
1
1 2 @ C721
R810 1U_0402_6.3V6K~D
100K_0402_5%~D 1 2
5
U50
1.05V_VTTPWRGD 1
P
<49,50> 1.05V_VTTPWRGD
2
B 1.05V_0.8V_PWROK
4 1.05V_0.8V_PWROK <14,51>
VCCSAPWROK O POWER_SW_IN#
<50> VCCSAPWROK 2 <22> POWER_SW_IN# 1 2 POWER_SW#_MB <43>
G
A R811 10K_0402_5%~D
1
Modify name net TC7SH08FU_SSOP5~D @
3
+RTC_CELL R815 C722
0_0402_5%~D 1U_0402_6.3V6K~D
1 2+RTC_CELL_VBAT 2
+3.3V_ALW
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
10U_0603_6.3V6M~D
+3.3V_ALW 1 1 1 1 1 1 1 1 1 1
C723
C725
C727
C729
C731
C726
C728
C739
C732
C730
+RTC_CELL
D 1 2 PCIE_WAKE# D
R759 10K_0402_5%~D 2 2 2 2 2 2 2 2 2 2
1
2 1 BC_DAT_EMC4022 @ C733
B64
A11
A22
B35
A41
A58
A52
A26
R821 100K_0402_5%~D R819 1U_0402_6.3V6K~D
B3
1 2 BC_DAT_ECE5048 U51 100K_0402_5%~D 1 2
R814 100K_0402_5%~D
VBAT
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
1 2 BC_DAT_ECE1117
2
R817 100K_0402_5%~D
1 2 PBAT_SMBDAT DOCK_PWR_SW# 1 2
<22> DOCK_PWR_SW# DOCK_PWR_BTN# <38>
R818 2.2K_0402_5%~D PS/2 INTERFACE MISC INTERFACE 1 R825 10K_0402_5%~D
1 2 PBAT_SMBCLK SML1_SMBDATA A5 A10 SYSTEM_ID
<15,30> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1
R820 2.2K_0402_5%~D SML1_SMBCLK B6 B10 BOARD_ID C734
<15,30> SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2 1U_0402_6.3V6K~D
1 2 LPC_LDRQ#_MEC CLK_TP_SIO A37 B14 DDR_ON
<41> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK DDR_ON <46> 2
@ R823 100K_0402_5%~D DAT_TP_SIO B40 B44 HOST_DEBUG_TX
<41> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_TX <34>
1 2 CHARGER_SMBDAT CLK_KBD A38 B46 HOST_DEBUG_RX
<38> CLK_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX HOST_DEBUG_RX <34>
R827 2.2K_0402_5%~D DAT_KBD B41 B26 RUNPWROK
<38> DAT_KBD GPIO113/PS2_DAT1A VCC_PRWGD RUNPWROK <7,39>
1 2 CHARGER_SMBCLK CLK_MSE A39 A25 EN_INVPWR
<38> CLK_MSE GPIO114/PS2_CLK0A GPIO060/KBRST EN_INVPWR <24>
R828 2.2K_0402_5%~D DAT_MSE B42 B36
<38> DAT_MSE GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK PCH_SATA_MOD_EN# <14>
PBAT_SMBDAT B59 B37
<44> PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO
1 2 SIO_LAN_SMBDATA PBAT_SMBCLK A56 B38
<44> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI
R830 2.2K_0402_5%~D A34 DDR_HVREF_RST_GATE
SIO_LAN_SMBCLK GPIO102/HSPI_SCLK DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE <7>
1 2 A35
R831 2.2K_0402_5%~D GPIO104/HSPI_MISO CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# <52> +RTC_CELL +3.3V_ALW
A36
GPIO106/HSPI_MOSI MSDATA CPU1.5V_S3_GATE <11>
JTAG INTERFACE GPIO116/MSDATA
A40 MSDATA <34>
1 2 GPU_SMBDAT JTAG_TDI A51 B43 MSCLK
GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK MSCLK <34>
R829 2.2K_0402_5%~D 1 2 AUX_ON JTAG_TDO B55 A45 SIO_A20GATE
SIO_A20GATE <18>
1
GPU_SMBCLK 2.7K_0402_5%~D R874 JTAG_CLK GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M PS_ID
1 2 B56 A55 PS_ID <44>
R822 2.2K_0402_5%~D JTAG_TMS GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 R870 R888
A53 A57
JTAG_RST# GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1 100K_0402_5%~D @
B57 B61
EC firmware can configure those un-used SMBUS pins as GPO (Output), JTAG_RST# GPIO157/LED2 FWP# 100K_0402_5%~D
B65
then it's OK to leave these un-used pins No-Connect. nFWP PROCHOT#_EC
A46
2
PROCHOT#/PWM4
C736 2 1 0.1U_0402_25V6K~D FAN PWM & TACH LAT_ON_SW# 1.05V_A_PWRGD_SIO
DOCK_POR_RST# B22 GENERAL PURPOSE I/O
<38> DOCK_POR_RST# GPIO050/FAN_TACH1
A21 B2 R884 1 2 1K_0402_1%~D VOL_MUTE
GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1 VOL_MUTE <37>
AUX_ON B23 A2
<30> AUX_ON GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2
B24 B8 R886 1 2 1K_0402_1%~D
GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1 VOL_UP <37> +1.05V_RUN_VTT
+3.3V_ALW PCH_ALW_ON A23 B18 R887 1 2 1K_0402_1%~D VOL_DOWN
<42,44> PCH_ALW_ON GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 VOL_DOWN <37> H_PROCHOT# <7,51,52>
<24> BIA_PWM_EC BIA_PWM_EC B25 A8 ME_SUS_PWR_ACK
GPIO055/PWM2 GPIO015/GPTP-OUT7 ME_SUS_PWR_ACK <16>
A24 B9 1.5V_SUS_PWRGD
GPIO056/PWM3 GPIO016/GPTP-IN8 1.5V_SUS_PWRGD <46>
1
10K_0402_5%~D
GPIO017/GPTP-OUT8
A9 PM_APWROK
PM_APWROK <16> ---vPro only 1 2
R824
A14 1.05V_A_PWRGD_SIO 1 2 ---vPro only @ R1179 10K_0402_5%~D
C GPIO026/GPTP-IN1 1.05V_A_PWRGD <48> C
JTAG_RST# citcuit BC-LINK B15 ALW_PWRGD_3V_5V @ R857 0_0402_5%~D
ALW_PWRGD_3V_5V <45>
GPIO027/GPTP-OUT1
1
BC_CLK_ECE5048 DEVICE_DET# Bat2 = Amber LED D
close to U51.B57 <39> BC_CLK_ECE5048 A43
GPIO123/BCM_A_CLK GPIO041
A17 DEVICE_DET# <28>
BC_DAT_ECE5048 B45 B39 RESET_OUT# Bat1 = Blue LED PROCHOT#_EC 2 @ Q47
<39> BC_DAT_ECE5048 RESET_OUT# <16>
2
BC_INT#_ECE5048 GPIO122/BCM_A_DAT GPIO107/nRESET_OUT G SSM3K7002FU_SC70-3~D
<39> BC_INT#_ECE5048 A42 A44
JTAG_RST# BC_CLK_EMC4022 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 PCH_RSMRST# 20mA drive pins
A12 B47 PCH_RSMRST# <41> 1 2 S
3
<22> BC_CLK_EMC4022 BC_DAT_EMC4022 GPIO022/BCM_B_CLK GPIO126 AC_PRESENT @ R812 100K_0402_5%~D
<22> BC_DAT_EMC4022 B13 A54 AC_PRESENT <16>
GPIO023/BCM_B_DAT GPIO151/GPTP-IN4
100_0402_1%~D
0.1U_0402_25V6K~D
BC_INT#_EMC4022 A13 B58 SIO_PWRBTN#
<22> BC_INT#_EMC4022 GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4 SIO_PWRBTN# <16>
1
@ 1 B20
PCH_PCIE_WAKE# GPIO044/BCM_C_CLK
A18
1
<16> PCH_PCIE_WAKE# GPIO043/BCM_C_DAT
R836
C735
@SHORT PADS~D
JTAG1 CONN@
PCIE_WAKE# B19 SMBUS INTERFACE 1 2
<34,35> PCIE_WAKE# GPIO042/BCM_C_INT#
BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT @ R1180 0_0402_5%~D
2 <41> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_DAT <38>
<41> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK
DOCK_SMB_CLK <38>
2
BC_INT#_ECE1117 GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK LCD_SMBDAT
<41> BC_INT#_ECE1117 A19 A4
BEEP GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA LCD_SMBCLK
<29> BEEP A16 B5
SIO_SLP_S5# GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK BAY_SMBDAT +3.3V_RUN
<16,42> SIO_SLP_S5# B16 B7
GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA
2
ACAV_IN_NB A15 A7 BAY_SMBCLK
<39,52,53> ACAV_IN_NB GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK
B48 GPU_SMBDAT
2
GPIO130/I2C2A_DATA
1
B49 GPU_SMBCLK
GPIO131/I2C2A_CLK CHARGER_SMBDAT R799
HOST INTERFACE GPIO132/I2C1G_DATA
A47 CHARGER_SMBDAT <52>
SIO_EXT_SMI# A6 B50 CHARGER_SMBCLK 10K_0402_5%~D
<14,17> SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK <52>
SIO_RCIN# A27 B52 CARD_SMBDAT
<18> SIO_RCIN# GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <35>
SSM3K7002FU_SC70-3~D
LPC_LDRQ#_MEC B29 A49 CARD_SMBCLK ALWON
CARD_SMBCLK <35>
2
IRQ_SERIRQ LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK SIO_LAN_SMBDATA RUNPWROK
<14,32,39> IRQ_SERIRQ A28 B53 SIO_LAN_SMBDATA <15,30>
PCH_PLTRST#_EC SER_IRQ GPIO143/I2C1E_DATA SIO_LAN_SMBCLK
<17,32,34,35,39> PCH_PLTRST#_EC B30 A50 SIO_LAN_SMBCLK <15,30> 1
CLK_PCI_MEC LRESET# GPIO144/I2C1E_CLK
<17> CLK_PCI_MEC A29
PCI_CLK
1
LPC_LFRAME# @ C1208 D
<14,32,34,39> LPC_LFRAME# B31
LPC_LAD0 LFRAME# 0.1U_0402_25V6K~D
<14,32,34,39> LPC_LAD0 A30
LAD0 DELL PWR SW INF <42> RUN_ON_ENABLE# 2
2
Q45
LPC_LAD1 B32 A59 G
<14,32,34,39> LPC_LAD1 LAD1 BGPO0
LPC_LAD2 A31 B63 LAT_ON_SW#
32 KHz Clock <14,32,34,39> LPC_LAD2 S
3
LPC_LAD3 LAD2 VCI_IN2# ALWON
<14,32,34,39> LPC_LAD3 B33 A60 ALWON <45>
CLKRUN# LAD3 VCI_OUT VCI_IN1#
<16,32,39> CLKRUN# A32 A63
SIO_EXT_SCI# CLKRUN# VCI_IN1# POWER_SW_IN#
<18> SIO_EXT_SCI# A33 B67
C741 GPIO100/nEC_SCI VCI_IN0# ACAV_IN
B1 ACAV_IN <22,52,53>
VCI_OVRD_IN DOCK_PWR_SW# R862 close to +1.05V_RUN_VTT
1 2 A1
VCI_IN3# U51& least 250mils
MASTER CLOCK
33P_0402_50V8J~D MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2
MEC_XTAL2 MEC_XTAL2 2 MEC_XTAL2_R XTAL1 PECI_VREF PECI_EC_R @ R862 0_0402_5%~D
1 A62 A48 1 2 PECI_EC <7>
@ R1068 1 XTAL2 PECI
<39> EC_32KHZ_ECE5048 2 0_0402_5%~D B62 DB Version 0.12 R863 43_0402_5%~D 1
GPIO160/32KHZ_OUT
2
@ R867 0_0402_5%~D I2S B17
Y6 I2S_DAT R1658 1 C737
B27 2 100K_0402_5%~D
VSS_RO
VR_CAP
I2S_CLK R1659 1
32.768KHZ_12.5PF_Q13FC1350000~D B34 B28 2 100K_0402_5%~D 0.1U_0402_25V6K~D
VSS[1]
VSS[4]
NC1 I2S_WS
AGND
A64 2
1
B MEC_XTAL1 NC2 +3.3V_ALW_PCH B
EP
B68
NC3
C743 MEC5055-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
C1
1 2 AC_PRESENT 2 1
GPIO024/THSEL_STRAP note R835 10K_0402_5%~D
33P_0402_50V8J~D 15mil least i.THSEL_STRAP =1 (selects thermistor on diode channel 1)
15mil ii.THSEL_STRAP = 0 (selects remote diode on diode channel +3.3V_ALW
1)
LCD_SMBCLK 2 1
1 R418 2.2K_0402_5%~D
LCD_SMBDAT 2 1
+3.3V_ALW
Reserve for ESD in 6/22 C740 R420 2.2K_0402_5%~D
4.7U_0603_6.3V6K~D DOCK_SMB_DAT 2 1
Place closed U51 C740 close to U51.B12 2 R838 2.2K_0402_5%~D
DOCK_SMB_CLK 2 1
PCH_PLTRST#_EC R841 2.2K_0402_5%~D
10K_0402_5%~D
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
+3.3V_ALW BAY_SMBDAT 2 1
1
R864
R858
R859
R860
R854 2.2K_0402_5%~D
R861
CE12 BAY_SMBCLK 2 1
0.1U_0402_25V6K~D +RTC_CELL R856 2.2K_0402_5%~D
1
2
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
100K_0402_5%~D
@ R850
@ DYN_TUR_CURRNT_SET# 2 1
2
R847
R848
R849
JDEG2 R1171 100K_0402_5%~D
1
1 JTAG_TDI
2
2 JTAG_TMS VCI_IN1#
3 2 1
2
3 JTAG_CLK R1156 100K_0402_5%~D
4
4 JTAG_TDO +5V_RUN
5
5 MSCLK
11 6
G1 6 MSDATA CLK_KBD
12 7 2 1
G2 7 HOST_DEB_TX @ R853 1
8 2 0_0402_5%~D HOST_DEBUG_TX R845 4.7K_0402_5%~D
8 HOST_DEB_RX @ R855 1
9 2 0_0402_5%~D HOST_DEBUG_RX +3.3V_ALW DAT_KBD 2 1
9 MSDATA R846 4.7K_0402_5%~D
10 1 2
10 R869 10K_0402_5%~D CLK_MSE 2 1
TYCO_1-2041070-0~D +3.3V_M 1 2 DDR_ON R851 4.7K_0402_5%~D
1
CONN@ R876 100K_0402_5%~D DAT_MSE 2 1
+3.3V_ALW 1 2 PCH_ALW_ON R852 4.7K_0402_5%~D
1
+3.3V_ALW R872 R880 100K_0402_5%~D
R875 C744 REV R893 10K_0402_5%~D 1 2 DOCK_POR_RST#
100K_0402_5%~D R881 100K_0402_5%~D +3.3V_RUN
Place closely pin A29
2
1
1 2 EN_INVPWR
240K 4700p X00
1
CLK_PCI_MEC FWP# R882 100K_0402_5%~D VOL_MUTE 2 @ 1
2
A R875 R871 R877 1 2 1.05V_0.8V_PWROK R1169 100K_0402_5%~D A
130K 4700p X01 PCH_PWRGD# <22>
1
33K_0402_5%~D 130K_0402_5%~D 240K_0402_5%~D R883 10K_0402_5%~D VOL_DOWN 2 @ 1
2
@ R885 @ 1 2 RESET_OUT# R1197 100K_0402_5%~D
62K 4700p X02
2
10_0402_1%~D D @ R879 @ R843 8.2K_0402_5%~D VOL_UP @
2 1
2
SYSTEM_ID RESET_OUT# 2 Q50 10K_0402_5%~D 1 2 CPU1.5V_S3_GATE R1118 100K_0402_5%~D
* 33K 4700p A00
4700P_0402_25V7K~D
BOARD_ID G SSM3K7002FU_SC70-3~D R889 100K_0402_5%~D
2
1 2 PCH_RSMRST#
1
8.2K 4700p S
3
R892 10K_0402_5%~D
@ C747
4.3K 4700p 1
1
DELL CONFIDENTIAL/PROPRIETARY
C742
4.7P_0402_50V8C~D C744
2 4700P_0402_25V7K~D @
2K 4700p 2
2
Compal Electronics, Inc.
1K 4700p PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
MEC5055
WWW.AliSaler.Com
SYSTEM_ID for BID function BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
Pop R877 240K for vPro and depop R871 PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
BOARD_ID rise time is measured from 5%~68%. * Pop R871 130K for non-vPro and depoip R877 LA-7902P
Date: Wednesday, March 07, 2012 Sheet 40 of 61
5 4 3 2 1
5 4 3 2 1
Touch Pad +3.3V_TP
BlueTooth
Pitch: 0.5
+3.3V_RUN
4.7K_0402_5%~D
4.7K_0402_5%~D
1
1
R903
R902
1 2
Follow CONN List_0609A +3.3V_RUN 1 2 BT_COEX_STATUS2
R1133 1K_0402_1%~D C748
JTP1 1 2 BT_PRI_STATUS 0.1U_0402_16V4Z~D
2
1 R1134 1K_0402_1%~D
L54 2 TP_DATA TP_CLK 1
<40> DAT_TP_SIO 1 BLM18AG601SN1D_0603~D 2
2
TP_DATA 3
L55 2 TP_CLK 3
<40> CLK_TP_SIO 1 BLM18AG601SN1D_0603~D 4
4
D JBT1 D
+3.3V_TP 5
5
10P_0402_50V8J~D
10P_0402_50V8J~D
PS2_DAT_TS 6 9 1
6 G1 1
10P_0402_50V8J~D
10P_0402_50V8J~D
1 1 1 1 PS2_CLK_TS 7 10 2
7 G2 <17> BT_DET# 2
C752
8 <34> COEX1_BT_ACTIVE 3
8 3
C751
C750
C749
BT_COEX_STATUS2 4
<32> BT_COEX_STATUS2 4
ACES_51522-00801-001 BT_PRI_STATUS 5
2 2 2 2 <32> BT_PRI_STATUS 5
CONN@ 6
<43> BT_ACTIVE 6
<39> BT_RADIO_DIS# 7
7
<34> COEX2_WLAN_ACTIVE 8
8
9
9
10
10
<17> USBP11- 11 11
<17> USBP11+ 12 12
13 G1
14 G2
TP_CLK +3.3V_ALW +3.3V_RUN
+3.3V_TP
PESD5V0U2BT_SOT23-3~D
TP_DATA ACES_50224-0120N-001
+3.3V_TP
100P_0402_50V8J~D
CONN@
33P_0402_50V8J~D
1 10K_0402_5%~D
@ C754
1 1 2 1 1
D37
C753
R904
R1161 0_0603_5%~D Follow CONN List_0609A
C755 1 2
0.1U_0402_16V4Z~D R1162 0_0603_5%~D
2 2 2
@
2
1
Place close to JTP1 Check JBT1 board connection
C C
Keyboard
EMI/RF transistion capacitors
+5V_ALW +5V_RUN
+5V_ALW +3.3V_ALW +VCC_GFXCORE +5V_ALW +5V_RUN
Follow CONN List_0609A
10P_0402_50V8J~D
1
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
Pitch: 1.0 1 1 1 CE29
CE21 CE31 CE30
@
JKB1 @ @ @ 2
2 2 2
1
<18> KB_DET# PS2_CLK_TS 1
2
+3.3V_ALW +5V_RUN PS2_DAT_TS 2
3
3
+3.3V_ALW 4
4
+5V_RUN 5
5
1 1 6
<40> BC_INT#_ECE1117 6
<40> BC_DAT_ECE1117 7
C756 C758 7
8
0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 8
<40> BC_CLK_ECE1117 9
2 2 9
10
10
11 +DOCK_PWR_BAR +DOCK_PWR_BAR +PWR_SRC +5V_ALW +5V_RUN +5V_ALW +5V_RUN
GND
12
GND
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
ACES_51524-0100N-001 1 1 1 1
B CE25 CE26 CE27 CE28 B
Place close to JKB1 CONN@
@ @ @ @
2 2 2 2
RSMRST circuit
+3.3V_ALW_PCH
+5V_ALW_PCH +3.3V_ALW
1
@R1623
@ R1623 1 2
R1622 0_0402_5%~D C288 0.1U_0402_25V6K~D
R1629 100K_0402_5%~D 1 2 PCH_RSMRST#_Q
33_0402_5%~D EC SIDE
U4
5
U7 R1655
2
PCH_RSMRST# 1 0_0402_5%~D
P
<40> PCH_RSMRST# B
1 4 1 2 PCH_RSMRST#_Q <14,16>
VCC O
0.01U_0402_16V7K~D
3 RSMRST# 2
RESET# A
G
1 2
GND TC7SH08FU_SSOP5~D
3
C289
RT9818A-44GU3_SC70-3~D
A 2 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Int KB/TP/BT/RSMRST
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 41 of 61
Rev
1.0
5 4 3 2 1
DC/DC Interface +1.5V_RUN Source
+3.3V_ALW_PCH Source
+PWR_SRC_S +3.3V_ALW Q49 +3.3V_ALW_PCH +1.5V_MEM Q59
+3.3V_ALW2 SI3456DDV-T1-GE3_TSOP6~D +PWR_SRC_S AO4304L_SO8 +1.5V_RUN
+3.3V_ALW2 8 1
D
6 7 2
S
1
10U_0603_6.3V6M~D
5 4 6 3
1
10U_0603_6.3V6M~D
2 R920 5 1
C769
R907 R905 1 1 470K_0402_5%~D R921
1
C760
100K_0402_5%~D 100K_0402_5%~D R908 20K_0402_5%~D
4
20K_0402_5%~D R909
2
ALW_ENABLE 100K_0402_5%~D 2
2
2 1.5V_RUN_ENABLE
2
3
DMN66D0LDW-7_SOT363-6~D
D D
2
1 1M_0402_5%~D
1
Q51B
DMN66D0LDW-7_SOT363-6~D
2.2M_0402_5%
1 1
R1619
R1610
ALW_ON_3.3V# 5
<20> ALW_ON_3.3V#
Q52B
@ R737 0_0402_5%~D C762 C771
6
1 2 3300P_0402_50V7K~D RUN_ON_ENABLE# 5 470P_0402_50V7K~D
<40,44> PCH_ALW_ON <40> RUN_ON_ENABLE#
4
2 2
DMN66D0LDW-7_SOT363-6~D
2
2
Q51A
4
6
<16,40> SIO_SLP_S5# 1 2 2 <11,16,27,35,39,47,48,49> SIO_SLP_S3# 1 2
Q52A
R745 @ 0_0402_5%~D @R735
@ R735 0_0402_5%~D
DMN66D0LDW-7_SOT363-6~D
1 <27,35,39,47,48> RUN_ON 1 2 2
@R744
@ R744 0_0402_5%~D
+1.05V_RUN Source
1
+PWR_SRC_S +1.05V_M +1.05V_RUN
+3.3V_SUS Source +3.3V_ALW Q54
SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS
1
+PWR_SRC_S Q63
D
R911 6 SI4164DY-T1-GE3_SO8~D
S
+3.3V_ALW2 470K_0402_5%~D 5 4 8 1
1
+1.05V_RUN_VTT
10U_0603_6.3V6M~D
2 +1.05V_M 7 2
10U_0603_6.3V6M~D
1 1 R930 6 3
1
C765
R914 330K_0402_5%~D 5 1
G
1
C772
20K_0402_5%~D +1.05V_RUN R931
3
R915 SUS_ENABLE 20K_0402_5%~D
4
100K_0402_5%~D 2 PJP7 1.05V_RUN_ENABLE
2
3
2
DMN66D0LDW-7_SOT363-6~D
1 2
2
4.7M_0402_5%~D
open
2
1
D
Q53B
100P_0402_50V8J~D
SSM3K7002FU_SC70-3~D
PAD-OPEN 1x3m
1
R1618
Q64
1M_0402_5%~D
SUS_ON_3.3V# 5 2
R1611
C @ C767 PJP8 G C
1
6
1 2 220P_0402_50V8J~D 1 2 S
<39> SUS_ON
4
C773
R739 0_0402_5%~D 2 open
2
Q53A PAD-OPEN 1x3m
2
2
SIO_SLP_S4# 1 2 2 For SSI
R746 0_0402_5%~D DMN66D0LDW-7_SOT363-6~D
<16,39,46>
@ w/ vpro: PJP7 open and PJP8 open
1
* w/o vpro: PJP7 open and PJP8 short.depop Q63
For PT, ST
* w/o vpro: PJP7 and PJP8 open. pop Q63
+3.3V_M Source +3.3V_M
+3.3V_ALW Q58 +3.3V_SUS
+PWR_SRC_S SI3456DDV-T1-GE3_TSOP6~D +3.3V_M +5V_RUN Source
1
+3.3V_ALW2
D
6 R916 +PWR_SRC_S +5V_ALW Q55
S
1
5 4 @ 2 1 39_0603_5%~D AO4478L_SO8 +5V_RUN
10U_0603_6.3V6M~D
R917 2 R206 0_0603_5%~D 8 1
1
1
470K_0402_5%~D 1 1 @ 7 2
2
C768
10U_0805_10V4Z~D
R918 R919 R906
+3.3V_M_CHG
6 3
G
1
100K_0402_5%~D 20K_0402_5%~D 470K_0402_5%~D 5 1
2
A_ENABLE For w/o vpro,+3.3V_M R910
2
C761
20K_0402_5%~D
change to +3.3V_SUS
2
4
3
DMN66D0LDW-7_SOT363-6~D
5V_RUN_ENABLE
2
SSM3K7002FU_SC70-3~D
2
Q57B
4.7M_0402_5%~D
220P_0402_50V8J~D
SSM3K7002FU_SC70-3~D
1
A_ON_3.3V# 5
1
1
D D
R1617
220P_0402_25V8J
6
C770
Q60
Q62
A_ON_3.3V# 2 2 1
4
Q57A G G
2
C763
B DMN66D0LDW-7_SOT363-6~D B
S S
2
3
SIO_SLP_A# 2
<16,39,48> SIO_SLP_A# 2
1
Discharge Circuit +3.3V_RUN Source
+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.5V_CPU_VDDQ +0.75V_DDR_VTT +3.3V_ALW Q61 +3.3V_RUN
+PWR_SRC_S AO4478L_SO8
8 1
1
10U_0805_6.3V6M~D
7 2
1
1
@ R929 R926 6 3 1
C764
@ R922 @ R928
@R928 @ R923 @ R924 39_0603_5%~D @ R925 220_0402_5%~D R927 R912 5 R913
1K_0402_1%~D 1K_0402_1%~D 1K_0402_1%~D 1K_0402_1%~D 39_0402_5%~D 22_0603_5%~D 470K_0402_5%~D 20K_0402_5%~D
2
4
2
+3.3V_ALWPCH_CHG
+5V_RUN_CHG
+1.5V_RUN_CHG
+3.3V_RUN_CHG
+1.5V_CPU_VDDQ_CHG
2
2
+3.3V_SUS_CHG
+1.05V_RUN_CHG
+DDR_CHG
3.3V_RUN_ENABLE
SSM3K7002FU_SC70-3~D
1M_0402_5%~D
220P_0402_25V8J
1
1
D
1
Q56
R1627
2 @
<7,11> RUN_ON_CPU1.5VS3#
C766
G
S
3
1
1
D D D D D 2
SSM3K7002FU_SC70-3~D
@ Q67
SSM3K7002FU_SC70-3~D
@ Q68
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
@ Q70
SSM3K7002FU_SC70-3~D
SSM3K7002FU_SC70-3~D
@
2
1
D D
SSM3K7002FU_SC70-3~D
@ Q65
SSM3K7002FU_SC70-3~D
@ Q66
Q69
Q72
RUN_ON_ENABLE# 2 2 2 2 2
1
SUS_ON_3.3V# ALW_ON_3.3V# 2 G G G G D G
2
Q71
G G S S S S 2 S
3
3
A G A
S S
3
S
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
5 4
WWW.AliSaler.Com NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
1
Sheet 42 of 61
Rev
1.0
5 4 3 2 1
Battery LED
HDD LED solution for White LED
+3.3V_ALW
Q83B +5V_ALW
+5V_ALW DMN66D0LDW-7_SOT363-6~D LED2
1
White
4 3 BAT2_MB_LED#_Q 1 2 BATT_WHITE_MB
<39> BAT2_LED#
R932 R949 1.2K_0402_5%~D
10K_0402_5%~D 3
1
5
3
Q74B SYS_LED_MASK#
2
DMN66D0LDW-7_SOT363-6~D Q74A 2
D59 DMN66D0LDW-7_SOT363-6~D Q125B
4 3 1 2 1 6 2 DMN66D0LDW-7_SOT363-6~D
<14> SATA_ACT# Yellow
D
SIDE emitter type white Led 4 3 BAT1_MB_LED#_Q 1 2 BATT_YELLOW_MB
D
RB751S40T1_SOD523-2~D Q75 R951 200_0402_5%~D LTW-326DSKS-5A_WHI-YEL
PDTA114EU_SC70-3~D
2
Note: LED current must be at least 2mA
5
LED3 SYS_LED_MASK#
<39> MASK_SATA_LED#
1
D62 1 2 SATA_LED_MB 2 1
1 2 SYS_LED_MASK# R934 910_0402_5%
<39> LED_SATA_DIAG_OUT#
RB751S40T1_SOD523-2~D
3
LTW-110DC5-C_WHITE Q125A
Note: LED current must be at least 2mA DMN66D0LDW-7_SOT363-6~D
1 6 BAT1_LED#_Q 1 2 BATT_YELLOW_LED
<39> BAT1_LED#
HDD_LED R953 300_0402_5%~D
2
3
MASK_BASE_LEDS#
Q80A
DMN66D0LDW-7_SOT363-6~D Q83A
1 6 2 DMN66D0LDW-7_SOT363-6~D
1 6 BAT2_LED#_Q 1 2 BATT_WHITE_LED
Q81 R958 1.3K_0402_5%
PDTA114EU_SC70-3~D
2
MASK_BASE_LEDS#
1
1 2 Check JLED1 connection
MASK_BASE_LEDS# R938 1.5K_0402_5%~D
Follow CONN List_0616E
+5V_ALW
JLED1
+3.3V_ALW +5V_ALW 1
1
2
+3.3V_ALW
WLAN LED solution for White LED 3
2
3
1 1 HDD_LED 4
BATT_WHITE_LED 4
5
C1002 C1003 BATT_YELLOW_LED 5
6 9
+5V_ALW WLAN_LED 6 G1
C 0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 7 10 C
7 G2
1
2 2 8
R937 8
100K_0402_5%~D ACES_51524-0080N-001
3 CONN@
Q78A
2
DMN66D0LDW-7_SOT363-6~D
<34,39> WIRELESS_LED# 1 6 2
Q79
PDTA114EU_SC70-3~D
2
MASK_BASE_LEDS# Breath LED
1
3
SIDE emitter type +5V_ALW
Q78B
DMN66D0LDW-7_SOT363-6~D
5 Q84A LED1
<41> BT_ACTIVE
DMN66D0LDW-7_SOT363-6~D
1 6 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_MB 1 2
<38,39> BREATH_LED#
4
1 2 WLAN_LED R957 820_0402_5%~D
1
R939 1.8K_0402_5%~D
R950 LTW-110DC5-C_WHITE
3
100K_0402_5%~D
SYS_LED_MASK# Note: LED current must be at least 2mA
2
Q84B
DMN66D0LDW-7_SOT363-6~D
4 3 BREATH_PWR_LED#_R 1 2
R959 1.2K_0402_5%~D
5
+3.3V_RUN +5V_ALW
Check JPWR1 connection
MASK_BASE_LEDS#
Follow CONN List_0616E
JPWR1
B B
1
POWER_SW#_MB 1
2
<40> POWER_SW#_MB 2
3
D23 BREATH_PWR_LED# 3
4
4
3 5
5
1 <29> DMIC_CLK1 6 9
6 G1
2 7 10
7 G2
8
PESD24VS2UT_SOT23-3~D <29> DMIC1 8
1
ACES_51524-0080N-001
C1004 CONN@
0.1U_0402_25V6K~D
2
LED Circuit Control Table
@
SW2
SYS_LED_MASK# LID_CL# NTC033-XJ1J-X260CM_4P
POWER_SW#_MB 3 1 Place SW2 between D23
Mask All LEDs (Sniffer Function) 0 X and JPWR1 Top side for
Mask Base MB LEDs (Lid Closed) 1 0 debug
4 2
+3.3V_ALW
Do not Mask LEDs (Lid Opened) 1 1
2
C778 0.1U_0402_25V6K~D SW1
2
1 2 SHORT PADS~D
Fiducial Mark @
5
@ FD1 U58
1 SYS_LED_MASK# 1
Place SW1 between D23
P
<39> SYS_LED_MASK# B
@ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14
O
4 MASK_BASE_LEDS# and JPWR1 BOT side for
1
FIDUCIAL MARK~D H_3P8 H_3P8 H_3P8 H_3P8 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_2P7 H_2P7 H_3P0 H_3P0X7P0 LID_CL# 2
<37,39> LID_CL# A
G
A debug A
1
@ FD2 TC7SH08FU_SSOP5~D
3
1
1
FIDUCIAL MARK~D
@ FD3 @ H15 @ H16 @ H17 @ H18 @ H19 @ H20 @ H21 @ H22 @ H23 @ H24 @ H25 @ H26 @ H27 @ H28
1 H_6P5 H_3P3 H_3P3 H_3P3 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
Compal Electronics, Inc.
1
@ FD4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
1
PWR/LED Conn/PAD/ME
WWW.AliSaler.Com
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
FIDUCIAL MARK~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Stand-off NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-7902P
Date: Wednesday, March 07, 2012 Sheet 43 of 61
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%
+3.3V_RTC_LDO
2
+COINCELL
Z4012
D D
JRTC1
1
1
2
ESD Diodes +RTC_CELL
2
2
3
G1
4
G2
1
PD4 ACES_50273-0020N-001
1
PD5 PD6 CONN@
PESD24VS2UT_SOT23-3~D PESD24VS2UT_SOT23-3~D PL2 +3.3V_ALW RB715FGT106_UMD3
1
FBMJ4516HS720NT_2P~D
1 2 PC3
Primary Battery Connector 1U_0603_10V6K
2
PL3
1
FBMJ4516HS720NT_2P~D Move to power schematic
100K_0402_5%
PBATT1 PBATT+_C 1 2 PBATT+
PR6
11
0.1U_0402_25V6
G2
1
10
G1
PC4
9 PR7
2
9 100_0402_5% PR9
8
2
8 Z4304 100_0402_5% PR8
7 1 2 PBAT_SMBCLK <40>
7 Z4305 100_0402_5%
6 1 2 PBAT_SMBDAT <40>
6 Z4306
5 1 2 PBAT_PRES# <39,53>
5
1
4
PC5 4 PQ1
3
2200P_0402_25V7K 3
2
2
2 FDN338P_G_NL_SOT23-3~D
1
1 PD8
SUYIN_200045MR009G188ZL 1 2 1 3
3
DOCK_SMB_ALERT# <40,42,56>
CONN@
DB2J31400L SOD323-2
2
2
@ PR10
C GND 1 2 C
<40,41,56> SLICE_BAT_PRES#
0_0402_5%
1
PC6
1500P_0402_7K~D
2
+3.3V_ALW
@ PR11 PU1
2.2K_0402_1%
2
1 2 <38> DOCK_PSID 1 6 GPIO_PSID_SELECT <39>
0_0402_5% NO IN
PR12
2 5 +5V_ALW
PL4 PR13 GND V+
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
S
NC COM PS_ID <40>
PQ2 TS5A63157DCKR_SC70-6~D
100K_0402_1%
2
FDV301N_G_NL_SOT23-3~D
G
2
+5V_ALW
PR14
10K_0402_1%
1
1
C
PQ3
PR15
2
B MMST3904-7-F_SOT323~D
E
15K_0402_1%~D
3
2
2
PR16
PR17
1 2
PSID_DISABLE# <39>
1
B B
10K_0402_5%
@
DC_IN+ Source
+PWR_SRC +PWR_SRC_S
3 1
+DC_IN +DC_IN_SS
PQ5
100K_0402_1%
0.1U_0402_25V6
0.22U_0603_25V7K
1
FDS6679AZ_G_SO8~D
1
PC9
PC8
PR19
1 8
PL5 S D
2 7
FBMJ4516HS720NT_2P~D S D
3 6
2
+DC_IN S D
1 2 4 5
2
G D PQ4
1
PR20 TP0610K-T1-E3_SOT23-3
1M_0402_5%~D
10U_0805_25V6K
0.022U_0603_50V7K
2
22K_0402_1%
100K_0402_5%
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
VSB_N_001
PC10
PR21
1 2
1
PC15
1VSB_N_003
1
PC11
PC13
PC14
PR22
0.1U_0402_25V6
2
1
PJPDC1 PR23
@ 4.7K_0805_5%~D
2
1
PS_HPW15003-05M101R 1 2
@0.1U_0402_25V6
SOFT_START_GC <56>
2
1
PC12
5
2
5 -DCIN_JACK 10K_0402_5% @ PR25 D
PR24
4
4
1
2VSB_N_002 PQ6
PC16
3 1 2
1M_0402_5%~D
<40,42> PCH_ALW_ON
2
3 +DCIN_JACK G SSM3K7002FU_SC70-3
2
2
2 0_0402_5%
PR26
1 S
.1U_0402_16V7K
3
1
PC17
CONN@
2
PL6 @
2
FBMJ4516HS720NT_2P~D
1 2
8/18 change from 7 pin to 5 pin
0.1U_0402_25V6
1
A A
PC18
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
LA-7902P
Date: Wednesday, March 07, 2012 Sheet 44 of 61
5 4 3 2 1
A B C D E
2VREF_6182
1
PC101
1 1U_0603_16V6K 1
2
@ PC120 @ PC121
2 1 2 1
22P_0402_50V8J~D 22P_0402_50V8J~D
PJP100 PR101 PR102
1 2 13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
@
PAD-OPEN 1x3m
+PWR_SRC +DC1_PWR_SRC PR103 PR104
20K_0402_1% 20K_0402_1% +DC1_PWR_SRC
FB_3V FB_5V 1
PL100 +3.3V_RTC_LDO 1 2 2
1UH_PCMB053T-1R0MS_7A_20%
2 1
+3.3V_ALW2
PR105 PR106
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@ PR100 130K_0402_1% 93.1K_0402_1%~D
1
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
PC103
PC119
0.1U_0402_25V6
1 2 1 2 ENTRIP2 ENTRIP1
1 2
1
PC100
PC102
PC106
PC118
PC104
PC105
PQ100 0_0402_5%
2
1
FDMC8884_POWER33-8-5 PU100
5
@ @
ENTRIP2
FB2
TONSEL
FB1
ENTRIP1
REF
1
PC107 PQ101
4 10U_0603_6.3V6M 25 FDMC8884_POWER33-8-5
P PAD
2
7 VO2 VO1 24 4
1
2
3
PC108 8 23 PC109
2 0.22U_0402_16V7K~D VREG3 PGOOD 0.22U_0402_16V7K~D 2
1 2 BST1_3V 1 PR107 2 BST_3V 9 22 BST_5V 1 PR108 2 BST1_5V 1 2
3
2
1
BOOT2 BOOT1
2.2_0603_5% 2.2_0603_5%
PL101 UG_3V 10 21 UG_5V PL103
4.7UH_FDSD0630-H-4R7M-P3_5.5A_20% UGATE2 UGATE1 4.7UH_FDSD0630-H-4R7M-P3_5.5A_20%
+3.3V_ALWP 1 2 LX_3V 11 PHASE2 PHASE1 20 LX_5V 1 2
+5V_ALWP
1
1
150U_B2_6.3VM_R35M
4.7_1206_5%
4.7_1206_5%
LG_3V 12 19 LG_5V
LGATE2 LGATE1
PR109
PR110
1 PQ102
SKIPSEL
150U_B2_6.3VM_R35M
FDMC8878_POWER33-8-5
VREG5
PC110
+
1
GND
VIN
NC
EN
2
PC111
4 4 +
2
SNUB_3V
SNUB_5V
13
14
15
16
17
18
PQ103
RT8205LZQW(2) WQFN 24P PWM FDMC7692S_POWER33-8-5 2
680P_0402_50V7K
1
2
3
3
2
1
680P_0402_50V7K
+5V_ALW2
PC112
1
PC113
3.3VALWP
1
TDC 5.185A
2
2
Peak Current 7.407A
1
300K_0402_1%
1U_0603_10V6K
1
+3.3V_ALW
PC115
PC114
OCP current 9.629A
PR111
4.7U_0805_10V6K
2
2
PD100
PR113 +DC1_PWR_SRC PR112
2
@ 499K_0402_1% 100K_0402_1%
1
1 2 2 1 @
+PWR_SRC
1
PC116
2VREF_6182
2
3 @ RLZ5.1B_LL34 0.1U_0402_25V6 3
ALW_PWRGD_3V_5V <40>
ENTRIP2
ENTRIP1
5VALWP
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D
TDC 4.415A
Peak Current 6.308A
3
OCP current 8.2A
PQ104B
PQ104A
5 2
4
PJP101
1 2
PR114 PAD-OPEN 1x3m
100K_0402_1% PJP102
1 2
+5V_ALW2 +5V_ALWP 1 2 +5V_ALW (5A,180mils ,Via NO.= 9)
1
PAD-OPEN 1x3m
PR115 PQ105 PJP103
2K_0402_1% PDTC115EU_SOT323-3
+3.3V_ALWP
1 2 +3.3V_ALW (4A,120mils ,Via NO.= 6)
<40> ALWON 1 2 2
PAD-OPEN 1x3m
@ PR116
3
<22> THERM_STP# 1 2
4 4
0_0402_5%
1U_0603_10V6K
1
PC117
Compal Electronics, Inc.
2
Title
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
A B
WWW.AliSaler.Com AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY
DEPARTMENT
BE USED BY
EXCEPT
OR DISCLOSED
AS AUTHORIZED
TO ANY THIRD
BY COMPAL
PARTY WITHOUT
ELECTRONICS,
PRIOR WRITTEN
INC. NEITHER
CONSENT
THISOFSHEET
COMPAL
NOR
ELECTRONICS,
THE INFORMATION
INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
IT CONTAINS
D
Size
Date:
Document Number
Wednesday, March 07, 2012
LA-7902P
E
Sheet 45 of 61
Rev
1.0
5 4 3 2 1
1.5Volt +/- 5%
TDC 9.74A
D D
Peak Current 13.915A 0.75Volt +/- 5%
OCP current 16.698A TDC 0.525A
Peak Current 0.75A
+PWR_SRC PJP200 OCP Current 0.9A
2 1 1.5V_B+
PJP204
PR200
@ PAD-OPEN 1x2m~D 1 2 BOOT_1.5V VLDOIN_1.5V 2 1 +1.5V_MEN_P
2.2_0603_5%
@ PAD-OPEN1x1m
DH_1.5V +0.75V_P
0.1U_0402_25V6
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.22U_0402_16V7K~D
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
SW _1.5V
PC278
PC281
PC274
PC276
PC279
1
2200P_0402_25V7K
2
1
DL_1.5V
PC280
PC263
16
17
18
19
20
PU200
VLDOIN
PHASE
UGATE
BOOT
VTT
2
PAD 21
4 15 1
+1.5V_MEN_P PQ200 LGATE VTTGND
FDMC8884_POW ER33-8-5
PR201 14 2
C PL200 22.6K_0402_1% PGND VTTSNS +V_DDR_REF C
1
2
3
1UH_FDSD0630-H-1R0M_11A_20% 1 2 CS_1.5V
1 2 13 CS GND 3
RT8207MZQW _W QFN20_3X3
+5V_ALW
5
PR202 1 2 PC272 12 4 +V_DDR_REF
VDDP VTTREF
1
1 5.1_0603_5%~D 1U_0603_10V6K
PC275
+ PC65 680P_0402_50V7K 1 2 VDD_1.5V 11 5 VDDQ_1.5V +1.5V_MEN_P
+5V_ALW
2
330U_2.5V_M VDD VDDQ
PGOOD
4
1
1SNUB_1.5V
TON
2 PC253 PC277
FB
S5
S3
1U_0603_10V6K 0.033U_0402_16V7~D
2
PQ210
1
2
3
10
6
FDMC7692S_POW ER33-8-5
PR203
+3.3V_ALW
4.7_1206_5% PR237
1
@ 0_0402_5%
PR204 1.5V_FB 2 1
2
100K_0402_1%
@ PC215
2 22P_0402_50V8J~D
2 1
Mode Level +0.75V_P +V_DDR_REF <40> 1.5V_SUS_PW RGD 1.5V_SUS_PW RGD
PR205
S5 L off off
1
@ 1M_0402_1%~D
1
S3 L off on PR206 1.5V_B+ 1 2 PR238
0_0402_5% 0_0402_5% PC282
B S0 H on on S5_1.5V @ .1U_0402_16V7K B
<40> DDR_ON 1 2
2
2
1
Note: S3 - sleep ; S5 - power off
1 2 PC255
<16,39,42> SIO_SLP_S4#
@ PR232 0_0402_5% @ .1U_0402_16V7K
2
<39> 0.75V_DDR_VTT_ON 1 2
@ PR236 0_0402_5%
+1.5V_MEN_P
PJP203
PJP201
+1.5V_MEN_P 2 2 1 1 +1.5V_MEM +0.75V_P 2 1 +0.75V_DDR_VTT
@ JUMP_1x3m
@ PAD-OPEN1x1m
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_MEN/+0.75V_DDR_VTT
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
Date: W ednesday, March 07, 2012 Sheet 46 of 61
5 4 3 2 1
A B C D
1 1
PR300
2 1
1.8Volt +/-5%
+3.3V_RUN
TDC 0.85A
10K_0402_5%
Peak Current 1.215A
1.8V_RUN_PWRGD <39> OCP current 1.458A
PU300 PL301
4
PJP301 1UH_NRS4018T1R0NDGJ_3.2A_30%
+3.3V_ALW 2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
PG
PVIN LX +1.8V_RUNP
22P_0402_50V8J
@ PAD-OPEN 1x2m~D 9 3
PVIN LX
1
1
1
4.7_0603_5%
PC301
PC300 PC307 8 SVIN
PR301
22U_0805_6.3VAM 0.1U_0402_25V6 PR302
2 2
6 1.8VSP_FB 20K_0402_1%
2
FB
47P_0402_50V8J
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
PC306
NC
NC
TP
PC302
PC303
@
11
2
SNUB_1.8VSP
1 2 EN_1.8VSP
<27,35,39,42,48> RUN_ON
1
1
.1U_0402_16V7K
@PR303
@ PR303 0_0402_5%
PC304
SYN470DBC_DFN10_3X3 PR305
1
@PR304
@ PR304 10K_0402_1%
47K_0402_5%
2
<11,16,27,35,39,42,48,49> SIO_SLP_S3# 1 2
2
@ PR306 0_0402_5%
680P_0402_50V7K
PC305
@
2
@
<Vo=1.8V> VFB=0.6V
Vo=VFB*(1+PR64/PR67)=0.6*(1+20K/10K)=1.8V
3 3
PJP300
2 1
+1.8V_RUNP +1.8V_RUN
@ PAD-OPEN 1x2m~D
4
DELL CONFIDENTIAL/PROPRIETARY 4
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.8V_RUN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 47 of 61
A B C D
WWW.AliSaler.Com
5 4 3 2 1
PJP400
D +V1.05SP_B+ D
2 1
+PWR_SRC
@ PAD-OPEN 1x2m~D
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
2200P_0402_25V7K
0.1U_0402_25V6
1
1
PC401
PC402
PC403
PC400
5
+3.3V_ALW
2
100K_0402_1%
1
PR400
4
PR401 PC404
2.2_0603_5% 0.1U_0402_25V6
1 2 1 2
2
PQ400
3
2
1
<40> 1.05V_A_PWRGD PU400 FDMC8884_POWER33-8-5
PR402 1 10 BST_+V1.05SP
82K_0402_1% PGOOD VBST
S0 mode be high level 1 2 TRIP_+V1.05SP 2 9 UG_+V1.05SP PL400
TRIP DRVH 1UH_FDSD0630-H-1R0M_11A_20%
C
EN_+V1.05SP 3 EN SW 8 SW_+V1.05SP 1 2 +1.05V_MP C
@PR403
@ PR403 0_0402_5%
5
1 2 FB_+V1.05SP 4 7
<16,39,42> SIO_SLP_A# VFB V5IN +5V_ALW
FDMC8878_POWER33-8-5
PR408 RF_+V1.05SP 5 6 LG_+V1.05SP 1
RF DRVL
1
@ 0_0402_5% 1 2
1 2 11 + PC406
SIO_SLP_S3# TP 220U_B2_2.5VM_R15M
PR409 4 PR404
<11,16,27,35,39,42,47,49>
@ 0_0402_5% TPS51212DSCR_SON10_3X3 PC405 4.7_1206_5%
1 2 1U_0402_6.3V6K 2
<27,35,39,42,47> RUN_ON
2
PQ405
1
3
2
1
1
PC407
@ .1U_0402_16V7K PR405 PC408
2
470K_0402_1% 680P_0402_50V7K
2
2
5@ for TM pop
6@ for vPOR pop
PR406
B 4.99K_0402_1% B
2 1
+1.05Volt +/- 5%
2
TDC 4.7A
PR407 Peak Current 6.5A
10K_0402_1%
OCP current 7.8A
1
+1.05V_MP 2 1 +1.05V_M
PJP401
@ PAD-OPEN 1x2m~D
A
DELL CONFIDENTIAL/PROPRIETARY A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 48 of 61
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
PJP500
+V1.05S_VCCPP_B+ 2 1
+PWR_SRC
@ PAD-OPEN 1x2m~D
+3.3V_RUN
2200P_0402_25V7K
4.7U_0805_25V6K~D
4.7U_0805_25V6K~D
0.1U_0402_25V6
1
1
PC501
PC502
PC503
PC500
2
D D
2
5
PR500
100K_0402_5%
1
PR502 PC504
2.2_0603_5% 0.1U_0402_25V6 4
<40,50> 1.05V_VTTPWRGD
1 2 1 2
PQ500
PU500 FDMC8884_POWER33-8-5
PR501 1 10 BST_+V1.05S_VCCPP
3
2
1
84.5K_0402_1% PGOOD VBST
1 2 TRIP_+V1.05S_VCCPP 2 TRIP DRVH 9 UG_+V1.05S_VCCPP PL500
1UH_FDSD0630-H-1R0M_11A_20%
EN_+V1.05S_VCCPP 3 8 SW_+V1.05S_VCCPP 1 2
@ PR503 0_0402_5% EN SW +1.05VTTP
1 2 FB_+V1.05S_VCCPP 4 7
<39> CPU_VTT_ON VFB V5IN +5V_ALW 1
1 2 RF_+V1.05S_VCCPP 5 6 LG_+V1.05S_VCCPP
SIO_SLP_S3# RF DRVL
1
+ PC511
PR307 0_0402_5% 11 PC505 220U_B2_2.5VM_R15M
<11,16,27,35,39,42,47,48> TP 1U_0402_6.3V6K
@ PR504
2
1
TPS51212DSCR_SON10_3X3 4.7_1206_5% 2
1
PC506
2
C C
@ .1U_0402_16V7K PR505 4 PC510
2
470K_0402_1% .1U_0402_16V7K
2
1
2
PC508
PQ501 680P_0402_50V7K @
3
2
1
2
FDMC7692S_POWER33-8-5 Local sense put on HW site
PR507
4.99K_0402_1% @ PR508 0_0402_5%
2 1 VTT_SENSE_FB 2 1 VTT_SENSE <10>
VSSIO_SENSE_R_FB 2 1 VSSIO_SENSE_R <10>
@ PR513 0_0402_5%
1
+3.3V_RUN +1.05Volt +/- 5%
PR509
@ 71.5K_0402_1%
TDC 6A
B VCCP_PWRCTRL = "High" , Vo = 1.05V (SNB) Peak Current 8.5A
B
2
VCCP_PWRCTRL = "Low" , Vo = 1V (IVB)
OCP current 10.2A
2
PR510 PR511
10K_0402_1% @ 10K_0402_5%
SSM3K7002FU_SC70-3
1
1
1
D
PQ502
2 From GPIO
VCCP_PWRCTRL <11>
G
S
3
1
@ PJP501
PR514 2 1
@ 10_0402_1% PC509
2
@ .01U_0402_16V7K @ PAD-OPEN 1x2m~D
2
PJP502
+1.05VTTP 2 1 +1.05V_RUN_VTT
A @ PAD-OPEN 1x2m~D DELL CONFIDENTIAL/PROPRIETARY A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.05V_RUN_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 49 of 61
5 4 3 2 1
WWW.AliSaler.Com
5 4 3 2 1
VID [0] VID[1] VCCSA Vout
D 0 0 0.9V D
The 1k PD on the VCCSA VIDs are empty. 0 1 0.8V
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability. 1 0 0.725V
1 1 0.675V
PR78
1K_0402_5%
2 1
output voltage adjustable network
+3.3V_RUN @ PR90
1 2 VCCSA_VID_1 <11>
100K_0402_5%
0_0402_5%
1
PR79
@ PR91
1 2
VCCSA
VCCSA_VID_0 <11>
TDC 4.2A
2
@ PR80 0_0402_5%
+VCCSA_PWRGD
<40> VCCSAPWROK
2 1 PR81 Peak Current 6A
1K_0402_5%
+VCCSA_PWRGD
0_0402_5% 2 1 OCP current 7.2A
+5V_ALW
1U_0603_10V6K
2
PC74
PR82
10_0402_1% @ PR83
1
2 1 +VCCSA_EN 1 2 1.05V_VTTPWRGD <40,49>
PC75
2.2U_0603_10V7K 0_0402_5%
C 1 2 C
18
17
16
15
14
13
PU7
PR84 PC76
VID1
VID0
PGOOD
EN
V5FILT
V5DRV
2.2_0603_1% 0.1U_0402_25V6
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL15
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSA_P
20
PGND
.1U_0402_16V7K
22U_0805_6.3V6M
10
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
2200P_0402_25V7K
SW
1
21
PGND
2
PC77
PC79
PC81
PC82
PC83
PC84
PC85
2200P_0402_25V7K
TPS51461RGER_QFN24_4X4~D @ 680P_0402_50V7K
PC80
9
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
1 2
SW
22
1
VIN
1
@
8
SW PR85
PC86
PC87
PC88
PC89
23
+3.3V_ALW
2
VIN @ 4.7_1206_5%
PJP19 7
2
SW
2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
VIN
@ PAD-OPEN 1x2m~D 25
COMP
MODE
TP
SLEW
VOUT
VREF
GND
1
6
2 1
PR86
22K_0402_5%
PR87
100_0402_5%
PC90 2 1
2 1
B
GNDA_VCCSA B
0.22U_0402_16V7K~D
2 1 2 1 @ PR88
2 1 VCCSA_SENSE <11>
0.01U_0402_25V7K
PC91 PR89
2
3300P_0402_50V7K 5.1K_0402_1% 0_0402_5%
PC92
PJP20
+VCCSA_P 1 2
+VCC_SA
PAD-OPEN 4x4m
PJP21
2 1
PAD-OPEN1x1m
GNDA_VCCSA
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
WWW.AliSaler.Com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_SA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 50 of 61
5 4 3 2 1
5 4 3 2 1
PR701 PC701
2K_0402_1% 330P_0402_50V7K
VCC_GFXCORE
Local sense put on HW site 2 1 2 1 TDC 21.5A
PR702 PC702 Peak Current 33A
2 1 2 1 2 1
OCP current 57.18A
+VCC_PWR_SRC
150K_0402_1%~D
@ PC703 2.61K_0402_1% PR703 150P_0402_50V8F~D
Load line -3.9mV/A PJP702
PR705
2 1 130K_0402_1%
<11> VCC_AXG_SENSE PR704 PC704 PC705 +GFX_PWR_SRC 2 1
330P_0402_50V7K 2 1 2 1 1 2
@ PAD-OPEN1x1m
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
<11> VSS_AXG_SENSE PC706 499_0402_1% 390P_0402_50V7K 68P_0402_50V8J~D
5
1 2
1
PC746
PC747
PC749
PC752
0.01U_0402_50V7K
D D
2
4
PQ708
VSUMG+ S TR MDU1516URH 1N POWERDFN56-8
2.61K_0402_1%
@PR708
@ PR708
3
2
1
1
0.022U_0402_25V7K 1 2 IMVP_PWRGD
0.068U_0402_16V7K
.1U_0402_16V7K
PR707
11K_0402_1%
0_0402_5% PL704
1
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
+VCC_GFXCORE
1
1
PR709
PC707
PC708
PC709
10KB_0402_5%_ERTJ0ER103J
4 1
1 2
680P_0402_50V7K
@ PR710
5
649_0402_1%~D PQ711 PQ710 GP1_SW GP1_Vo
SIR818DP-T1-GE3_POWERPAK8-5
SIR818DP-T1-GE3_POWERPAK8-5
3 2
2
PC751
1 2
2
2
PH700
LGATE1G
10K_0603_1%
3.65K_0603_1%
PC710 PC750
10K_0402_1%
PR711 3300P_0402_50V7K PHASE1G 0.22U_0402_16V7K~D
2
1 1
1_0402_5%
PR761
PR758
PR759
PR762
365_0402_1% 4 4
PGOODG
4.7_1206_5%
VSUMG- 1 2 UGATE1G
1
PR763
.1U_0402_16V7K
PR760
@ BOOT1G 2.2_0603_5% @
1
1
@ ISEN2G
3
2
1
3
2
1
PC711
@ PC712
2
2 1
2
2
VSUMG+ VSUMG-
40
39
38
37
36
35
34
33
32
31
VSUMG- 0.22U_0402_16V7K~D PU700 BOOT2
@ PC713
ISUMNG
RTNG
FBG
COMPG
PGOODG
PWM2G
LGATE1G
PHASE1G
UGATE1G
BOOT1G
2 1 UGATE2 ISEN1G
PR712
1 2 2 1 0.22U_0402_16V7K~D PHASE2
PH701
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE 1 2 ISEN1G
1
2
ISUMPG BOOT2 30
29 LGATE2 +5V_ALW VCC_core
+5V_RUN @PR713
@ PR713 0_0402_5% ISEN2G 3
ISEN1G UGATE2
28 1 2 TDC 36A
PR7151 NTCG ISEN2G PHASE2 @ PR714 0_0402_5%
2 4 27
C
27.4K_0402_1% SCLK 5
NTCG
SCLK
LGATE2
VCCP 26 VCCP 1 2 Peak Current 53A C
<10> VIDSCLK @PR716
@ PR716
1 0_0402_5%
2 ALERT# 6 25 PR717
7
ALERT# VDD
24 PWM3 1_0603_5% OCP current 64A
@PR718
@ PR718 0_0402_5% SDA PWM3
<10> VIDALERT_N 1 2 8 23 Load line -1.9mV/A
VR_EN VR_HOT# LGATE1 LGATE1
9 VR_ON PHASE1 22 2 1
<10> VIDSOUT @PR719
@ PR719
1 0_0402_5%
2 SDA NTC 10 NTC UGATE1 21 Icc_Dyn_VID1 43A
ISEN3/FB2
PHASE1 PR720
PGOOD
@PR721
@ PR721
1 0_0402_5%
2 VR_HOT# 1_0603_5%
BOOT1
ISUMN
ISUMP
1
COMP
ISEN2
ISEN1
UGATE1
+PWR_SRC
RTN
@PR722
@ PR722 0_0402_5% 41 PC714 PC715 PL700
FB
<39> IMVP_VR_ON TP 1U_0603_10V6K 1U_0603_10V6K FBMA-L11-453215-121LMA90T_2
<7,40,52> H_PROCHOT# 1 2
2
+VCC_PWR_SRC 1 2
11
12
13
14
15
16
17
18
19
20
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
<14,40> 1.05V_0.8V_PWROK 1 2 ISL95836HRTZ-T_TQFN40_5X5~D
+1.05V_RUN_VTT
5
@PR724
@ PR724 @PR723
@ PR723 0_0402_5%
1 2 BOOT1 PQ700
PGOOD
1
PC716
PC717
PC700
PC753
PR725 COMP
43P_0402_50V8J~D
0_0402_5%
ISEN3
ISEN2
ISEN1
1 2 2 1
PC719
PH702
2
1
3.83K_0402_1% 470K_0402_5%_ TSM0B474J4702RE @PR726
@ PR726
1 0_0402_5%
2 IMVP_PWRGD <39> UGATE2 4
PR727 PR728 1.91K_0402_1%
2
27.4K_0402_1% 2 1
2 1 +3.3V_RUN S TR MDU1516URH 1N POWERDFN56-8 PL701
3
2
1
0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
PHASE2 4 1
+VCC_CORE
680P_0402_50V7K
PC720 22P_0402_50V8J 3 2
PC725
PR730 54.9_0402_1% COMP PR729 PQ703 PQ702
SIR818DP-T1-GE3_POWERPAK8-5
SIR818DP-T1-GE3_POWERPAK8-5
2 1
BOOT2 2 1 1 2
2 1 SCLK @ PR732
@PR732 0_0402_5% 2.2_0603_5% P2_SW P2_Vo
2
1 2 PC721
+5V_RUN PC722 0.22U_0402_16V7K~D PR733 PR734
1
4.7_1206_5%
@ PR735 75_0402_5% PR736 390P_0402_50V7K PC723 LGATE2 4 4 ISEN21 2 2 1ISEN1
PR731
2 1 ALERT# 2 1 2 1 2 1 10K_0603_1% 10K_0402_1%
B B
@ PC724 499_0402_1% 47P_0402_50V8J
PR737 130_0402_1% 2 1 PR738
3
2
1
3
2
1
2
2 1 SDA 0.22U_0402_6.3V6K VSUM+ 1 2
PC726 PR742 3.65K_0603_1%
VSUM- 2 1 PR740 PR741 PC727 21K_0402_1% PR743
0.22U_0402_6.3V6K 2 1 2 1 2 1 1 2 VSUM- 2 1
PC728 1_0402_5%
2 1 2K_0402_1% 130K_0402_1% 150P_0402_50V8F~D
0.22U_0402_6.3V6K +VCC_PWR_SRC
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
100U_25V_M~D
100U_25V_M~D
0.1U_0402_25V6
PR744 PC729 1 1
5
1 2 1 2
+
PC730
+
PC731
PQ704
1
PC733
PC734
PC736
PC754
2K_0402_1% 680P_0402_50V7K
VSUM+
0.033U 16V K X7R 0402
2 2
.1U_0402_16V7K
0.22U_0402_16V7K~D
2
11K_0402_1%
2.61K_0402_1%
@ UGATE1 4
PC737
1
PR746
10KB_0402_5%_ERTJ0ER103J
1 2
VCCSENSE <10>
1
330P_0402_50V7K S TR MDU1516URH 1N POWERDFN56-8 PL702
3
2
1
PC741 0.36UH_FDUE104J-H-R36M=P3_33A_20%~D
VSSSENSE <10>
12
1 2 PHASE1 4 1
+VCC_CORE
PC738 2
PC739 2
680P_0402_50V7K
PR747
PH703
PC740
0.01U_0402_50V7K
SIR818DP-T1-GE3_POWERPAK8-5
3 2
2
PC745
PR749 PQ706 PQ707 P1_Vo
SIR818DP-T1-GE3_POWERPAK8-5
PR750 BOOT1 2 1 1 2 P1_SW
2
VSUM- 2 1 2.2_0603_5%
2
365_0402_1% PC742
0.22U_0402_16V7K~D PR752 PR753
Local sense put on HW site
1
4.7_1206_5%
.1U_0402_16V7K
LGATE1 4 4 ISEN11 2 2 1 ISEN2
1
PR751
PR754 10K_0603_1% 10K_0402_1%
PC743
1 2 1 2 PC744
3300P_0402_25V7K
2
649_0402_1%~D PR755
3
2
1
3
2
1
2
A A
VSUM+1 2
3.65K_0603_1%
PR757
VSUM- 2 1
1_0402_5%
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
Title
5 4
WWW.AliSaler.Com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size
Date:
Document Number
Wednesday, March 07, 2012
+VCC_CORE
LA-7902P
1
Sheet 51 of 61
Rev
1.0
A B C D
ISL88731C 11@ @ PD1300
2 1 PL1300
BQ24747 22@ ES2AA-13-F
1UH_PCMB053T-1R0MS_7A_20%
2 1
PR1301
+SDC_IN 0.01_1206_1%~D +PWR_SRC CHAGER_SRC
1 PJP800
2 4 1 1 2
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
+DC_IN_SS
5 3
@0.1U_0402_25V6
1
PQ1300 @ PAD-OPEN 4x4m
PC1346
PC1344
PC1343
PC1345
3 2
47P_0402_50V8J
0.1U_0402_25V6
SI7121DN-T1-GE3_POWERPAK8-5
1
PC1300
PC1301
PC1302
4
2
PR1300
2
1
1 2 PR1302 D
DC_BLOCK_GC <53>
0_0402_5% 1 2 2 PQ1301
1 <53> CSS_GC 1
@ 0_0402_5% G NTR4502PT1G_SOT23-3~D
1
@ D S
3
2 PQ1303A
G AP2623GY-HF 2P SOT26-6
PQ1302 S
PD1302
S
NTR4502PT1G_SOT23-3~D
D
5 6 DOCK_DCIN_IS+ <38>
E2 AC_OK=17.7 Volt +DOCK_PWR_BAR 2
CSSN_1
CSSP_1
1
G
1
PR1313 PQ1303B
3 PR1303 AP2623GY-HF 2P SOT26-6
TI bq24745 = 316K +DC_IN_SS 10K_0402_5%
10_0402_5%
S
Intersil ISL88731 = 226K
D
2 1 2 4
10_0402_5%
100K_0402_1%
BAT54CW_SOT323~D DOCK_DCIN_IS- <38>
PR1304
11@1
1
11@
PR1305
PR1306
100K_0402_1%
1
1
11@
G
3
+SDC_IN
MAX8731A_LDO MAX8731_REF PC1303 PC1304
PR1307
0.1U_0402_25V6 0.047U_0402_25V7K
11@ 10K_0402_1%
22@ 10K_0402_5%
11@ 226K_0402_1%~D
2
<53> +CHGR_DC_IN 1 2 1 2 11@ 1 2 1 2 PR1312
2
1
1
PC1305 1 2 DK_CSS_GC <53>
PR1309 0.1U_0402_25V6 0_0402_5%
PR1310
PR1311
2
@ 1_0805_5%~D 11@ @
PR1313
GNDA_CHG
28
27
1
PC1306 GNDA_CHG PU1300 ICOUT
2
0.1U_0805_50V7K
CSSN
ICREF
CSSP
2 1 +DCIN 22 26
1
DCIN ICOUT
2
PR1317 PR1318
1
2 49.9K_0402_1%
1 2 2.2_0603_1% PR1319
ACIN
1PS76SB21 SOD323-2
BOOT
25 1 2 BOOT_D 4.7_0603_5% PC1309
BOOT
1 PR1320 2 13 11@ 1U_0603_10V6K
11@ 15.8K_0402_1%
2
<22,40,53> ACAV_IN ACOK
1
0_0402_5% 11@
PC1310
0.1U_0402_25V6
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_25V7K
1
1
1
@
PD1301
2 1 11
VDDSMB
5
PC1307
PR1316
1
0.01U_0402_25V7K GNDA_CHG PQ1304
PC1313
PC1314
PC1315
10
2
SCL
PC1312
22@ 2
GNDA_CHG 9 21 MAX8731A_LDO 1 2
2
2
+5V_ALW SDA VDDP
2 2
GNDA_CHG 14 PC1311 4
NC CHG_UGATE 1U_0603_10V6K
24
MAX8731_IINP UGATE
8
VICM
1
23 2 1 +VCHGR_B
@ 3300P_0402_50V7K
PC1316 PHASE PR1322 S TR MDU1516URH 1N POWERDFN56-8
6
3
2
1
FBO
1
.1U_0402_16V7K 11@ 0_0603_5%
2
1 2 5
EAI PC1317
1
GNDA_CHG PR1323 220P_0402_50V7K~D CHG_LGATE
PC1319
2 1 1 2 4 20
2.2K_0402_1%
200K_0402_5% PC1318 PR1324 EAO LGATE PR1326 +VCHGR
<40> CHARGER_SMBCLK
56P_0402_50V8~D
1
22@ 2200P_0402_25V7K 7.5K_0402_5% PL1301 0.01_1206_1%~D
PR1325
PC1320
2
<40> CHARGER_SMBDAT 22@ 22@ 5.6UH_FDVE1040-H-5R6M-P3_9.2A_20%~D
2
2 11@
MAX8731_REF 3 19 2 1+VCHGR_L
4 1
VREF PGND
18
PC1321 CSOP
3 2
22@1
<22> MAX8731_IINP
1
22@
120P_0402_50VNPO~D 1 2 7 17
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
CE CSON
5
1 2 22@ PR1327
10_0402_5%
@ 8.45K_0402_1%
220P_0402_50V7K~D
1
1
FDMC8878_POWER33-8-5
10K_0402_5% 15 VFB 1 PR1328 2 PC1322
PR1330
+VCHGR
@.1U_0402_16V7K
2
VFB
1
1
Vref 22@ 680P_0402_50V7K
PC1330
PC1331
PC1332
12
0.01U_0402_25V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
GND
2 11@
100_0402_5% PR1331
PR1329
PC1329
16
TI bq24747 = 3.3V NC
1
1
PC1327 0_0402_5%
PC1323
PC1325
PC1326
29
22@2
2
TP
2
Intersil ISL88731C = 3.2V 1U_0603_10V6K @
PQ1305
PC1324
PC1328
4
2
2
22@ PR1332
11@ 2
11@ 2
2
VDDP
1
ISL88731C_QFN28_5X5~D 4.7_1206_5%
TI bq24747 = 6V 11@ PJP801
1 2 PC1333
3
2
1
1
Intersil ISL88731C = 5.1V @ 0.1U_0402_25V6
22@ 1 2 1 2 1 2
@ PAD-OPEN1x1m
GNDA_CHG GNDA_CHG PC1334 PC1335
GNDA_CHG 0.22U_0402_16V7K @ 0.1U_0402_25V6
Maximum charging current is 7.2A 11@
GNDA_CHG
MAX8731_REF
+5V_ALW
+DC_IN MAX8731_REF
@ 100P_0402_50V8J
@0.01U_0402_25V7K
DYN_TUR_CURRENT_SET# PR1333
10K_0402_1%
3
1M_0402_1%~D 3
47K_0402_1%~D
232K_0402_1%~D
1
1
PC1336
PC1337
221K_0402_1%~D H_PROCHOT# <7,40,51> 1 2
2
PR1334
PR1335
PR1336
PR1338
+5V_ALW
65W High
2
2
+3.3V_ALW2
+5V_ALW PR1340 PR1339
2
1.8M_0402_1% 0_0402_5%
1
8
1 2 PU1304B
90W Low @
1
5 PR1342
P
+
1
PR1341 7 1 2
O ACAV_IN_NB <39,40,53>
2N7002DW-T/R7_SOT363-6~D
2N7002DW-T/R7_SOT363-6~D
150K_0402_1%~D PR1343 6 0_0402_5%
22.6K_0402_1%
100P_0402_50V8J
42.2K_0402_1%~D
41.2K_0402_1%~D
-
8
G
PQ1307B
20K_0402_1% PU1304A @
100P_0402_50V8J
6
1
PQ1307A
MAX8731_IINP 1 2 3 LM393DR_SO8~D
P
2
4
+
1
PC1338
PR1346
PR1347
PC1339
PR1348
1
O
2 5
-
G
2
220P_0402_50V7K~D
2
LM393DR_SO8~D @
4
2
1
PC1340
66.5K_0402_1%
150K_0402_1%~D
+3.3V_ALW
100P_0402_50V8J
1
2
1
PR1349
PR1350
PC1341
1
2
PR1351
+3.3V_ALW 100K_0402_5%
1
D PC1342
<40> DYN_TUR_CURRNT_SET# 2 0.1U_0402_25V6
2
G
S 2 1
3
PQ1310
2N7002KW 1N SOT323-3
5
PU1302
1
D
1
P
B
4 2 ACAV_IN <22,40,53>
O G
2 PROCHOT_GATE <39>
A
G
S 2N7002KW 1N SOT323-3
3
To preset system to throtlle
Adapter Protection Circuit for Turbo Mode PQ1306
3
4
TC7SH08FU_SSOP5~D switching from AC to DC 4
DELL CONFIDENTIAL/PROPRIETARY
PU1300 22@ PR1313 22@ PR1325 22@ PC1334 22@ PR1330 22@ PR1304 22@ PR1305 22@ PC1304 22@ PR1322 22@
Compal Electronics, Inc.
Title
BQ24747 316k_0402_1% 4.7k_0402_1%
A
0.1U_0402_25V6 0_0402_5% 0_0402_5% 0_0402_5%
WWW.AliSaler.Com
0.1U_0402_25V6 1 +-5% 0603
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Size
Date:
Document Number
Charger
Wednesday, March 07, 2012
D
LA-7902P
Sheet 52 of 61
Rev
1.0
5 4 3 2 1
S2AA-13-F SMA
PD17
2 1
PQ43
D D
+DOCK_PWR_BAR 8 1
D S
7 2
D S
6 3
D S
5 4
0.47U_0805_25V7K~D
D G
1
FDS6679AZ_SO8~D
PC187
PR207
330K_0402_5%
2
2
@ PR208
2 1STSTART_DCBLOCK_GC
0_0402_5%
PD18
2
1
3
PDS5100H-13_POWERDI5-3~D
1 PR209
2
PQ44 PBATT+ PQ45 330K_0402_5% PQ46
SI7121DN-T1-GE3_POWERPAK8-5 FDS6679AZ_SO8~D 8 1
D S
1 1 8 7 2
S D PBATT_IN_SS D S
2 2 7 6 3 +PWR_SRC
+VCHGR S D D S
5 3 3 6 5 4
S D D G
1
4 5
1K_1206_5%
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
@ PR210 G D FDS6679AZ_SO8~D
PR211
1
PC1347
2 1
4
0_0402_5%
PC188
PC189
C C
2
1
@ PR212 PC190
1U_0603_25V6
1 2 BLK_MOSFET_GC 1U_0603_25V6
1
0_0402_5%
PC191
2
2
@ PR214 0_0402_5% @ PR213
+DOCK_PWR_BAR 1 2 DK_PWR_BAR 0_0402_5%
1
1 2 3301_DC_IN_SS @ PR215
+DC_IN_SS
1
@ PR216 0_0402_5% 0_0402_5%
<52> +CHGR_DC_IN DSCHRG_MOSFET_GC
2
+DC_IN 1 2 CD3301_DCIN
PR217 47_0805_5%~D
1
PC192
0.1U_0603_50V4Z
2
P50ALW 1
36
35
34
33
32
31
30
29
28
2 +5V_ALW
<44> SOFT_START_GC PU11 @ PR218 0_0402_5%
PR219 100K_0402_5%
GPIO Input from NB
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
DC_IN_SS
+3.3V_ALW2 1 2 CD_PBATT_OFF 1 2 SLICE_BAT_ON <39>
@ PR220 0_0402_5%
1 2 ACAVDK_SRC 1 2
Embedded Controller
<38> ACAV_DOCK_SRC# DOCK_AC_OFF <38,39>
@ PR221 0_0402_5% 1 27 @ PR222
DC_IN P50ALW 0_0402_5%
2 26 1 2
ERC1 SS_GC PBATT_OFF DK_AC_OFF
+SDC_IN 1 2 3 25
B
@ PR224 0_0402_5% ERC1 DK_AC_OFF_EN 3301_ACAV_IN_NB 1M_0402_5%~D B
4 24 1 2 ACAV_IN_NB <39,40,52>
ACAVDK_SRC ACAV_IN_NB @ PR225 0_0402_5% PR223
5 23
CD3301_SDC_IN GND GND DK_AC_OFF_EN
6 22 1 2 DOCK_AC_OFF_EC <39>
SDC_IN DK_AC_OFF_EN SL_BAT_PRES# @ PR226 0_0402_5%
7 21
<52> DC_BLOCK_GC ACAVIN DC_BLK_GC SL_BAT_PRES# BLKNG_MOSFET_GC
8 20
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC
19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
<22,40,52> ACAV_IN 1 2
SS_DCBLK_GC
@ PR227 0_0402_5%
DK_CSS_GC
1 2 SLICE_BAT_PRES# <38,39>
PWR_SRC
@ PR229 0_0402_5%
CSS_GC
P33ALW
37
TP
ERC3
ERC2
1 2 1 2
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
@ PR228 0_0402_5% @ PR230 0_0402_5%
S IC CD3301ARHHR QFN 36P CONTROL LOGIC
10
11
12
13
14
15
16
17
18
0.1U_0402_25V6
<52> CSS_GC P33ALW 1 2
ERC2
<52> DK_CSS_GC +3.3V_ALW
@ PR231 0_0402_5%
1
ERC3
PC193
EN_DK_PWRBAR 1 2 EN_DOCK_PWR_BAR <39>
2
0.047U_0402_25V7K
@ PR233 0_0402_5%
0.1U_0402_25V6
1 2
PC194
STSTART_DCBLOCK_GC 1M_0402_5%~D
PC195
@ PR234
2
3301_PWRSRC 1 2 +PWR_SRC
@ @ PR235 0_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
WWW.AliSaler.Com
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 53 of 61
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
D D
1 1 1 1 1
PC1153 PC1163 PC1164 PC1168 PC1169
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D
2
10U_0805_4VAM~D +VCC_GFXCORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1
PC1111
PC1112
PC1113
PC1114
PC1115
PC1116
PC1117
PC1118
PC1170 PC1171 PC1108 PC1109 PC1110
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2 2 2 2
+1.05V_RUN_VTT
+VCC_CORE +1.05V_RUN_VTT
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
PC1124
PC1125
PC1126
PC1127
PC1128
PC1129
PC1130
PC1131
PC1132
PC1134
PC1119 PC1120 PC1121 PC1122 PC1123
2 2 2 2 2 2 2 2 2 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 1 1 1 @1 @1 1 1
2 2 2 2 2
PC1135
PC1136
PC1137
PC1138
PC1139
PC1140
PC1141
2 2 2 2 2 2 2
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
22U_0805_6.3VAM
C 1 1 1 1 1 1 1 C
1 1 1 1 1 @ @ @ @ @
PC1147
PC1148
PC1149
PC1150
PC1151
PC1152
PC1154
PC1143 PC1144 PC1145 PC1146 PC1101
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 2 2 2 2 2 2 2
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
2 2 2 2 2
330U 2V M D2 LESR6M
330U 2V M D2 LESR6M
1 1
1
PC1157
PC1158
+ +
PC1500
PC1501
PC1502
PC1503
PC1504
2
2
2 2
330U 2V M D2 LESR6M
330U 2V M D2 LESR6M
1 1
1 1 1 1 1
PC1165
PC1166
+ +
PC1102 PC1103 PC1104 PC1105 PC1106
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2 2 2
1
PC1107
22U_0805_6.3VAM
2
+VCC_CORE
B B
1 1 1 1
+ + @ PC1173 + PC1174 + @ PC1175
PC1187
330U 2V M D2 LESR6M 470U_D2_2VM_R4.5M 330U 2V M D2 LESR6M 470U_D2_2VM_R4.5M
2 3 2 3 2 3 2 3
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
330U 2V M D2 LESR6M
330U 2V M D2 LESR6M
1 1
1
+ +
PC1400
PC1401
PC1402
PC1403
PC1404
PC1176
PC1177
2
2 2
A A
Compal Electronics, Inc.
Title
PROCESSOR DECOUPLING
WWW.AliSaler.Com
Size Document Number Rev
1.0
LA-7902P
Date: W ednesday, March 07, 2012 Sheet 54 of 61
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D
1 44 Power 8/18 Compal ME design change. PJPDC1 change from 7pin to 5pin X01 D
2 45 Power 8/18 Compal Main and 2nd IC common setting. De-pop PD100,PR113,PR111 X01
3 45 Power 8/18 Compal Prevent Jitter issue. Add PC120,PC121,PC215 parallel with X01
46 PR101,PR102,PR207
PU700 VCCP and VDD change form +5V_RUN
4 51 Power 8/18 Compal Prevent output voltage glitch when power up. to +5V_ALW X01
5 53 Power 8/18 Dell Change net name same as E4. X01
Change net name PBATT to SLICE_BAT_ON.
6 50 Power 8/18 Compal Reserve 0 ohm resistance for test. Add PR90, PR91 X01
C C
7 54 Power 8/31 Compal Reserve cap for improve transient response. Reserve PC1176 X01
Change PQ4, PC1153, PC1163, PC1164, PC1168,
8 54 Power 8/31 Compal Change to green P/N. PC1169, PC1170, PC1171, PC1108, PC1109, PC1110, X01
PC1187, PC1173, PC1174, PC1175, PC1157, PC1158
PQ1310, PQ1306, PC719 to green P/N
Change 6@ to pop for PC400~PC406, PC408, PL400,
9 48 Power 9/1 Dell For support TL+TM PQ400, PQ405, PR400~PR407, X01
PU400. 5@ to @ for PR408.
10 49 Power 9/1 Compal For fix 1.05V_RUN_VTT on 1.05V Depop PR509, PR511, PQ502. X01
Change PR507 to 4.99k.
B B
11 45 Power 8/30 Compal For reduce EMI radiation. Pop PL100, PL1300 X01
52
12 51 Power 9/5 Compal For reduce EMI radiation. Change PL700 to SM01000DJ00 X01
13 45 Power 9/6 Compal Change to green P/N. Change PC107, PC263, PC280, PC405, X01
46 PC505 to HF P/N.
14 52 Power 9/13 Compal For reduce EMI radiation. Pop PC1400~1404, PC1500~PC1504. X01
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_PIR 1
5 4
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 55 of 61
Rev
1.0
5 4 3 2 1
Request Owner
Item Page# Title Date Issue Solution Rev.
Description Description
15 51 Power 9/14 Compal For Vcore OCP setting Change PC740 to 10nF, X01
D PR750 to 365 ohm. D
16 51 Power 9/14 Compal For AXG OCP setting Change PR702 to 2.61kohm, X01
PR711 to365ohm.
17 51 Power 9/14 Compal For Vender proposal Change PC704 to 390pF, X01
PC705 to 68pF,PC720 to 22pF,
PC722 to 390pF,PC723 to 33pF,
PR741 to 130kohm,PR703 to 130kohm,
PC744 to 3300pF,PR754 to 649ohm.
18 52 Power 11/17 Compal Shortage issue Change PQ1303 from NTGD416 to AP2623 X02
19 52 Power 11/17 Compal Need ESD protected Change PQ1306,PQ1310 from SB57002040L X02
C
to SB000009Q80 C
20 53 Power 11/17 Compal IC version upgrade Change PU11 from CD3301 to CD3301A X02
21 45 Power 11/17 Compal Shortage issue Change PC110, PC111 from SGA00004E00 X02
to SGA00002N80
22 44 Power 11/21 Compal HW requirement for S3 power consumption PWR_SRC_S control signal change from X02
+3.3V_ALW to PCH_ALW_ON
23 52 53 Power 12/04 Compal EMI requirement add PC1343 PC1344 PC1345 PC1346 PC1347 X02
(0.1U_0402_25V6)
24 52 Power 12/04 Compal EMI requirement add PC1302 (0.1U_0402_25V6) X02
PC1317 (220P_0402_50V7K~D)
B
25 52 Power 12/04 Compal Prevent COS. change PD1301 from SCS00003M0L X02 B
to SCS00004O0L
PD8 from SCS00004L0L to SCS00005C00
26 54 Power 12/13 Compal Prevent COS. change PC1174 PC1176 PC1177 PC1187 X02
PC1158 PC1157 PC1165 PC1166
to SGA00002U1L
27 50 Power 12/13 Compal Improve efficiency change PR86 to 22K_0402_5% X02
28 47 Power 12/16 Compal Prevent COS. change PL301 to SH00000MW00 X02
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PWR_PIR 2
5 4
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 56 of 61
Rev
1.0
5 4 3 2 1
Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
1 11 HW 08/15/2011 COMPAL INTEL review feedback Add CC178,CC179,CC149,CC150 X01
2 32 HW 08/15/2011 COMPAL Finger Print connector changed Change JBIO1 to pitch 1.0mm X01
D D
3 37 HW 08/15/2011 COMPAL Sniffer Switch location changed Change JSF1 to SF1 X01
4 14,39 HW 08/15/2011 COMPAL SMSC request to delete LPC_LDRQ0# Leave LDRQ0# no connection on both of 5048 and PCH side X01
Removed R743
5 22 HW 08/15/2011 COMPAL Removed reserve circuit for EMC4022 Removed R405,C280,R392,R394 X01
6 42 HW 08/15/2011 COMPAL Load SW sources output rising time Change back to E3 +3.3V/5V_RUN discrete solution X01
mismatch and COS. cost concern Removed U78 and add Q55,Q61 circuit
Pop R162~R166 and de-pop U73,R1540
7 1,29 HW 08/15/2011 COMPAL Codec is change to 92HD93 X01
add R1641 connect the codec pin48 to U73 pin1
8 29 HW 08/15/2011 COMPAL Reserve co-lay with ALC290 Pop option for 92HD93/ALC290=>R1646/C1164; R1644/R1643; X01
C965/R1642; Q107/R171
Reserve for ALC290 only: C1204, C1205, R1647, C1165, R1648
Reserve for 92HD93 only: R1645, C963
C C
Add R174 depop and R175 pop
9 20,42 HW 08/15/2011 COMPAL Vgs less than cut-in voltage in battery mode Add control circuit QH6,R279,CH107 for +5V_ALW_PCH X01
10 27,28 HW 08/15/2011 COMPAL Vgs of 5V MOS maybe large than max rating X01
Add R517, R518
11 11 HW 08/15/2011 COMPAL Follow INTEL PDDG 0.8 De-pop RC140 X01
12 40 HW 08/15/2011 COMPAL Change board ID to X01 Change R875 to 130Kohms X01
13 34 HW 08/15/2011 COMPAL PCH GPIO52 need 8.2~10K pull up +3.3VS Change R695 from 100K to 10Kohms X01
14 23 HW 08/15/2011 COMPAL CRT SW 2nd source TI, TS3V713 pin29 is VDD Connect U18 pin29 to +3.3V_RUN X01
15 16 HW 08/15/2011 COMPAL +1.05V_M turn off before APWROK de-assert Add UH5,CH108 6@ circuit reserve for VPRO X01
B 16 41 HW 08/15/2011 COMPAL Reset IC threshold voltage issue Change U4 to RT9801A (threshold adjustable) X01 B
Add R1649~R1654;Reserve R1655 and pop R1623
17 26 HW 08/15/2011 COMPAL DPX_CA_DET voltage too low through dongle Change U21 and U24 to SA000055G0L X01
18 17,18 HW 08/15/2011 COMPAL Request from INTEL review feedback Pop RH332 for PCH_GPIO3 and RH180 for GPIO27 X01
19 42 HW 08/15/2011 COMPAL Material changed Power team request Q59 change to SB00000L80L X01
20 43 HW 08/15/2011 COMPAL White light LED brightness is abnormal Change R934, R938, R939, R949, R958, R957 and R959 X01
to 2.2 Kohms
21 40 HW 08/15/2011 COMPAL Reserve C1208 for ESD backup plan Reserve C1208 for ESD backup plan X01
22 11 HW 08/15/2011 COMPAL S3 can't resume issue Control 1.5V_VDDQ by EC. Pop RC79 and de-pop RC82 X01
23 15 HW 08/15/2011 COMPAL Fine tune CLK EA Changed RH311,RH314 to 10 ohm X01
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HW_PIR 1
5 4
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 57 of 61
Rev
1.0
5 4 3 2 1
Request
Item Page# Title Date Issue Description Solution Description Rev.
Owner
24 17,18 HW 08/16/2011 COMPAL INTEL review feedback Change RH331,RH272 to 10K ohm X01
D 25 34 HW 08/16/2011 COMPAL WWAN card request JMINI1 pin 1 connect to PCIE_WAKE# X01 D
26 1,14 HW 08/16/2011 COMPAL ROM size changed Change U52 to 8M and R936,R895,R897,R900 to 6@ X01
27 11 HW 08/17/2011 COMPAL Material package changed Change CC161~CC166 from 0402 to 0603 X01
28 42 HW 08/17/2011 COMPAL BOM changed Change Q60 to 6@
X01
29 31 HW 08/17/2011 COMPAL Correct Lan power net name Change LL1,LL4,LL6~LL8 pin 2 net from +3.3V* to +1.2V* X01
30 39 HW 08/19/2011 COMPAL GPIO signal name changed same as E/P Change PBATT_OFF to SLICE_BAT_ON X01
31 34 HW 08/19/2011 COMPAL Material package changed Changed C615,C1176 X01
32 37 HW 08/26/2011 COMPAL Change audio connector pin definition. Change JAUD1 pin15 to NC X01
Remove below circuit:
C 33 29 HW 08/29/2011 COMPAL Remove reserve co-lay with ALC290 circuit X01 C
Pop option for 92HD93/ALC290=>R1646/C1164;
R1644/R1643; C965/R1642; Q107/R171
Reserve for ALC290 only: C1204, C1205, R1647, C1165, R1648
Reserve for 92HD93 only: R1645, C963
Add R174 depop and R175 pop
Change R934, R938, R939, R949, R958, R957 and R959
34 43 HW 08/29/2011 COMPAL White light LED brightness is abnormal X01
to 1.2 Kohms
35 25 HW 08/30/2011 COMPAL Due to EMI HDMI test Fail, add EMI solution Change resistor to Inductor X01
Change R451, R459, R462, R466, R468, R469, R470, R471
to (Inductor CIS symbol is not ready)
Add C1209, C1210, C1211, C1212, C1213, C1214, C1215
and C1216 between Inductor and HDMI connector
Follow CONN List_0824 Change JAUD1 to ACES_51522-02001-001
36 37 HW 08/30/2011 COMPAL X01
Change JAUD1 to ACES_51522-02001-001 and swap pin because pin1 definition different
Follow CONN List_0824
B 37 24 HW 08/31/2011 COMPAL Change JLVDS1 to STARC_111H40-100000-G4-R X01 B
Change JLVDS1 to STARC_111H40-100000-G4-R
For EMI solution de-pop L19~L22 and de-pop L19~L22 and pop R451, R459, R462, R466, R468,
38 25 HW 08/31/2011 COMPAL X01
pop 0ohm resistors(need change to Inductor) R469, R470, R471(need change to Inductor)
39 30 HW 08/31/2011 COMPAL Change RL23 to 1.2k for IEEE EA Change RL23 to 1.2k for IEEE EA X01
40 30 HW 08/31/2011 COMPAL Change 3.3V_LAN control signal Change RL46 to pop & RL47 to @ X01
pop option for TM/TL
14,16,19,22 Change 6@ to pop; 5@ to @
41 HW 09/02/2011 COMPAL Change pop option for TM/TL X01
30,40,42 Change R871 pop, R877 depop
Reserved 2 GNDA pins for Audio
42 37 HW 09/05/2011 COMPAL Add JAG1 2 pin connector. X01
performance issue.
Change CH2, CH3 from 15pF to 18pF
43 14,15 HW 09/06/2011 COMPAL Change Cap value for Crystal EA X01
Change CH18, CH19 from 12pF to 10pF
44 25 HW 09/06/2011 COMPAL For EMI solution change resistor to Inductor Change 0ohm (R451, R459, R462, R466, R468, R469, X01
R470, R471) to 9nH (L99,L100,L101,L102,L103,L104,
A A
L105,L106)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HW_PIR 2
5 4
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 58 of 61
Rev
1.0
5 4 3 2 1
Request Owner
Item Page# Title Date Issue Solution Rev.
Description Description
15,30,
45 HW 09/06/2011 COMPAL Reserved TM LAN SMBus Add QH8, RL48~RL51 X01
40
46 37 HW 09/07/2011 COMPAL Change USB common choke from Audio/B to M/B Add L107 & R1656,R1657 X01
D D
47 07 HW 09/07/2011 COMPAL PCH_PLTRST#_R & VCCPWRGOOD_0_R add 2 CAP Add CC141 & CC142 X01
to GND for ESD.
48 24 HW 09/08/2011 COMPAL DMIC0 & DMIC_CLK0 add 100pF CAP Reserve C1217 & C1218 X01
close to JLVDS
49 36 HW 09/08/2011 COMPAL Change USB3.0 CAP to 0.1uF Change C412,C413,C414,C415 to 0.1uF X01
50 29 HW 09/08/2011 COMPAL Change AGND to DGND CAP to pop Change C982,C985,C986,C987 to pop X01
51 07 HW 09/09/2011 COMPAL Change RC25 value for ESD Change RC25 from 0ohm to 1kohm X01
52 32 HW 09/09/2011 COMPAL Swap JBIO1 pin define Swap JBIO1 pin define X01
53 29 HW 09/13/2011 COMPAL IDT suggest exchange location IDT suggest exchange location X01
R169~R172 & C973~C976. R169~R172 & C973~C976.
C C
Change L91~L94 part number to 0ohm Change L91~L94 part number to 0ohm
54 42 HW 09/13/2011 COMPAL Change Q55,Q61 part for open soldering Change Q55,Q61 from DMN3030LSS-13 to AO4478L X01
issue.
55 15 HW 09/13/2011 COMPAL CLK_SMART_48M reserve 10pF CAP to GND for RF Reserve CE18 to GND X01
56 15,30 HW 09/13/2011 COMPAL Change LAN SMBus pop option. Change QH8,RL50,RL51 to pop & RL48,RL49 to de-pop X01
57 29 HW 09/15/2011 COMPAL Follow EMI recommand Change L91~L94 to 2A bead X01
58 19 HW 09/15/2011 COMPAL Change LH1 from bead to Inductor for CRT Change LH1 to 1uH Inductor(SHI00007W0L) X01
59 40 HW 11/28/2011 COMPAL Crystal EA result, change CAP value. Change C741,C743 to 33pF (PT Memo) X02
EXPRESS card insert in 15" vPro can't
60 39 HW 11/28/2011 COMPAL Change R760 to 20k ohm (PT Memo) X02
B power on issue B
61 40 HW 11/28/2011 COMPAL Change board ID to X02 Change R875 to 62Kohms X02
62 42 HW 11/28/2011 COMPAL Rated Vgs of Q61 is 25V De-pop R1627 (PT Memo) X02
63 39 HW 11/28/2011 COMPAL SMSC change 5048 pin A23 to GPIOI0 Re-link ECE 5048 symbol X02
64 40 HW 11/28/2011 COMPAL SMSC review feedback Reserve R1658 and R1659 100Kohms to GND for I2S disabled X02
Update U4 symbol and add R1629 for backup of inrush
65 41 HW 11/28/2011 COMPAL Change reset IC to RT9818A-44GU3 X02
prevention.
Change RSMRST# pull up with 100Koms. Pop R1655 and de-pop
R1623.Delete R1649~R1654
When suspend/resume cycles, wireless SW Add R771 pulling up to +3.3V_ALW for WIRELESS_ON#/OFF
66 39 HW 11/28/2011 COMPAL X02
GPIO IRQs keeps giving and de-pop R766
Depop HDD control power circuit for
67 27 HW 11/28/2011 COMPAL Depop R1624,Q28,R500,R499,R517,C393 X02
A cost down. A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL HW_PIR 3
5 4
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size
Date:
Document Number
LA-7902P
Wednesday, March 07, 2012
1
Sheet 59 of 61
Rev
1.0
5 4 3 2 1
Version Change List ( P. I. R. List )
Request Owner
Item Page# Title Date Issue Solution Rev.
D
Description Description D
68 30 HW 11/28/2011 COMPAL Crystal EA result Change YL1 to 3G025000FA1H, CL5,CL6 to 12pF. (PT Memo) X02
69 11,42 HW 11/28/2011 COMPAL Change MOSFET to wihtout Schottky Diode Change QC3 and Q59 to AO4304L_SO8 X02
70 34 HW 11/28/2011 COMPAL S3 had leakage in +3/5V_RUN De-pop R725, remove R695 and add +3.3V_RUN pull high at PCH side(RH361) X02
71 32 HW 11/28/2011 COMPAL TPM is changed to AT97SC3204-X2A18-AB U39(TPM) is changed to SA00004WQ10(AT97SC3204-X2A18-AB) for WIN8 support X02
Reserve D87, R1663 (pull high to +3.3V_RUN_TPM)
72 32 HW 11/28/2011 COMPAL +3.3V_RUN Giltch when AC plugin X02
and add R1662 for HW solution backup
73 14~21 HW 11/28/2011 COMPAL Change PCH to C1 version Change UH4 to SA00005AG1L(HM77 for non vpro) X02
Change RC value at Gate of MOS Load SW to RC72 from 100K to 330K; RC143 form 330K to 1M; CC136 form 0.1u to 0.022u
74 HW 11/28/2011 COMPAL X02
modify power rail soft start timing R412 from 100K to 470K; R1632 form 1M to 4.7M; C293 form 0.1u to 0.022u
R507 from 100K to 470K; R517 form 1M to 4.7M; C400 form 0.1u to 0.022u
R722 from 100K to 470K; R1625 form 1M to 4.7M; C644 form 4700p to 220p
C
R729 from 100K to 470K; R1628 form 1M to 4.7M; C650 form 4700p to 220p C
R917 from 100K to 470K; R1617 form 1M to 4.7M; C770 form 4700p to 220p
R920 from 100K to 470K; R1610 form 470K to 2.2M; C771 form 4700p to 470p
R930 from 100K to 330K; R1611 form 470K to 1M; C773 form 2200p to 100p
R906 from 100K to 470K; C763 form 2200p to 220p
R912 from 100K to 470K; C766 form 470p to 220p
75 36 HW 11/28/2011 COMPAL Change P/N for HF Change C412~C415 P/N to SE076104K8L X02
76 HW 11/28/2011 COMPAL For cost saving Change 0 ohm to R-short X02
77 37 HW 12/01/2011 COMPAL Remove 2pin connector for Audio performance Remove JAG1 2 pin connector. X02
78 15 HW 12/01/2011 COMPAL Add 10pF CAP to GND for RF request SIO_14M add CE19(10pF) to GND X02
79 35 HW 12/01/2011 COMPAL Reserve 0.1uF CAP to GND for ESD request PCH_PLTRST#_EC & EXPCLK_REQ# reserve 0.1uF CAP(CE14,CE20) to GND X02
B B
80 35 HW 12/02/2011 COMPAL Reserve 0.1uF CAP to GND for ESD request EXPRESS_DET# reserve 0.1uF CAP(CE22) to GND X02
Follow CONN List_1130A Change JAUD1 to ACES_51522-0200N-P01
81 37 HW 12/05/2011 COMPAL X02
Change JAUD1 to ACES_51522-0200N-P01 and swap pin because pin1 definition different
Swap USB Port7 and Port8 and reserve a choke(L108) at E-Docking side:
82 17,38 HW 12/07/2011 COMPAL EMI solution for E-Docking USB port X02
Port7 from NA to E-docking ; Port8 from E-Docking to NA
Change USB9,12,13 CMC to 180ohm
83 24,32,37 HW 12/07/2011 COMPAL Change L10,L52,L107 to SM070002X00(OCF2012181YZF) X02
for EMI request
84 22 HW 12/09/2011 COMPAL Thermal requests to change OTP from 88 to 92 Change R406 from 953ohm to 1.24Kohm X02
85 41 HW 12/09/2011 COMPAL To prevent inrush current at reset IC input Change R1629 from 0ohms to 33ohm resistor X02
Change R448,R449,R450,R452,R453,R454,R455,R456 from 680ohm to 604ohm;
86 25 HW 12/13/2011 COMPAL Change HDMI R,C value for EMI request X02
C1209~C1216 from 4.7pF to 3.9pF
87 42 HW 12/15/2011 COMPAL +3.3V_SUS sequence timing R911 from 100K to 470K; R1618 from 1M to 4.7M; C767 from 4700p to 220p X02
A R934 from 1.2K to 910, R957 from 1.2K to 820, R951 from 330 to 200, A
88 43 HW 12/15/2011 COMPAL Change current limit resistors of LED X02
R938 from 1.2K to 1.5K, R958 from 1.2K to 1K, R953 from 330 to 300
and R939 from 1.2K to 1.8K
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HW_PIR 4
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 60 of 61
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D Dalmore14 UMA hang on white screen issue D
89 38 HW 02/10/2012 COMPAL Change R755 from 100k ohm to 10k ohm A00
when attached AC+media battery after hot
dock.
Change SD CLK damping resistor for EMI
90 33 HW 02/10/2012 COMPAL Change R676 from 33 ohm to 10 ohm A00
request
91 43 HW 02/24/2012 COMPAL Change current limit resistors of LED Change R958 from 1K to 1.3K (ST Memo) A00
SMSC creates a new catalog part number and
92 40 HW 02/24/2012 COMPAL Change U51 P/N to SA00003TZ2L A00
IC marking for the MEC5055
93 40 HW 02/24/2012 COMPAL Change board ID to A00 Change R875 to 33K ohm A00
94 32 HW 02/24/2012 COMPAL Change BOM option for TPM/TCM funtion Change C550,C551,C552,C553,R659,R660,R1662,RH311 BOM option to 5@ A00
For DFX conern of F2 2nd source, SP040003H0L, change F2 footprint to
95 25 HW 03/02/2012 COMPAL SMT request to change F2 footprint A00
F_MF-MSMF050-2
96 14~21,30 HW 03/02/2012 COMPAL Change PCH chip P/N for X-build UH4 is changed to SA00005AG3L(wait confirm with PJE) A00
C C
97 14 HW 03/02/2012 COMPAL De-pop resistor on PCH JTAG for power saving De-pop RH288, RH47, RH48 and RH49 A00
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HW_PIR 5
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-7902P
Date: Wednesday, March 07, 2012 Sheet 61 of 61
5 4 3 2 1
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