Institute of

Integrated Sensor Systems

Dept. of Electrical Engineering and Information Technology

Design of an
Folded Cascode Operational Amplifier
in
High Voltage CMOS Technology

Benjamin LUTGEN
Wintersemester 2008/2009

Supervisor: Prof. Dr.-Ing. Andreas König

1 Benjamin Lutgen
 Overview

1. Intoduction 3. Layout Design

– Given Objectives – High Voltage Layouting
– Motivation – Final Layout
2. Schematic Design • Functional Groups
– Practical Version of the Amplifier – LVS Log
– Schematic Description 4. Summary and Conclusion
– Design Plan – Comparison Specification/Achieved
Values
• Transistor groups
– Discussion
– First Approach – Conclusion
– Second Approach – References
• Simulation Results
– Final Solution
• Final Schematic
• Measurement Setup
• Maximizing the Gain
• Simulation results
• Measuring the Characteristics

2 Benjamin Lutgen
1. Introduction

3 Benjamin Lutgen
 Given Objectives
S. Nr Characteristics Specification values
Objective of the project: 1 Open loop Gain > 100 dB

• design of an folded cascode 2 Gain Bandwidth 10 MHz

3 Phase margin > 60 °
operational amplifier 4 Settling Time < 1 µs
• using a new high voltage 5 Slew Rate 200 V/µs

technology („H35“ 20 V) 6 Offset 5 µV

7 Input CMR ±6V
8 Output Swing ±8V

Meeting these specifications Î 9 CMRR > 100 dB

10 Power Dissipation Minimum
11 Area Consumption Minimum
12 Voltage Supply 20 V
13 Load Capacitance 10 pF
14 Load Resistance 100 kΩ

4 Benjamin Lutgen
 Motivation (1)

The used folded cascode topology offers the following

properties:
• good common-mode range
• self compensation
• High gain
• Relatively low power-dissipation
• High output resistance

The special challenge of this project was the transfer of

this circuit to a high voltage CMOS technology

5 Benjamin Lutgen
 Motivation (2)

The high voltage CMOS Technology H35 provides a high

voltage capability up to 50V.

In the project, the symmetrical 20V variant with thick oxide

is used („xMOS20HS“)

Disadvantage:
• Less K’n/K’p as in 3.3V technology in
µA/V²
20V 3.3V
Technology Technology
K‘p 12 50
K‘n 35 110

6 Benjamin Lutgen
2. Schematic Design

7 Benjamin Lutgen
 Practical Version of the Amplifier

Figure 6.5-7 from

Allen/Holberg [1]

8 Benjamin Lutgen
 Schematic Description (1)

This is a special current mirror sink, with

the following attributes:

• High output resistance

• Small saturation voltage
• Low power dissipation
• Self biasing
• High swing

This current mirror sink, and the current

mirror source are the basic modules of the
folded cascode op amp.

9 Benjamin Lutgen
 Schematic Description (2)

Another basic module:

• The differential pair with a
constant common current.
• M3 works as current sink

This are the currents of the pair, during a DC-sweep of +Vin

10 Benjamin Lutgen
 Schematic Description (3)

Schematic of the folded cascode op amp

used in the project

Based on Schematic from [1]

Allen/Holberg – CMOS Analog Circuit Design

11 Benjamin Lutgen
 Design Plan (1)

Design plan from

Allen/Holberg - CMOS
Analog Circuit Design
[1] was used for
determining the values of
the transistor and
resistors

12 Benjamin Lutgen
 Design Plan (2) Transistor Groups

The transistors in the groups must

always have the same ratio.
• M1,2
• M3
• M4,5,6,7,13,14
• M8,9,10,11
• M12

13 Benjamin Lutgen
 Design Plan (3)
Design Plan
Step 1 I3 = 2,00E-03 A = 2,00 mA

The calculations of the Step 2 Factor k = 1,20 Ratio I3 to I4,5 Transistor ratios
design plan were
I4 = 2,40E-03 A = 2,40 mA
I5 = 2,40E-03 A = 2,40 mA

realized in an Excel- Step 3 VSD5 = 1V

Transistor widths
Sheet, providing very VSD7
S4
=
= 4,00E+02
1V
= 400 NOK max 249
fast recalculations. S5 = 4,00E+02 = 400 NOK max 249 Transistor widths
S14 = 4,00E+02 = 400 NOK max 249 @ Length 2 µm
Given Specifications Factor i57 = 1,00 Ratio I5 to I7
Specification Values
Trans. Ratio Width
Characteristics Symbol
S6 = 4,00E+02 = 400 NOK max 249
Open loop Gain > 100 dB M1 0 0 µm
S7 = 4,00E+02 = 400 NOK max 249
Gain Bandwidth GB 1,00E+07 Hz M2
S13 0 0 µm
Phase Margin PM > 60 ° = 4,00E+02 = 400 NOK max 249
Settling Time < 1,00E-06 s Step 4 VDS9 = 1V
M3 0 0 µm
Slew Rate SR 2,00E+08 V/s VDS11 = 1V M4 400 800 µm
Offset 5,00E-06 V
Factor i79 = 1,00 Ratio I7 to I9 M5 400 800 µm
Input CMR Vin(max) 6V
S9 = 1,23E+02 = 123 M6 400 800 µm
Vin(min) -6 V
S8 = 1,23E+02 = 123
Output Swing Vout(max) 8V M7 400 800 µm
Vout(min) -8 V
Factor i711 = 1,00 Ratio I7 to I11
M8 123 246 µm
CMRR > 100 dB S11 = 1,23E+02 = 123
Power Dissipation Pdiss min S10 = 1,23E+02 = 123
M9 123 246 µm
Area Consumption min
Step 5 R1 = 4,17E+02 = 417,00 Ohm M10 123 246 µm
Voltage Supply VDD 10 V
R2 = 4,17E+02 = 417,00 Ohm M11 123 246 µm
VSS -10 V
Load Capacitance 1,00E-11 F Step 6 S1 = 1,28E-01 = 0 NOK min 3 M12 0 0 µm
Load Resistance = 1,00E+05 Ohm S2 = 1,28E-01 = 0 NOK min 3 M13 400 800 µm
Step 7 S3 = 3,33E-01 = 0 NOK min 3 M14 400 800 µm
Process Parameters S12 = 4,17E-01 = 0 NOK min 3
Characteristics Symbol Specification Values
Gain Factor K'n 3,90E-05 A/V2
Step 8 S4 = 82,6446281 = 83 OK S4 and S5 have to This shows only the first tentative
S5 = 82,6446281 = 83 OK be bigger as here
K'p 1,20E-05 A/V2
VT1n Step 9
¾ Values not correct
Threshold Voltage 1,54 V
VT1p -1,8 V Step 10 Pdiss = 1,84E-01 = 184,00 mW

14 Benjamin Lutgen
 First Approach
Design Plan
Step 1 I3 = 2,00E-03 A = 2,00 mA

By entering the specifications into Step 2

I4 =
Factor k
2,40E-03 A
=
=
1,20
2,40 mA
Ratio I3 to I4,5

the design plan it became

I5 = 2,40E-03 A = 2,40 mA
Step 3 VSD5 = 1V

obvious, that the transistor-

VSD7 = 1V
S4 = 4,00E+02 = 400 NOK max 249

ratios were not feasible.

S5 = 4,00E+02 = 400 NOK max 249
S14 = 4,00E+02 = 400 NOK max 249
Factor i57 = 1,00 Ratio I5 to I7
S6 = 4,00E+02 = 400 NOK max 249
S7 = 4,00E+02 = 400 NOK max 249
Given Specifications S13 = 4,00E+02 = 400 NOK max 249
Characteristics Symbol Specification Values
Step 4 VDS9 = 1V
Open loop Gain > 100 dB
VDS11 = 1V
Gain Bandwidth GB 1,00E+07 Hz
Factor i79 = 1,00 Ratio I7 to I9
Phase Margin PM > 60 °
S9 = 1,23E+02 = 123
Settling Time < 1,00E-06 s
S8 = 1,23E+02 = 123
Slew Rate SR 2,00E+08 V/s Factor i711 Ratio I7 to I11
= 1,00
Offset 5,00E-06 V
S11 = 1,23E+02 = 123
Input CMR Vin(max) 6V S10 = 1,23E+02 = 123
Vin(min) -6 V
Step 5 R1 = 4,17E+02 = 417,00 Ohm
Output Swing Vout(max) 8V R2 = 4,17E+02 = 417,00 Ohm
Vout(min) -8 V Step 6 S1 = 1,28E-01 = 0 NOK min 3
CMRR > 100 dB S2 = 1,28E-01 = 0 NOK min 3
Power Dissipation Pdiss min Step 7 S3 = 3,33E-01 = 0 NOK min 3
Area Consumption min S12 = 4,17E-01 = 0 NOK min 3
Voltage Supply VDD 10 V Step 8 S4 = 82,6446281 = 83 OK S4 and S5 have to
VSS -10 V S5 = 82,6446281 = 83 OK be bigger as here
Load Capacitance 1,00E-11 F Step 9
Load Resistance = 1,00E+05 Ohm Step 10 Pdiss = 1,84E-01 = 184,00 mW

15 Benjamin Lutgen
 Second Approach
Design Plan
Step 1 I3 = 2,70E-03 A = 2,70 mA

By modifying the specifications Step 2

I4 =
Factor k
3,24E-03 A
=
=
1,20
3,24 mA
Ratio I3 to I4,5

entered in the Design Plan, it

I5 = 3,24E-03 A = 3,24 mA
Step 3 VSD5 = 1,5 V

was possible to achieve

VSD7 = 1,5 V
S4 = 2,40E+02 = 240 OK max 249

feasible transistor-ratios
S5 = 2,40E+02 = 240 OK max 249
S14 = 2,40E+02 = 240 OK max 249
Factor i57 = 1,00 Ratio I5 to I7
S6 = 2,40E+02 = 240 OK max 249
S7 = 2,40E+02 = 240 OK max 249
Given Specifications S13 = 2,40E+02 = 240 OK max 249
Characteristics Symbol Specification Values
Step 4 VDS9 = 1,5 V
Open loop Gain > 100 dB
VDS11 = 1,5 V
Gain Bandwidth GB 3,50E+07 Hz
Factor i79 = 1,00 Ratio I7 to I9
Phase Margin PM > 60 °
S9 = 7,38E+01 = 74
Settling Time < 1,00E-06 s
S8 = 7,38E+01 = 74
Slew Rate SR 1,80E+08 V/s Factor i711 Ratio I7 to I11
= 1,00
Offset 5,00E-06 V
S11 = 7,38E+01 = 74
Input CMR Vin(max) 6V S10 = 7,38E+01 = 74
Vin(min) -6 V
Step 5 R1 = 4,63E+02 = 463,00 Ohm
Output Swing Vout(max) 7V R2 = 4,63E+02 = 463,00 Ohm
Vout(min) -7 V Step 6 S1 = 2,62E+00 = 3 OK min 3
CMRR > 100 dB S2 = 2,62E+00 = 3 OK min 3
Power Dissipation Pdiss min Step 7 S3 = 1,92E+01 = 19 OK min 3
Area Consumption min S12 = 2,40E+01 = 24 OK min 3
Voltage Supply VDD 10 V Step 8 S4 = 111,5702479 = 112 OK S4 and S5 have to
VSS -10 V S5 = 111,5702479 = 112 OK be bigger as here
Load Capacitance 1,50E-11 F Step 9
Load Resistance = 1,00E+05 Ohm Step 10 Pdiss = 2,48E-01 = 248,40 mW

16 Benjamin Lutgen
Second Approach Simulation Results

17 Benjamin Lutgen
 Second Approach Conclusion

Due to the different characteristics of the H35 technology

¾ Very little amplification (~ 10)
¾ High offset (> 1 V)

¾ High power dissipation (> 400 mW)

¾ Non-linear

Î changing several input specifications for design-

plan

18 Benjamin Lutgen
 Final Solution
Design Plan
Step 1 I3 = 2,00E-04 A = 0,20 mA

After several attempts a promising Step 2

I4 =
Factor k
2,40E-04 A
=
=
1,20
0,24 mA
Ratio I3 to I4,5

design was found:

I5 = 2,40E-04 A = 0,24 mA
Step 3 VSD5 = 1V
VSD7 = 1V

• Low power dissipation S4

S5
=
=
4,00E+01
4,00E+01
=
=
40 OK max 249
40 OK max 249

• Relatively small transistors S14 = 4,00E+01

Factor i57
=
=
40 OK max 249
1,00 Ratio I5 to I7
S6 = 4,00E+01 = 40 OK max 249
S7 = 4,00E+01 = 40 OK max 249
Given Specifications S13 = 4,00E+01 = 40 OK max 249
Characteristics Symbol Specification Values
Step 4 VDS9 = 1V
Open loop Gain > 100 dB
VDS11 = 1V
Gain Bandwidth GB 1,00E+08 Hz
Factor i79 = 1,00 Ratio I7 to I9
Phase Margin PM > 60 °
S9 = 1,23E+01 = 12
Settling Time < 1,00E-06 s
S8 = 1,23E+01 = 12
Slew Rate SR 2,00E+07 V/s Factor i711 Ratio I7 to I11
= 1,00
Offset 5,00E-06 V
S11 = 1,23E+01 = 12
Input CMR Vin(max) 6,5 V S10 = 1,23E+01 = 12
Vin(min) -6,5 V
Step 5 R1 = 4,17E+03 = 4167,00 Ohm
Output Swing Vout(max) 8V R2 = 4,17E+03 = 4167,00 Ohm
Vout(min) -8 V Step 6 S1 = 1,28E+02 = 128 OK min 3
CMRR > 100 dB S2 = 1,28E+02 = 128 OK min 3
Power Dissipation Pdiss min Step 7 S3 = 3,31E+00 = 3 OK min 3
Area Consumption min S12 = 4,14E+00 = 4 OK min 3
Voltage Supply VDD 10 V Step 8 S4 = 13,84083045 = 14 OK S4 and S5 have to
VSS -10 V S5 = 13,84083045 = 14 OK be bigger as here
Load Capacitance 1,00E-11 F Step 9
Load Resistance = 1,00E+05 Ohm Step 10 Pdiss = 1,84E-02 = 18,40 mW

19 Benjamin Lutgen
Final Schematic

20 Benjamin Lutgen
 Measurement Setup
•Offset compensation
For AC and DC analysis
•Supply Voltage

•Signal input

21 Benjamin Lutgen
 Final Solution Simulation Results (1)

Dependences M1/2 M3 M12 R1 R2

Increase
• For increasing the gain it Gain
Ï Ï Ð Ï Ï
showed out, that the best way Increase
was just increasing M3 in Phase Ð Ð ; ; ;
width, to get more current in Margin
the differential pair.
Increase 6
• Changing M3 even decreases GBW Ï ; ; ;
ÐÏ
the offset

Legend
Ï Make wider
Ð Make smaller
6 Has a maximum
; Not measured

22 Benjamin Lutgen
 Maximizing Gain (1)
Voltage amplification

22.000
Finding the best width for M3 with
20.000
18.000
maximum gain and PM > 60°
16.000
M3 M12 I3 Comp. Offset Av GBW PM
14.000
12.000 6,0 8,0 198,4 µA + 4430,00 µV 2.018 12,59 MHz 83,38 °
Av

10.000 12,0 8,0 398,7 µA + 1940,00 µV 5.060 17,62 MHz 78,49 °

8.000 12,5 8,0 415,5 µA + 1810,00 µV 5.440 17,96 MHz 77,94 °
6.000
13,0 8,0 432,2 µA + 1670,00 µV 5.900 18,28 MHz 77,34 °
4.000
13,5 8,0 448,9 µA + 1550,00 µV 6.370 18,56 MHz 76,69 °
2.000
0 14,0 8,0 465,6 µA + 1430,00 µV 6.910 18,82 MHz 75,97 °
6,0

12,0

12,5

13,0

13,5

14,0

14,5

15,0

15,5

16,0

16,5

17,0

17,5

17,6

17,7

17,8

17,9

18,0

18,5
14,5 8,0 482,4 µA + 1320,00 µV 7.520 19,04 MHz 75,15 °
Width M3 [µm] 15,0 8,0 499,1 µA + 1190,00 µV 8.228 19,23 MHz 74,22 °
15,5 8,0 515,8 µA + 1070,00 µV 9.060 19,36 MHz 73,14 °
Gain Bandwidth and Phase Margin
16,0 8,0 532,5 µA + 962,38 µV 10.009 19,44 MHz 71,84 °
20,00 90,00 16,5 8,0 549,3 µA + 849,02 µV 11.191 19,41 MHz 70,23 °
18,00 85,00 17,0 8,0 566,0 µA + 735,94 µV 12.681 19,23 MHz 68,10 °
16,00 80,00 17,5 8,0 582,7 µA + 622,27 µV 14.659 18,74 MHz 65,00 °
Gain Bandwidth [MHz]

14,00 75,00 17,6 8,0 586,0 µA + 598,93 µV 15.142 18,57 MHz 64,18 °

Phase Margin [°]

12,00 70,00 17,7 8,0 589,4 µA + 576,29 µV 15.658 18,36 MHz 63,26 °
10,00 65,00
17,8 8,0 592,7 µA + 553,38 µV 16.218 18,11 MHz 62,21 °
8,00 60,00
17,9 8,0 596,1 µA + 530,08 µV 16.829 17,80 MHz 60,99 °
6,00 55,00
18,0 8,0 599,4 µA + 506,24 µV 17.502 17,40 MHz 59,55 °
4,00 50,00
18,5 8,0 616,7 µA + 385,05 µV 22.210 12,98 MHz 48,20 °
2,00 45,00
0,00 40,00 All other transistors according to the
6,0
12,0

12,5
13,0
13,5
14,0

14,5
15,0
15,5

16,0
16,5
17,0
17,5

17,6
17,7
17,8
17,9

18,0
18,5

Width M3 [µm]
final solution values.

23 Benjamin Lutgen
 Maximizing Gain (2)

Differential Pair currrent and Offset

700,0 5000,00

4500,00
600,0
4000,00
500,0 3500,00
3000,00

Offset [µV]
400,0
I3 [µA]

2500,00
300,0
2000,00

200,0 1500,00
1000,00
100,0
500,00
0,0 0,00
6,0
12,0
12,5
13,0
13,5
14,0
14,5
15,0
15,5
16,0
16,5
17,0
17,5
17,6
17,7
17,8
17,9
18,0
18,5
Width M3 [µm]

24 Benjamin Lutgen
 Final Approach Simulation Results (2)
AC Analysis (linear) / DC Analysis in Differential Mode

25 Benjamin Lutgen
 Final Approach Simulation Results (3)
AC Analysis (dB) / DC Analysis in Differential Mode

26 Benjamin Lutgen
Final Approach Simulation Results (4)
AC Analysis (linear) in common mode

27 Benjamin Lutgen
 Measuring the Characteristics (1)

CMRR [input: sinus with 1 mV amplitude]

Differential mode output: 16829 mV Measured on the plateau
at low frequency
Common mode output: 0.213 mV
16829
= 79009 .38 =ˆ 97.95dB
0.213
Pdiss
Max current in differential mode: 1,106 mA
1.106mA ⋅ 20
{ V = 22.12mW
Area Vsupply

155µm ⋅ 200µm = 31000µm 2 = 0.031mm 2

28 Benjamin Lutgen
 Measuring the Characteristics (2)

ICMR
±8.5 V Fig. 6.6-10 [1]

Fig. 6.6-10 [1]

29 Benjamin Lutgen
 Measuring the Characteristics (3)

Output Swing
±8.6 V Fig. 6.6-11 [1]

Fig. 6.6-11 [1]

30 Benjamin Lutgen
 Measuring the Characteristics (4)

Slew Rate
Rise: 27.052.69 V/µs Fall: 35.337 V/µs

Fig. 6.6-14 [1]

31 Benjamin Lutgen
 Measuring the Characteristics (5)

Settling Time
Rise: 168.6 ns Fall: 149.0 ns

32 Benjamin Lutgen
3. Layout Design

33 Benjamin Lutgen
 High Voltage Layouting (1)

Transistors from high

voltage library:
• Many different layers
(different doped
TUBs)
• Very restrictive layout
rules
• Protective structures

NMOS
• Guard ring (to Vdd)
• For folded Transistors
-> multiple Gates

34 Benjamin Lutgen
 High Voltage Layouting (2)

PMOS
• Inner guard ring (to Vdd)
• Outer guard ring (to Vss)
• For folded Transistors ->
common Gate
• Protective Metal1-Layer
over the transistor

35 Benjamin Lutgen
 Final Layout (1)

The following layout is only principle

¾ Due to the time intensive design plan, there was not
enough time to design a matched layout.
ÄThe actual layout is very sensitive to process variations
¾ Matching of the layout is possible

36 Benjamin Lutgen
 155 µm
Final Layout (2)

37 Benjamin Lutgen

200 µm
 Final Layout (3) Functional Groups

38
Benjamin Lutgen
 LVS Log
*******************************************************************************************************************
******* FoldedCascode2 schematic TESYS_BL_P1 <vs> FoldedCascode2 layout TESYS_BL_P1 *******
*******************************************************************************************************************

Filter/Reduce statistics only. Network matching was OK.

Pre-expand Statistics
====================== Original
Cell/Device schematic layout //comment for layout
(NMOS20HS) MOS 9 3* //(M3, M12, M15)
(PMOS20HS) MOS 9 1* //(M17) #
(RPOLY2) RES 2 0* //
(_, nmos20hs layout PRIMLIB l="2u" mult="8" w=" 32u" wtot=" 256u") Cell 0 2* //(M1, M2)
(_, nmos20hs layout PRIMLIB l="2u" mult="3" w=" 8u" wtot=" 24u") Cell 0 4* //(M8, M9, M10, M11)
(_, pmos20hs layout PRIMLIB l="2u" mult="4" w=" 20u" wtot=" 80u") Cell 0 6* //(M4, M5, M6, M7, M13, M14)
(_, pmos20hs layout PRIMLIB l="2u" subGuard=FALSE w="14.5u" wtot="14.5u") Cell 0 2* //(M16, M18)
(_, rpoly2 layout PRIMLIB Bends=9 Dummy=TRUE l="145.85u" r="4167.14" w="2u") Cell 0 2* //(R1, R2)
------ ------
Total 20 20

Reduce Statistics
================= Original Reduced
Cell/Device schematic layout schematic layout
(NMOS20HS) MOS 9 31* 9 9
(PMOS20HS) MOS 9 27* 9 9
(RPOLY2) RES 2 2 2 2
------ ------ ------ ------
Total 20 60 20 20

Schematic and Layout Match

//# M17 is created from PRIMLIB and then the substrate contacts are removed, to aviod DRC errors. Now M17 is regarded as drawn by user.

39 Benjamin Lutgen
4. Summary and Conclusion

40 Benjamin Lutgen
 Comparison Specification/Achieved Values
Specification Values for the Design Mesured Values Mesured Values
S. Nr Characteristics
values Plan Schematic Simulation Post-Layout Simulation
1 Open loop Gain > 100 dB 100 dB 84.52 dB (*16829) 84.59 dB (*16954)
2 Gain Bandwidth 10 MHz 100 MHz 17.80 MHz 15.809 MHz
3 Phase margin > 60 ° 60 ° 60,99 ° 52.09 °
4 Settling Time < 1 µs 1 µs 74.09 ns -
5 Slew Rate 200 V/µs 20 V/µs 25.693 V/µs -
6 Offset 5 µV 5 µV 530 µV -
7 Input CMR ±6V ± 6.5 V ± 8.5 V -
8 Output Swing ±8V ±8V ± 8.6 V -
9 CMRR > 100 dB 100 dB 97.95 dB -
10 Power Dissipation Minimum Minimum 22.12 mV -
11 Area Consumption Minimum Minimum - 31000 µm2
12 Voltage Supply 20 V 20 V 20 V 20 V
13 Load Capacitance 10 pF 10 pF 10 pF 10 pF
14 Load Resistance 100 kΩ 100 kΩ 100 kΩ 100 kΩ
Comp. Offset - - 530.08 µV 2.634 mV

41 Benjamin Lutgen
 Discussion

• It was not possible to reach all the specifications, but also

some specifications were exceeded.
• The HV design just reached a gain of 84.5 dB, mostly
limited by the lower K’-values . A low voltage folded
cascode op amp should easily reach more than 100 dB or
even 120 dB.
• The offset of the op amp is very high, and tentatively
compensated by an external voltage source.
• The slew rate/settling time diagram shows an unusual,
non smooth characteristics

42 Benjamin Lutgen
 Conclusion

• Analyzing, understanding the topology, getting good

transistor values from the design plan [1] and get better
gain and more stability was very difficult and time
intensive because the HV-technology has not the same
behavior than a low voltage technology.
• Assura (layout checking tool) had problems recognizing
the pins during the LVS (Layout Vs Schematic) check
– Solution: changing the rule-file “extract.rul” according
to [4]
• The designed operation amplifier is not excellent, but on
schematic level good enough to be used in an
application.

43 Benjamin Lutgen
 References

[1] Allen/Holberg - CMOS Analog Circuit Design (Second ed. 2002) -

Oxford University Press
[2] Prof. Andreas König - Electronics II Script - WS 07/08
[3] Prof. Andreas König - TESYS Script - SS 08
[4] Martin Hetterich - Untersuchung der Realisierbarkeit
eines generisch rekonfigurierbaren Sensorelektronikbausteins
in einer 0,35µm Hochvolt-CMOS-Technologie - 2009

Used Tools
• Sun Solaris 9.2
• Cadence HIT-Kit v3.72
• Assura v3.1
• Austriamicrosystems’ high voltage transistor-technology (20V) H35

44 Benjamin Lutgen
Thank You
END

45 Benjamin Lutgen