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Report Power

The document details the steps taken in a power analysis of a design. It lists the inputs, libraries, and steps including processing timing data, signals, levelizing, activity propagation, and power computation. Metrics like total, internal, switching, and leakage power are reported along with highest power instances.

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srajece
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131 views4 pages

Report Power

The document details the steps taken in a power analysis of a design. It lists the inputs, libraries, and steps including processing timing data, signals, levelizing, activity propagation, and power computation. Metrics like total, internal, switching, and leakage power are reported along with highest power instances.

Uploaded by

srajece
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Begin Power Analysis

0.00V vssx
3.30V vdd_p1
0.00V vddx

Begin Processing Timing Library for Power Calculation

Begin Processing Timing Library for Power Calculation

Begin Processing Power Net/Grid for Power Calculation

Ended Processing Power Net/Grid for Power Calculation: (cpu=0:00:00, real=0:00:00,


mem(process/total)=1384.89MB/1384.89MB)

Begin Processing Timing Window Data for Power Calculation

CK: assigning clock clk to net clk


Ended Processing Timing Window Data for Power Calculation: (cpu=0:00:00,
real=0:00:00, mem(process/total)=1384.89MB/1384.89MB)

Begin Processing User Attributes

Ended Processing User Attributes: (cpu=0:00:00, real=0:00:00,


mem(process/total)=1384.89MB/1384.89MB)

Begin Processing Signal Activity

Starting Levelizing
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT)
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 10%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 20%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 30%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 40%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 50%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 60%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 70%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 80%
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT): 90%

Finished Levelizing
2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT)

Starting Activity Propagation


2020-Sep-07 15:01:45 (2020-Sep-07 09:31:45 GMT)
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 10%
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 20%
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 30%

Finished Activity Propagation


2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT)
Ended Processing Signal Activity: (cpu=0:00:01, real=0:00:00,
mem(process/total)=1384.96MB/1384.96MB)

Begin Power Computation


----------------------------------------------------------
# of cell(s) missing both power/leakage table: 0
# of cell(s) missing power table: 0
# of cell(s) missing leakage table: 0
# of MSMV cell(s) missing power_level: 0
----------------------------------------------------------

Starting Calculating power


2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT)
... Calculating switching power
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 10%
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 20%
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 30%
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 40%
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 50%
... Calculating internal and leakage power
2020-Sep-07 15:01:46 (2020-Sep-07 09:31:46 GMT): 60%
2020-Sep-07 15:01:47 (2020-Sep-07 09:31:47 GMT): 70%
2020-Sep-07 15:01:47 (2020-Sep-07 09:31:47 GMT): 80%
2020-Sep-07 15:01:47 (2020-Sep-07 09:31:47 GMT): 90%

Finished Calculating power


2020-Sep-07 15:01:48 (2020-Sep-07 09:31:48 GMT)
Ended Power Computation: (cpu=0:00:01, real=0:00:01,
mem(process/total)=1384.96MB/1384.96MB)

Begin Processing User Attributes

Ended Processing User Attributes: (cpu=0:00:00, real=0:00:00,


mem(process/total)=1384.96MB/1384.96MB)

Ended Power Analysis: (cpu=0:00:02, real=0:00:02,


mem(process/total)=1384.96MB/1384.96MB)

Begin Static Power Report Generation


*----------------------------------------------------------------------------------
------
* Innovus 17.14-s077_1 (64bit) 05/04/2018 09:53 (Linux 2.6.18-194.el5)
*
*
* Date & Time: 2020-Sep-07 15:01:48 (2020-Sep-07 09:31:48 GMT)
*
*----------------------------------------------------------------------------------
------
*
* Design: topdesign
*
* Liberty Libraries used:
* Worst:
/home/fxece/Desktop/adc/pnr/dinesh/finalfloorpland05092020.enc.dat/libs/mmmc/slow.l
ib
*
* Power Domain used:
* Rail: vdd_p1 Voltage: 3.3
*
* Power View : Worst
*
* User-Defined Activity : N.A.
*
* Activity File: N.A.
*
* Hierarchical Global Activity: N.A.
*
* Global Activity: N.A.
*
* Sequential Element Activity: 0.200000
*
* Primary Input Activity: 0.200000
*
* Default icg ratio: N.A.
*
* Global Comb ClockGate Ratio: N.A.
*
* Power Units = 1mW
*
* Time Units = 1e-09 secs
*
* report_power
*
-----------------------------------------------------------------------------------
------
40 instances have no static power

Total Power
-----------------------------------------------------------------------------------
------
Total Internal Power: 51.23518722 73.4713%
Total Switching Power: 17.40981085 24.9657%
Total Leakage Power: 1.09001038 1.5631%
Total Power: 69.73500770
-----------------------------------------------------------------------------------
------

Group Internal Switching Leakage Total


Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------
------
Sequential 31.81 2.968 0.2635 35.04
50.25
Macro 0 0 0 0
0
IO 0 0 0 0
0
Combinational 17.88 11.43 0.8225 30.14
43.22
Clock (Combinational) 1.541 3.01 0.004033 4.554
6.531
Clock (Sequential) 0 0 0 0
0
-----------------------------------------------------------------------------------
------
Total 51.24 17.41 1.09 69.74
100
-----------------------------------------------------------------------------------
------

Rail Voltage Internal Switching Leakage Total


Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------
------
vdd_p1 3.3 0 0 0 0
0
Default 0.9 51.24 17.41 1.09 69.74
100

Clock Internal Switching Leakage Total


Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------
------
clk 1.541 3.01 0.004033 4.554
6.531
-----------------------------------------------------------------------------------
------
Total 1.541 3.01 0.004033 4.554
6.531
-----------------------------------------------------------------------------------
------

-----------------------------------------------------------------------------------
------
* Power Distribution Summary:
* Highest Average Power: CTS_ccl_a_BUF_clk_G0_L2_10 (CLKBUFX12):
0.2988
* Highest Leakage Power: FE_OCPC3689_n_9211 (BUFX20): 0.000367
* Total Cap: 2.6751e-10 F
* Total instances in design: 15352
* Total instances in design with no power: 40
* Total instances in design with no activty: 0

* Total Fillers and Decap: 40


-----------------------------------------------------------------------------------
------

Ended Static Power Report Generation: (cpu=0:00:00, real=0:00:00,


mem(process/total)=1384.96MB/1384.96MB)

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