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It Is A Process To Convert RTL Code Into Design Implementation

Synthesis is a process that converts RTL code into a design implementation. Synthesis errors can occur due to issues like multiple assignments on the same signal, asynchronous resets mixed with other signals, missing sensitivity lists, or mixing blocking and non-blocking assignments. B.A. assignments are used to model combinational logic while N.B.A. assignments are used for sequential logic. Constraints are needed for timing optimization, I/O parameters, and design rules. Without constraints, only an unoptimized gate-level netlist can be produced.

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920 views5 pages

It Is A Process To Convert RTL Code Into Design Implementation

Synthesis is a process that converts RTL code into a design implementation. Synthesis errors can occur due to issues like multiple assignments on the same signal, asynchronous resets mixed with other signals, missing sensitivity lists, or mixing blocking and non-blocking assignments. B.A. assignments are used to model combinational logic while N.B.A. assignments are used for sequential logic. Constraints are needed for timing optimization, I/O parameters, and design rules. Without constraints, only an unoptimized gate-level netlist can be produced.

Uploaded by

srajece
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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1.What is synthesis?

It is a process to convert RTL code into design implementation.

2.Tell the scenarios where synthesis error occurs.

 A synthesis error can occur in the following scenarios:

1. When there is multiple assignments on the same signal in two different blocks, “a
multiple driver found” message will come.

2. When there is mixture of asynchronous reset with some other signal and that signal is
not used in the sensitivity list; basically mixing of multiple edges and synchronous
and asynchronous elements are not allowed.

3. No element in the always block sensitivity list.

4. Mixing of B.A and N.B.A on the same signal in two different conditional statements.

5. If reg datatypes are used in assign statements, etc.

3. Why we use B.A (Blocking Assignments) and N.B.A (Non Blocking Assignments)?

B.A are used to model combinatorial logic as the value is of continuous assignment
and doesn’t depend on the previous value, while N.B.A are used to model sequential circuits
as the previous value is needed to propagate.

• What are the various factors that need to be considered while choosing a technology library
for a design?

The technology lib should have all the cells which u are having in the RTL. Additionally It
should have the filler,Tie, endcap and decap cells. Then the cells should have information of
proper timing information, pin direction, trasition value, power and area in lib file.

4.What will happen to a design that is synthesized without any constraints?

Without any constaints means that u are not taking care of the timing . So u dont know how
much frequency should ur chip work. Once u set freqency U should also check for setup and
hold violation. If there is a setup violation then your chip will function slow.If u have hold
then ur chip will not work as u expect. So without constraints u will get only gate level netlist
file(i.e mapping the normal gates with the gates in the lib).

5.How do you perform Synthesis activities in Multi vt libraries?

For area calculation choose the worst case lib(low voltage) for synthesis and for power
calculation choose the best case lib(high voltage) for synthesis. default use worst case lib for
Synthesis. Also worst case lib for setup and best case lib for hold.

6. What are the difference you find when you switch from 130nm to 90nm?
In 130nm Cell size will be bigger , it consumes more area and hence floorplan will be bigger.
Also It consumes more power. 90nm consumes less area and less power compared to 130nm.

7.Why max and min capacitance required?

The maximum and minimum capacitance is the total capacitive load that an output pin can
drive..The min_capacitance rule specifies the minimum load a cell can drive.
max_capacitance is available only for output pins. These things will be present in lib file.

Ex:-

pin (Z) {

direction : "output";

related_bias_pin : "VDDB VSSB";

max_capacitance : 0.334971 ;

max_fanout : 20 ;

timing () {

cell_degradation (constraint) {

index_1 ("1.0, 1.5, 2.0") ;

values ("1.0, 1.5, 2.0") ;

Hint :-

If you have more output capacitance load then it will take more time to charge /discharge
to/from a particular logic level. It means that the delay of the cell is more.

8.What is Metastability? How to overcome metastability? If metastable condition exists


which frequency you will use as clock- faster or slower? Why?

Metastable: A state which exist between either "valid" digital logic state {an undefined
voltage}

Connecting two or more flip flops in series can also reduce the probability of metastability
occuring.
In flip flops it occurs mainly if the input signal occurs temporally close to the clock signal or
it held its state for a shorter time than necessary, i.e. setup and hold time violations.

9. What are the inputs required to start synthesis ?

Ans :

 .lib-timing info of standard cell & macros


 .v- RTL code.
 SDC- Timing constraints.
 UPF- power intent of the design.
 Scan config- Scan related info like scan chain length, scan IO, which flops
are to be considered in the scan chains.
 RC co-efficient file (tluplus).
 LEF/FRAM- abstract view of the cell.
 Floorplan DEF- locations of IO ports and macros.

10. If you are given an RTL tag which is not getting linked properly, what workarounds
have you done ?

Ans : If designer is around, sit with him/her to get it corrected. If not, hack the RTL, x the
syntax mistakes, to get it linked. Even unsynthesisable code can be present in the RTL, which
gives Error in the Elaborate stage. Whatever changes we make in the RTL should be
informed and get it confirmed from the Designer.

11. What are the requisites for compile stage ?

Ans : Fully elaborated database is the minimum requirement. Additional information for


compile are the constraints. Initial compile can be done without constraints, if they are not
ready. But this will take huge runtime.

12. What are the different constraints needed for Synthesis ?

Ans : Timing optimisation constraints — clock constraints which includes create_clocks,


create_generated_clocks, virtual_clocks, and exceptions which includes multicycle_paths,
case_analysis, false_paths. Input/Output constraints like set_input_delay, set_output_delay
are also required. If delay constraints need to be specied, the set_max_delay, set_min_delay
also should be used. Optimisation constraints for area and power also should be specied if
needed.

Design Rule Constraints — This includes max_transition for the design, input_transition and
driving cell for the inputs, load/capacitance for the outputs.

13. How can you detect whether transparent latch is inferred while elaboration ?
Ans : We can turn on the variable “hdlin_check_no_latch”, so that Design Compiler issues a
warning message, if transparent latches are inferred.

14.Which design rule constraint will be given the maximum priority by Design
Compiler ?

Ans : max_transition

15. If you have a violating path after synthesis, how to optimise it ?

Ans : Group that path with -from -to option and give weightage value and do an incremental
compile.

16. Which library will you generally use as target library, if your standard cell library
consists of multiple threshold voltage cells ?

Ans : We use normal threshold voltage cells as target library for Synthesis.

17. What corner will you use for Synthesis ?

Ans : Worst corner.

18.If you have multiple modes, where a single clock’s frequency differs, how will you
constrain it in Synthesis ?

Ans : We take the highest frequency for this clock while doing Synthesis to optimise
maximum.

19.What is clock gating?

Due to high switching activity of clock a lot of dynamic power is consumed. to lower the
dynamic power is clock gating technique is used
clock gating circuit consists of an AND gate in the clock path with one input as enable.

20. What are the output files of synthesis?

Outputs of Synthesis

 netlist

 SDC

 UPF

 ScanDEF- information of scan flops and their connectivity in a scan chain

21. What are the Checks to be done after synthesis


 the RTL and netlist are logically equivalent (LEC/FM)
 Floating pins
 multi driven inputs
 un-driven inputs
 un-driven outputs
 normal cells in clock path
 pin direction mismatch
 don’t use cells
 Setuptiming
 CLP check --- always on buffer is placed or not
 Cell profiling
 Buffer count

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