EEE/ INSTR F313

Analog Digital VLSI Design

BITS Pilani
Pilani Campus Anu Gupta
 BITS Pilani
Pilani Campus

MOS Scaling Techniques

Dennard at al. (1972)
Basic principle
The basic principle –

that in order to increase the performance of a MOSFET we must

reduce linearly

• the size of the transistor,

• together with the supply voltage,

• and increase the doping concentration

• in a way which keeps the electric field in the device constant - hence
the name “constant field scaling”

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Moore’s Law
• Integrated circuits would double in
Initially
2 years
performance every 18 months
Careful observation
• First observed by Intel co-founder Gordon
E. Moore in a 1965 paper

• It has continued for almost half of a

century
 Implication
• Although Moore's law was initially made in the form of an
observation and forecast, the more widely it became
accepted, the more it served as a goal for an entire industry.

• This drove both marketing and engineering departments of

semiconductor manufacturers to focus enormous energy
aiming for the specified increase in processing power
that it was presumed one or more of their competitors would
soon actually attain.

• In this regard, it can be viewed as a self-fulfilling prophecy

Technology Generation 250 nm 180 nm 150 nm 130 nm 100 nm 70 nm 50 nm

Year (Production) 1997 1999 2001 2003 2006 2009 2012

DRAM/SRAM 256/64M 1G/256M 1G/256M 4G/1G 16G/4G 64G/16G 256/64G

DRAM chip (cm2) 2.8 4.0 4.45 5.6 7.9 11.2 15.8

DRAM cost (per bit) 120 60 30 15 5.3 1.9 0.66

Wafer Diameter (mm) 200 300 300 300 300 450 450

Logic gates/cm2 3.7-8M 6.2-14M 10-16M 18-24M 39-40M 84-64M 180-100M

Logic chip (cm2) 3-4.8 3.4-8 3.85-8.5 4.3-9 5.2-10 6.2-11 7.5-13

Frequency (GH) 0.3-0.75 0.5-1.2 0.6-1.4 0.7-1.6 0.9-2.0 1.2-2.5 1.5-3.0

Technology Generation 250 nm 180 nm 150 nm 130 nm 100 nm 70 nm 50 nm

Year (Production) 1997 1999 2001 2003 2006 2009 2012

ASIC NRE cost (m ?T) 50 25 20 15 10 5 2.5

Power/chip (W) 70 90 110 130 160 170 175

Power Supply 2.5-1.8V 1.8-1.5V 1.5-1.2V 1.5-1.2 V 1.2-0.9V 0.9-0.6V 0.6-0.5

Levels of Metal 6 6-7 7 7 7-8 8-9 9

Oxide Thickness (nm) 4-5 3-4 2-3 2-3 1.5-2 <1.5 <1

Xj at Channel (nm) 50-100 36-72 30-60 26-52 20-40 15-30 10-20

Xj Contact (nm) 100-200 70-140 60-120 50-100 40-80 15-30 10-20

Nominal Leff (m)* 140-210 100-151 84-126 73-109 56-84 44-54 28-42
*Taken as 70% of the technology parameter

Leff Variation <20% <20% <20% <20% <20% <20% <20%

Id sat (uA/ m ) ++ 600/280 600/280 600/280 600/280 600/280 600/280 600/280

++ NMOS/PMOS

Ioff (nA/ m ) 1 1 3 3 3 10 10

Number of I/O pins 1450 2000 2400 3000 4000 5400 73002
Technology roadmap projections
Need of ITRS

(ITRS) has road-mapped technology requirements of the

semiconductor industry over the past two decades.

The need arose for a clear roadmap --

• to anticipate the evolution of the market and

• to plan and control the technological needs of IC

production

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The International Technology Roadmap for Semiconductors
ITRS
• The roadmap identifies major challenges in advanced technology and leads the
investment of research in a cost effective way.

• ITRS identifies major semiconductor IC products as drivers; there set

requirements for the state-of-theart semiconductor technologies.- High-
performance microprocessor unit (MPU-HP) for servers and consumer portable
system-on-chip (SOC-CP) for smartphones are two examples.

• Throughout the history of the ITRS, Moore’s Law has been the main impetus for
these drivers, continuously pushing the transistor density to scale at a rate of 2×
per technology generation (aka “node”).

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 Why Scaling?
Technology shrinks by ~0.7/generation

• With every generation can integrate 2x more functions per

chip; chip cost does not increase significantly

• Cost of a function decreases by 2x

• But …
– How to design chips with more and more functions?

– Trained design engineering population does not double every two

years…

• Hence, a need for more efficient design methods

– Exploit different levels of abstraction
Why scaling ?
Moore’s Law - #DRAM Bits per chip doubles every 18 months
~25% bigger chips/wafers
~25% design improvements
~50 % Lithography – ability to print smaller features

With feature size shrink of 2 (typical generation)

– 2x #transistors/unit area
– 2X Higher speed (fmax)
– Fixed cost per wafer
 Smaller (2x), Faster (2x), cheaper – strong economic driving force
 30% improvement in cost per function per year

Small Dimension (short channel) effects

• Some long channel assumptions no longer valid
• Enhancement of some small effects
• Entirely new effects arise

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Design tradeoffs
• Cycle Time/ Data rate
• Silicon area/ Cost
• power consumption
• Reliability
• Re-configurability/ programmability
Scaling advantages

30% reduction in CMOS IC technology node scaling has -

1) reduced the gate delay by 30% allowing an increase in

maximum clock frequency of 43%;

2) doubled the device density;

3) reduced the parasitic capacitance by 30%;

4) reduced energy and active power per transition by 65%

and 50%, respectively

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Negative effects of scaling
Negative effects that are directly related to the shrinking die
size are
• increased temperatures in the hottest structures on the
die accelerating negative effects ( gate leakage,
electromigration ---)
• the decreased tolerance to the electromigration-caused
degradation of interconnects
• the increased vulnerability to the effects of dielectric
breakdown on the gate oxides (thin tox)
Adv. of Scaling

Improvements

• Density
• Speed
• power
 SCALING THEORY

RESULTS:
Density/Chip D
Delay/Ckt t
Power/Circuit P
Arbitrary scaling not advisable
• Electric field increases as dimensions
reduce
• Current magnitude increase
----------Transistor burns out.
Technology scaling

• Currently, technology scaling has a threefold

objective:
– Reduce the gate delay by 30% (43% increase in
frequency)
– Double the transistor density
– Saving 50% of power (at 43% increase in frequency)
• How is scaling achieved?
– All the device dimensions (lateral and vertical) are
reduced by 1/s
– Concentration densities are increased by s
– Device voltages reduced by 1/s (not in all scaling
methods)
– Typically 1/s = 0.7 (30% reduction in the dimensions)
 BITS Pilani
Pilani Campus

SCALING TECHNIQUES

SHORT CHANNEL EFFECTS

Scaling Models
Non scaling functions

• Material related parameters do not change with scaling

like

• Energy bandgap

• Work function

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FULL SCALING

Provides basic guideline to design of

scaled MOSFETs based on

constant electric field

FULL SCALING---
in accordance with poison equation

εsi (d2V(x) /dx2) = – ρ(x) = q · (ND+ - NA- - n + p)

• The scaling variables are:
– Supply voltage: Vdd  Vdd / s
– Gate length: L  L/s
– Gate width: W  W/s
– Gate-oxide thickness: tox  tox / s
– Junction depth: Xj  Xj / s
– Substrate doping: NA  NA  s
This is called constant field scaling because the
electric field across the gate-oxide does not
change when the technology is scaled
How to control Ē?
• POISSON’s EQUATION--
• Variation of carrier concentration with
position under electric field
• εsi (d2V(x) /dx2) = – ρ(x) space charge density
• εsi (dE(x) /dx) = q ·[ND + p- NA-n]
• ≈ q ND for n type semiconductor
• - (dV(x) /dx) = Ē
• Ē= negative gradient of potential
Some consequences of full scaling--
εsi (d2V(x) /dx2) = – ρ(x) = q · ND

30% scaling in the constant field regime (s =

1.43, 1/s = 0.7):
Device/die area:
W  L  (1/s)2 = 0.49
– In practice, microprocessor die size grows about 25% per technology generation!
This is a result of added functionality.

Transistor density:
(unit area) /(W  L)  s2 = 2.04
– In practice, memory density has been scaling as expected.
(not true for microprocessors…)

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Some consequences of full scaling--
• Gate capacitance:
W  L / tox  1/s = 0.7
• Drain current:
(W/L)  (V2/tox)  1/s = 0.7
• Gate delay:
(Cg)  V / I  1/s = 0.7
Frequency  s = 1.43
In practice, microprocessor frequency has doubled every
tech. generation (2 to 3 years)! This faster increase rate
is due to two factors:
1. the number of gate delays in a clock cycle decreases with time (the designs
become highly pipelined)
2. advanced circuit techniques reduce the average gate delay beyond 30%
per generation.
Some consequences of full scaling--

• Active capacitance/unit-area:
Power dissipation is a function of the operation
frequency, the power supply voltage and of the
circuit size (number of devices).

If we normalize the power density to Vdd2  f ,

we obtain the active capacitance per unit area
(=N Cgs/ area)
For a given circuit inc. by s
1/tox  s = 1.43
Some consequences of full scaling--

Similar to oxide capacitance per unit area:

1/tox  s = 1.43

In practice, for microprocessors, the active

capacitance/unit-area only increases between
30% and 35% because of interconnects

Because of inc., the two fold improvement in logic

density between technologies is not achieved.
 Some consequences of full scaling--
• Power dissipation:
Cg  Vdd2  f  (1/s)2 = 0.49

• Power density: Active power per chip area

(n Cgs  Vdd2  f ) / area  1; (not scaling down, so
no ease of packaging issues)
n –no. of gates switched/ per transition <1

Junction capacitance= Cj’= s Cj

qN a x p 0 qN a  2 sbi  N d  q s N a N d
C j0      
2bi 2bi  qN a  N a  N d  2bi N a  N d
 Do it yourself---calculate
scaled bi

• Barrier potential bi

bi

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Limitations of full scaling
• Requirement of reducing the voltage by the
same factor is too restrictive because there is a
general reluctance to depart from standardized
voltage levels of previous generation
• Reason---Entire set of analog drivers of
peripheral circuitry (communicating with digital
design) need to be redesigned
• So, we will require multiple power supplies and
complicated level shifters every new generation
• So power supply voltage is seldom scaled in
proportion to channel length.
• As a result---electric field has been gradually
rising over the generations rather than staying
constant
• Result---electro-migration, hot carrier injection in
gate oxide
• And High power dissipation
Short channel MOSFET- CE
Scaling

Gate capacitance:
Cg = W  L / tox  1/s = 0.7
Drain current:
(W/L)  (V/tox)  1 = 1
Gate delay:
(Cg)  V / I  1/s2 = 1/0.49
Frequency  s2

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• Power dissipation:
Cg  Vdd2  f  (1/s) = 0.7

• Power density: Active power per chip area

( Cg  Vdd2  f ) / area  s;
 Constant voltage scaling

If the power supply voltage is maintained constant

the scaling is called constant voltage.

In this case, the electric field across the gate-oxide

increases as the technology is scaled down
.
Due to gate-oxide breakdown, below 0.8µm only
“constant field” scaling is preferred.
C V scaling

As the field across oxide is increasing, it is necessary to develop

a set of guidelines that allow electric field to increase under
control.
It is desired that both vertical and lateral electric field change by
same multiplication factor. So that contours of electric field
pattern is preserved.
This assures the short channel effects do not become worse
upon scaling.
But , higher fields cause reliability problem

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• The scaling variables are:

– Supply voltage: Vdd  Vdd

– Gate length: L  L/s
– Gate width: W  W/s
– Gate-oxide thickness: tox  tox / s
– Junction depth: Xj  Xj / s
– Substrate doping: NA  NA  s2
Some consequences of CV scaling

εsi (d2V(x) dx2) = – ρ(x) = q · ND

Device/die area:
W  L  (1/s)2 = 0.49

Transistor density:
(unit area) /(W  L)  s2 = 2.04

Carrier velocity:
vdrift = µĒ  s
Some consequences of CV scaling
• Gate capacitance:
CGS W  L / tox  1/s = 0.7

• Drain current:
(W/L)  (V2/tox)  s = 1.43

• Gate delay:
(CGS  VDS) / ID  1/ s 2 = 0.49

• Frequency  s2 = 2.04
Some consequences of CV scaling

• Power dissipation:
Vds*Ids = CGS  V2  f  s = 1.43
• Power density:
Active power per chip area (P/AREA)
εox/tox  V2  f  s3 = 2.92----serious issue.
This puts burden on VLSI packaging technology to
dissipate extra heat generated on the chip
High Power density necessitates development of better ways
to get the heat out of an IC chip and package
• Active capacitance/unit-area (Cox):
power density/ (V2  f )  s
Peak supply current/ power
• Peak current from supply--- P
• [ no. of Transistor on chip x drain current (ID )]
• =[ (chip area) /(device area W  L) x ID

• P(s2/s)= Ps- increase peak current

• Cannot be ignored.
• In any design the power source can only provide a certain current at
the specified voltage;
• going beyond this, even as a transient can cause logic errors or worse
(damaging the power source).
Power density (power diss./ area)
Trans-conductance (gm)
Short channel MOSFET-CV Scaling
Generalised Scaling
to
control reliability problems

Dimensions  1/s
Vdd 1/ β
electric field [s / β]= 
 PARAMETER LONG SHORT
CHANNEL CHANNEL
Device dimensions tox, L, W 1/s 1/s
Electric field  if vdd does not
scale]

Depletion region width =(s/β)

Inversion layer charge density 
Carrier velocity, vd  1
Drift current 2/s /s= 1/β
Circuit delay 1/s 1/s
Power dissipation 3/s2 2/s2
Circuit density s2 s2
Power density 3 2
 Summary scaling factor 
Parameter Constant Field Constant Voltage
Supply voltage (Vdd) 1/ 1
Length (L) 1/ 1/
Scaling
Width (W) 1/ 1/
Variables
Gate-oxide thickness (tox) 1/ 1/
Junction depth (Xj) 1/ 1/
Substrate doping (NA)  
Electric field across gate oxide (E) 1 
Depletion layer thickness 1/ 1/
Gate area (Die area) 1/2 1/2 Device
Gate capacitance (load) (C) 1/ 1/ Repercussion
Drain-current (Idss) 1/ 
Transconductance (gm) 1 
Gate delay 1/ 1/2
Current density  3
DC & Dynamic power dissipation 1/2 
Power density 1 3 Circuit
Power-Delay product 1/3 1/ Repercussion
Scaling Models Summary
 Breakdown of Dennard scaling
• Transistor power reduction afforded by Dennard scaling allowed
manufacturers to drastically raise clock frequencies from one generation
to the next without significantly increasing overall circuit power
consumption.
• Since around 2005–2007 Dennard scaling appears to have broken
down. As of 2016, transistor counts in integrated circuits are still growing,
but the resulting improvements in performance are more gradual than the
speed-ups resulting from significant frequency increases.
• The primary reason cited for the breakdown is that at small sizes, current
leakage poses greater challenges and also causes the chip to heat up,
which creates a threat of thermal runaway causing increases energy
costs.
• The breakdown of Dennard scaling and resulting inability to increase
clock frequencies significantly has caused most CPU manufacturers to
focus on multicore processors as an alternative way to improve
performance.
 SCALING OF CONDUCTORS( wires)

CAPACITANCE C C/a
RESISTANCE R aR
TIME CONSTANT RC RC
CURRENT DENSITY J aJ
• R=ρL/wt---increases R’= sR

• C=εoxA/t------decreases C’= [1/s ] C

Interconnect delay does not scale

• Practical scaling is different as wire delay and
wire density does not scale at the same rate
as transistors scale
Multilevel Interconnect
Parasitic cap. of interconnect
Vertical Parasitic cap. of interconnect
• Poly over field oxide (area) 0.066 fF/um2
• Poly over field oxide (perimeter) 0.046 fF/um
• Metal-1 over field oxide (area) 0.030 fF/um2
• Metal-1 over field oxide (perimeter) 0.044 fF/um
• Metal-2 over field oxide (area) 0.016 fF/um2
• Metal-2 over field oxide (perimeter) 0.042 fF/um
• Metal-1 over poly (area) 0.053 fF/um2
• Metal-1 over poly (perimeter) 0.051 fF/um
• Metal-2 over poly (area) 0.021 fF/um2
• Metal-2 over poly (perimeter) 0.045 fF/um
• Metal-2 over metal-1 (area) 0.035 fF/um2
• Metal-2 over metal-1 (perimeter) 0.051 fF/um
Horizontal and vertical cap.
Parasitic cap at node 2
Interconnect delays
Impact of scaling on parasitic cap.

• Shallow s/d junctions

Interconnects scaling
– Higher densities are only possible if the
interconnects also scale.
– Reduced width  increased resistance
– Denser interconnects  higher parasitic
capacitance due to mutual coupling
– To account for increased parasitics and
integration complexity more interconnection
layers are added:
• thinner and tighter layers  local interconnections
• thicker and sparser layers  global interconnections
and power
Interconnects are scaling as expected
Global vs Local wires
• Thin Local wire as their delay is negligible in
comparison to global wire.
• Thick global wires-----
• Because already large length, and with scaling
we add more functionality-> increased chip
area length further increases
• If we reducing cross-sectional area (w x t)->
increases resistance , increase current density
(electro-migration problem)
So, do not scale global wires rather scale up.
But this increases capacitance
 Electromigration -long term wear out mechanism

Lim its d c-cu rren t to 1 m A/  m

• Movement of metal atoms in wire due to
high current stress
• High current density increases the number
of electrons scattering against the atoms
of conductor , hence the speed at which
those atoms are displaced
• This drift can also cause drift towards
other nearby conductors (whisker failure)
• Causing short circuit
Best strategy for interconnect scaling

• Keep global wires to min.

• Scale down the size and spacing of local wires in step with
device scaling for local wiring

• Use un-scaled or even scaled up global wires on top levels.

Use repeaters in global wires,
• increase inter-metal dielectric thickness to keep wire
capacitance per unit length constant
Wiring hierarchy

Thicker and sparse

Thinner and close