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Experiment-1

SAMPLE AND HOLD CIRCUIT USING OPAMP

AIM: To test a sample and hold circuit using opamp and FET.

APPARATUS: FET BFW11, opamp 741, diode BY127, resistors (100KΩ, 1KΩ, 10KΩ),
capacitors (0.01μF-2).

THEORY: The basic sample and hold circuit is the combination of switch and a capacitor as
shown below.

Vin S Vout

The switch ON and OFF is controlled by a control signal called sample signal. The input
signal is transferred to the capacitor when ‘S’ is closed. Capacitor holds the value to which it has
charged when ‘S’ is opened. The implementation of switch is done by using an FET and input is
applied to a buffer to prevent loading.

Given data:

Fin = 1KHz

Fs = 2Fin according to Nyquist criterion

= 2KHz

Ts = 1/Fs

= 0.5ms

Ibias = 1.5μA from the data sheets

V0 = opamp droop voltage = 40mV

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Calculations:

V0/Ts = Ibias/Cmin

Cmin = 1.5μA*0.5ms/40mV

= 18.75nF

Cmax = Ts/5Rs where Rs is the source resistance

= 0.5ms/5*150 = 0.66μF

CIRCUIT DIAGRAM:

PROCEDURE:

1. Rig up the circuit as shown in the circuit diagram.

2. Apply sampling voltage to the gate of FET.
3. Apply input voltage 10 Vp-p, 1KHz sinewave to the first opamp input.
4. Let the initial sampling frequency of the negative pulse be 2KHz and note down the hold
time from the output.
5. Increase the sampling frequency in steps of 1KHz upto 10KHz and note down the
corresponding hold time.
6. Tabulate the results and plot a graph for sampling frequency Vs hold time.

TABULAR COLUMN:
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Sampling frequency (fs) Hold time (th)

RESULT: To obtain proper sampling the nyquist criteria has to be satisfied,

which states the sampling frequency has to be equal to or greater than the
maximum frequency content of the signal. If the criteria is not met then there
is aliasing effect obtained and the signal cannot be reconstructed properly.

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EXPERIMENT-2
ANALOG MULTIPLEXER

AIM: To verify the operation of a unipolar / bipolar analog multiplexer IC.

APPARATUS: CD4051, resistor (1KΩ-8), regulated power supply.

THEORY: Multiplexer is a device which selects one out of n inputs at a time, depending on the
addresses given to the select lines.
CD4051 is an 8-channel analog multiplexer with 3 digital select lines (S0 to S2),
an active low enable input CE bar, 8 independent inputs (Y0 to Y7) and an output Z. With CE
bar LOW, one of the 8-input switches (low impedance on state) is selected by S2S1S0. With CE
bar high all the input switches are in high impedance off state independent of S2S1S0. Vcc and
GND are the supply voltage and ground pins for digital control inputs. Some of the features of
CD4051 are,
 Wide analog input voltage range(±5V)
 Low on resistance
 Logic level transition to enable 5V logic to communicate with ±5V analog signals
 Output capability nonstandard
 IC category- MSI

CIRCUIT DIAGRAM:

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UNIPOLAR BIPOLAR

PROCEDURE:

1. Seven resistors of 1KΩ value are connected in series between the supply 5V and GND,
for unipolar operation.
2. The value of each node a log this series is also noted.
3. We connect this network of resistors with corresponding pins of IC 4051.
4. The select lines are used to multiplex one input at a time. Note down that output.
5. Next connect the resistor network and corresponding notes, to only that input pin which
is to be selected by select lines. The other inputs are not connected(floating inputs).
6. In each case note down the output.
7. The output is noted down for the entire range.
8. For bipolar operation the resistors are connected between +5V and -5V.

TABULAR COLUMN:

SELECT LINES EXPECTED OUTPUT IN OBTAINED OUTPUT IN

A2 A1 A0 VOLTS VOLTS

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RESULT: for each select line the corresponding analog signal is obtained.

Inference: the function of the mux is to obtain an analog signal for the
corresponding select line. In the unipolar mux the analog signals are with the
same polarity and in the bipolar mux the analog signals have both polarities
and depending upon the select lines the analog signal is obtained.

AIM: to rig up and test a PGA using a DAC and other components

APPARATUS: : DAC 0800, OPAMP, resistors, capacitors, Power supply, DMM.

THEORY : Basically a PGA(programmable gain amplifier) using DAC consists of an opamp.

Here is an amplifier is Vo/Vin which is controlled by the digital input given to the DAC
connected in the feedback path of the opamp.

The output of the DAC is given by, Vod=[Vref/2^n][∑2^i*ai], i varying from 0 to (n-1)

Where n is the number of digits in th edigital input. Vref is the reference voltage to the DAC.
According teh idal opamp characteristics Vod must be equal to Vin. Therefore substituting
Vod=Vin

Therefore, [Vref/2^n][ ∑2^i*ai]=Vin i varying from 0 to (n-1)

Gain= V0/Vin=2^8[∑2^i*ai] i varying from 0 to 7

For digital inputs 11111111

V0/Vin=256/255>1

PROCEDURE :

1. Connect the circuit as shown in fiqure.

2. Change input bits one at a time and note down the corresponding output

3. Calculate the practical gain from the ratio of Vo to Vin.

4. Compare practical gain with theoritical gain.

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CIRCUIT DIAGRAM :

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TABULAR COLUMN :

Select lines Output Gain

voltage
D7 D6 D5 D4 D3 D2 D1 D0

RESULT : the gain of the output is obtained for the corresponding select lines.

INFERENCE: the mux is used to obtain the analog values for the corresponding select lines and
these analog values are amplifer fot the required gain.

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EXPERIMENT 3

R-2R LADDER NETWORK

AIM: 1. To study the operation of 4 bit DAC using R-2R ladder network.
APPARATUS: Resistors (1KΩ and 2KΩ), digital multimeter, springboard, op-amp 741,
connecting wires and IC trainer kit.
THEORY: A ladder is a series/parallel resistor network. An R-2R ladder type DAC is shown in
the figure. It requires only two resistor values R and 2R.

Here S0,S1,S2 and S3 are electronic switches which are digitally controlled, when 1 is
present on the MSB line, switch S3 connects the resistor 2R to Vref. Conversely when 0 is
present on MSB line, switch S3 connects the same resistor to the ground line. Since the ladder is
composed of linear resistors, it is a linear network and the principal of super position can be
used. This means that the total output voltage due to a combination of input digital levels can be
found by simply taking the same of the output levels caused by each digital input individually.

CIRCUIT DIAGRAM:
A) R-2R LADDER NETWORK:

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A 4 bit DAC using R-2R ladder network and an op-amp voltage follower acting as a
buffer stage D0, D1, D2, D3 are the digital inputs. Each digital input may be low (0) or high (1).

VR(0) = 0, VR(1) = VR= reference voltage can be selected depending on the maximum
analog o/p voltage required. If the digital inputs are obtained from a digital IC trainer, then V R =
+5 volts = constant/ DC reference voltage.

The analog output voltage Vo for a 4-bit DAC shown above can be written as:

Output Vo = (23 D3 + 22 D2 + 21 D1 + 20 D0) VR

V0 = VR/ 24 (2R/3)

V0 = (8D3 + 4D2 + 2D1 + D0) VR/24

V = VR / 24

V = VR/ 24 * (2R/3) = smallest incremental change in the output voltage V0

PROCEDURE:

1. Verify all the components and patch-chords whether they are in good condition.

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2. Make connection as shown in circuit diagram.

3. Give supply to the trainer kit.
4. For different digital inputs measure the output voltage using multimeter.
5. Verify whether the theoretical value is matching with practical values and observe the
output.

TABULAR COLUMN:

Decimal Digital inputs Theoretical value V0 Experimental value V0

equivalent D3 D2 D1 D0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

RESULT: The digital values are converted into analog values.

Inference: the binary weight and the R-2R ladder networks are designed to convert the
digital inputs into analog outputs. A four bit DAC is designed with reference of 5V.

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EXPERIMENT 4:
3 BIT FLASH ADC
AIM: 1. To realize Flash ADC to convert the specified volts to 3 bit binary numbers.
APPARATUS: LM 324, IC 74148, Patch-chords, power chord and IC trainer kit.

THEORY: The Flash converter is the highest – speed ADC available, but it requires much more
circuitry than other types. For example 6-bit Flash ADC requires 63 analog comparators, while
an 8-bit unit requires 255 comparators and a 10-bit converter requires 1023 comparators. The
large number of comparators has limited the size of Flash converters are currently available in 2
to 8-bit units, and most manufacturers predict that 9 and 10-bit units will the market in the near
future.

In general an N-bit Flash converter would require 2 N-1comparators,2N resistors and the
necessary encoder logic.

PROCEDURE:
1) Check all the components and IC packages using multi-meter and digital IC tester.
2) Make connection as shown in circuit diagram.
3) Give supply to the trainer kit.
4) Provide Analog input voltage through 0 to 5v through variable power supply.
5) Verify the function table sequence of 2-bit Flash ADC and 3-bit Flash ADC and observe
the outputs.

CIRCUIT DIAGRAM:

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Resolution= 1.25 V

Tabular Column

Analog Input Comparator outputs Digital output

C1 C2 C3 C4 C5 C6 C7 C B A

0-0.5 V 1 1 1 1 1 1 1 1 1 1

0.5 – 1 V 0 1 1 1 1 1 1 1 1 0

1 – 1.5V 0 0 1 1 1 1 1 1 0 1

1.5 – 2.0 V 0 0 0 1 1 1 1 1 0 0

2 – 2.5 V 0 0 0 0 1 1 1 0 1 1

2.5 – 3.5 V 0 0 0 0 0 1 1 0 1 0

> 4V 0 0 0 0 0 0 1 0 0 1

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RESULT: the given analog value is converted into its digital value.

INFERENCE : the analog value is given to the negative of the comparator and
reference is given to the positive of the comparator and depending on the
difference which is greater the output is either positive or negative. And the
priority encoder gets the input from these comparator and the digital output
is obtained from the priority encoder.

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EXPERIMENT 5
8 BIT DAC USING IC 0800

AIM: to study the operation of 8 bit DAC using IC DAC 0800

COMPONENTS AND EQUIPMENTS REQUIRED: DAC 0800, resistors, capacitors, patch

cords and IC trainer kits.

THEORY:

 Fast settling output current: 100 ns

 Full scale error: ±1 LSB
 Nonlinearity over temperature: ±0.1%
 Full scale current drift: ±10 ppm/°C
 High output compliance: -10V to +18V
 Complementary current outputs
 Interface directly with TTL, CMOS, PMOS and others
 2 quadrant wide range multiplying capability
 Wide power supply range: ±4.5V to ±18V
 Low power consumption: 33 mW at ±5V
 Low cost

Description

The DAC0800 series are monolithic 8-bit high-speed current-output digital-to-analog converters
(DAC) featuring typical settling times of 100 ns. When used as a multiplying DAC, monotonic
performance over a 40 to 1 reference current range is possible. The DAC0800 series also features
high compliance complementary current outputs to allow differential output voltages of 20 Vp-p
with simple resistor loads. The reference-to-full-scale current matching of better than ±1 LSB
eliminates the need for full-scale trims in most applications, while the nonlinearities of better
than ±0.1% over temperature minimizes system error accumulations.

The noise immune inputs will accept a variety of logic levels. The performance and
characteristics of the device are essentially unchanged over the ±4.5V to ±18V power supply
range and power consumption at only 33 mW with ±5V supplies is independent of logic input
levels.

The DAC0800, DAC0802, DAC0800C and DAC0802C are a direct replacement for the DAC-
08, DAC-08A, DAC-08C, and DAC-08H, respectively. For single supply operation, refer to AN-
1525.

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PROCEDURE:
1. verify all the components and patch chords weather they are in good condition
2. make connections as shown in circuit diagram
3. give supply to the trainer kit
4. for different digital inputs measure the output voltage using multi meter
5. verify whether the theoretical values is matching with practical values and observe
the outputs.

CIRCUIT DIAGRAM:

TABULAR COLUMN:

Digital inputs Output voltage in volt

D7 D6 D5 D4 D3 D2 D1 D0 Practical Theoretical

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RESULTS:

INFERENCE:

EXPERIMENT 6: 8-BIT UNIPOLAR ADC USING 0804

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AIM: To rig up an 8 bit unipolar successive approximation type ADC and verify the operation
for a full scale input voltage of 5V.

APPARATUS: IC 0804, LED bank, Function generator, regulated power supply

THEORY: ADC 0804 is an 8-bit ADC working on successive approximation technique. The
important features of this IC are on chip clock generator, differential analog voltage input, and
no requirement of zero adjustment.

The pin diagram of ADC 0804 is shown in figure. The start conversion signal is to
be applied to WR bar. The start conversion signal is applied to WR bar. The start of conversion
is to be first made low and then high. To start conversion is to be first made low and then high.
To start conversion CS bar must be low. When both CS bar and WR bar goes low, the converter
is reset. When WR bar returns to high state the conversion begins. When both CS bar and RD bar
are low, the digital is available on the output lines. The range of clock frequency is 100khz-
800khz. The clock may be supplied from an external source or it can be generated by an internal
clock generator.

PROCEDURE:

 Rig up the circuit as shown in circuit diagram

 Apply input to pin 6 through a potentiometer

 Vary the pot and set the input at 0.5V and note down the status of LEDs on the LED
bank which represents the equivalent digital code.

 Change the input with an increment of 0.2V and note down the output upto 5V.

 Tabulate the readings

 Calculate resolution using the formula

 Plot a graph for Vin Vs digital output

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CIRCUIT DIAGRAM:

TABULAR COLUMN:

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Analog Input Digital output Decimal Decimal Output

Voltage output(Practical) (Ther)

D7 D6 D5 D4 D3 D2 D1

RESULT:

INFERENCE:

EXPERIMENT 7

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To determine the step response of first order system using RC circuit

AIM : Determine the output response of first order system using RC circuit, measure‘t’ for different
values of R, L & C

APPARATUS: DRB, DCB, DIB signal generator and CRO

THEORY:

The first order system is one where the highest order of derivation describing the system behavior
is one. It os described by the equation: a1dc(t)/dt+a0c(t)=b0r(t) where a1 a0 b0 are all constants.
First order system are commonly found in measurement systems.
The time constant s of such a system is defined as the time to reach 63.2% of the final value. It
has some dimension at the time i.e is equal to the product of resistance and capacitance used in
common RC circuit which is considered here. Since constant is indicative of low, fast is the
system response to reach the final value.

PROCEDURE:

1. Connect the circuit as shown in figure.

2. Adjust the values of R and C for different conditions

3. the values of R and C are varied randomly to get a response through DRB and DCB

4. the 63.2% of the output response got is calculated. It is projected from this value
downwards to get the time constant.

5. the rise time corresponding to the output is also calculated.

6. the procedure is repeated for different values of R and C.

CIRCUIT DIAGRAM:

Sl no. R in ohm C in farad t theoretical t Practical

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RESULT:

EXPERIMENT 8

To determine the step response of the second order system using RLC circuit.

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AIM: Determine the output response of a second order system for under damped, over damped
and critically damped cases for step input. Also determine rise time, overshoot, and settling time
for under damped condition. Verify using theoretically calculated values

APPARATUS: DRB, DCB, DLB, signal generator and CRO.

THEORY: For second order system the denominator of the closed loop transfer function is

quadratic transfer function where:

x(t) = Response of the System,

u(t) = Input to the System,
= Damping Ratio,
n=Undamped Natural Frequency,
Gdc= The DC Gain of the System.

Second order systems are important for a number of reasons.  They are the
simplest systems that exhibit oscillations and overshoot.

 Many important systems exhibit second order system behavior.

 Second order behavior is part of the behavior of higher order systems and
understanding second order systems helps you to understand higher order
systems.

he parameters you find in a second order system determine aspects of various

kinds of responses. Whether we are talking about impulse response, step response
or response to other inputs, we will still find the following relations.
, the damping ratio, will determine how much the system oscillates as the
response decays toward steady state.
n,the undamped natural frequency, will determine how fast the system oscillates
during any transient response.
Gdc, the DC gain of the system, will determine the size of steady state response
when the input settles out to a constant value.

PROCEDURE:

1. connections are made as per the circuit diagram

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2. Design the values of R L C for critically damped, over damped and under damped
conditions.

3. Observe the response on CRO. From response measure rise time, peak over shoot, peak
time for critically damped, over damped and under damped conditions.

CIRCUIT DIAGRAM:

TABULAR COLUMN:

Sl.no Condition R in ohms L in Henry C in Farad

1
2 Critically damped

3
1 Over damped

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2
3
1
2 Under damped

Sl. Parameters values Rise time Peak time Settling time Max overshoot

no

R L C The Prac The Prac The Prac The Prac

RESULT:

EXPERIMENT 9

To determine the response of lead, lag and lead lag circuits

AIM: To study the response of Lead, lag and lead-lag network.

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APPARATUS: DRB, DRC, ASG, Oscilloscope, connecting wires and Signal generator.

PROCEDURE:

1) Connections for the Lead,Lag,Lead-Lag networks are made as shown in figure

2) He circuit is designed to get a phase angle of 30deg at 500HZ

3) He designed values of resistance and capacitance are adjusted.

4) An input voltage of 5V is adjusted.

5) By varying the frequency of the input voltage, note down the output voltage and phase
angle.

6) The readings are tabulated in tabular column.

7) The magnitude and phase plot are plotted on a semilog graph sheet and compare the
results with the designed values.

8) Same procedure is repeated for Lag and lead network.

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1) CIRCUIT DIAGRAM PHASE LEAD NEWORK

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TABULAR COLUMN

Frequency in Hz Vin in Volts Vout in Volt Gain Gain in dB Phase angle

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2) CIRCUIT DIAGRAM PHASE LAG NEWORK

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Tabular column

Frequency in Vin in Volts Vout in Volt Gain Gain in dB Phase angle

Hz

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CIRCUIT FOR LEAD LAG CIRCUIT:

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Tabular column

Frequency in Vin in Volts Vout in Volt Gain Gain in dB Phase angle

Hz

RESULT:

EXPERIMENT 10:

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RELAY DRIVING CIRCUIT USING LDR

AIM: 1. To conduct an experiment to study the operation of relay under two circumstances:
i) Relay to be ON when light falls on LDR.
ii) Relay to be ON when light falls on LDR is interrupted.
APPARATUS: Resistors (330 Ω ,6.8K,10K pot),LED,LDR,optocoupler,Relay,ransistor SL100,
digital multimeter , connecting wires and base board.

PROCEDURE:

1. Connections as per the circuit diagrams are made one by one.

2. Light is allowed to fall on LDR and the condition of LED and that of the Relays noted
down.

3. Light on LED is interrupted and conditions of LED and Relay is noted down.

4. Also, optocoupler circuit is rigged up and condition of LED is noted for no obstruction
and paper obstruction.

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CIRCUITDIAGRAM:

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TABULAR COLUMN:

Relay Connection Condition of LDR LED condition

Illumination ON
Normally open (NO)
Dark OFF

Illumination OFF
Normally closed (NC)
Dark ON

RESULTS:

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EXPERIMENT 11

To determine the response of P, PI and PID

AIM: To design and test proportional controller

Apparatus: OPAMP 741, resistors, Capacitors and Oscilloscope

Theory: In the proportional control algorithm, the controller output is proportional to the error
signal, which is the difference between the set point and the process variable. In other words, the
output of a proportional controller is the multiplication product of the error signal and the
proportional gain.

This can be mathematically expressed as

where

 Pout: Output of the proportional controller

 Kp: Proportional gain
 e(t): Instantaneous process error at time t. e(t) = SP − PV
 SP: Set point
 PV: Process variable

Procedure:

1. The proportional gain and the resistor values are calculated for the given problem

2. the circuit connections are made as per the circuit diagram

3. by maintaining error voltage as zero. The output Vout is adjusted for initial
conditions using V0 (if it is set to zero)

4. the input error voltage Ve is applied and increased gradually within the given range
and corresponding output voltage Vout is measured

5. a graph of ΛVe versus ΛVout is drawn.

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Circuit diagram:

TABULAR COLUMN:

Ve Vout practical Vout theoritical

RESULT:

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AIM: To design and test PI controller

APPARATUS: opamp 741, resistor, capacitors, connecting wires, probes,DMM.

PROCEDURE:
1. connect the circuit as shown in the circuit diagram.
2. apply 5 Vpp square wave of 1KHz from the signal generator
3. fix the resistance and capacitance as per the design
4. obtain the output waveform and plot it is a graph.

CIRCUIT DIAGRAM:

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RESULTS:

AIM: To design and test PID controller

APPARATUS: Op-amps, capacitors (10μF, 100μF), resistors
(48kΩ,10kΩ,333kΩ,840kΩ,127kΩ), ic base board spring base board, power supply (±15V, 0-
30v)

PROCEDURE:

 The circuit is designed for the given problem

 The circuit connections is as per the circuit diagram

 By maintaining Ve as zero output is set for initial voltage ( if it is given otherwise it is set
to zero).

 The error voltage Ve (step change) is applied at the input and the output is note down
with respect to time.

 After Vout reached saturation the individual output are measured and verified with the
obtained output.

 A graph of output voltage Vout versus time is drawn.

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CIRCUIT DIAGRAM:

RESULTS:

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EXPERIMENT 12

AIM : Using MATLAB/LAB VIEW software, plot the Bode plot and Root locus with and
without compensation for a given transfer function and specifications. Verificatioto n using
Theoretical values.

ALGORITHM FOR BODE DIAGRAM

 The open loop gain K of the system is determined to satisfy the requirement of error
constant.
 The bode plot is drawn for uncompensated system using the value of K.
 Determine the phase margin of the uncompensated system from the plot.
 Determine the phase lead ᶲm to be provided by the lead compensator using the relation.
ᶲm = ᶲs - ᶲu + €
ᶲs = specified or desired phase margin.
ᶲu = phase margin of the uncompensated system G(s)
€ = The margin of the safety to account for the increase phase lead of G(s) due to increase
in gain cross over frequency.

 Determine the attenuation α

 α = (1- sin ᶲm )/(1+sin ᶲm)
 Determine the frequency where the magnitude of the uncompensated system is -20 log
(1/sqrt(α)).This frequency is selected as the new gain cross over frequency ω c .This
frequency corresponds to ωm of the phase lead compensator at which it produces a phase
lead of ᶲm.
 The corner frequencies of the lead network are determined
Z c =1/T and Pc = 1/ (α T)
Transfer function of lead compensator Gc (s) = α(1+ST)/(1+αTS)

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PROGRAM
N=[15];
D= [1 1 0];
Figure(1);
Margin (n,d);
[gm pm wcp wcg] = margin (n, d);
Pms = 45;
L=11;
Pml = pms – pm +l;
Pmr = pml * pi/180;
A2 = 1- sin (pmr);
A3 = 1+sin(pmr);
A=a2 / a3 ;
A1 = 20* log 10(sqrt (a));
N=conv (n, 1/a);
W=100;
For i=wcg;.01;w
[m, p] = bode (n, d, i);
M=20*log 10(m);
If m>= a;
f = I;
break;
end;
end;
w1=f * (sqrt (a));
w2=f/ (sqrt (a));
n1 = [1,w1];
d = [1,w2];
[nc, dc] = series (n, d, n, d);
Figure (2);
Margin (nc, dc);
End;

RESULT :

INFERENCE :

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