Single-Chip Low-Power FM Receiver For Portable Devices

QN8075
Single-Chip Low-Power FM Receiver for Portable Devices
__________________________ General Description __________________________

The QN8075 is a high performance, low power; full-featured single-chip stereo FM receiver designed for mini-speakers,
MP3 players. It integrates FM receive functions, auto-seek and clear channel scan. Advanced digital architecture enables
superior receiver sensitivity and crystal clear audio.
With its small footprint, minimal external component count and multiple crystal clock frequency support, the QN8075 is
easy to integrate into a variety of small form-factor low power portable applications.
_______________________________ Key Features ___________________________

• Worldwide FM Band Coverage • Direct Earphone Driving
• 60 MHz to 108 MHz full band tuning in
50/100/200 kHz step sizes • Adaptive Noise Cancellation
• 50/75μs de-emphasis • Integrated adaptive noise cancellation (SNC, HCC,
SM)
• Ease of Integration
• Small footprint, available in SOP16 and SSOP16 • Volume Control
package • High Performance
• 32.768 kHz and Multiple MHz crystal and direct • Superior sensitivity, 1.4 µVEMF
clock input supported • 65dB stereo SNR, 0.03% THD
• I2C control interface • Improved auto channel seek and fast tune
• Very Low Power Consumption • L/R separation 44dB
• 12.8mA typical • Robust Operation
• VCC: 2.7~5.0V, integrated LDO, support battery • -250C to +850C operation
direct connection • ESD protection on all input and output pads
• Power saving Standby mode
• 1 KHz Tone Generator Inside
• Low shutdown leakage current
• Accommodate 1.6~3.6V digital interface
___________________________ Typical Applications ________________________

• Portable Audio & Media Players • Portable radios
• Mini-speakers
QN8075 Functional Blocks:
Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 1

Confidential A Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA).
Advance Technical Information. This is a product under development. Characteristics and specifications are subject to change without notice.
QN8075
CONTENTS
1 Pin Assignment ................................................................................................................................................3
2 Electrical Specifications ..................................................................................................................................4
3 Functional Description ....................................................................................................................................9
3.1 FM Receiver ............................................................................................................................... 9

3.2 Audio Processing ...................................................................................................................... 10
3.3 Auto Seek (CCA) ...................................................................................................................... 11
4 Control Interface Protocol .............................................................................................................................12
5 Typical Application Schematic .....................................................................................................................13
6 Ordering Information.....................................................................................................................................14
7 Package Description ......................................................................................................................................15
8 Solder Reflow Profile ....................................................................................................................................18
8.1 Package Peak Reflow Temperature .......................................................................................... 18

8.2 Classification Reflow Profiles .................................................................................................. 18
8.3 Maximum Reflow Times ..........................................................................................................19
REVISION HISTORY
REVISION CHANGE DESCRIPTION DATE
0.1 Draft 2011-7-14

0.2 Modified parameters according to test report 2011-8-23

1 Pin Assignment
(Top View)
Figure 1 QN8075 Pin Out SOP16/SSOP16
Table 1: Pin Descriptions

SOP16/SSOP16 NAME DESCRIPTION
1/2/3/11/15/16 NC No connect
5/6/14 GND Ground
4 RFI FM Receiver RF input
7 SCL Clock for I2C serial bus.
Bi-directional data line for I2C serial
8 SDA
bus.
9 XCLK Clock input
10 VCC Voltage supply
12 ALO Analog audio output – left channel
13 ARO Analog audio output – right channel

2 Electrical Specifications
Table 2: Absolute Maximum Ratings
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Vbat Supply voltage VCC to GND -0.3 5 V
VIO1 Logic signal level SCL, SDA to GND -0.3 3.6 V

o
Ts Storage temperature -55 +150 C
Notes:
1. VIO is pulled up externally via resisters.
Table 3: Recommended Operating Conditions

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
Vcc Supply voltage VCC to GND 2.7 3.3 5.0 V

o
TA Operating temperature -25 +85 C
RFin RF input level1 Peak input voltage 0.3 V
VIO2 Digital I/O voltage 1.6 3.6 V

Notes:
1. At RF input pin, RFI.

Table 4: DC Characteristics
(Typical values are at Vcc = 3.3V and TA = 25oC).
IRX Receive mode supply current 12.8 mA
IIDLE Idle mode supply current Idle mode 660 μA
ISTBY Standby mode supply current Standby mode 58 μA
Interface
VOH High level output voltage 0.9*VIO1 V
VOL Low level output voltage 0.1*VIO1 V
VIH High level input voltage 1.1 V
VIL Low level input voltage 0.3 V

Notes:
Table 5: AC Characteristics
SYMBOL PARAMETERS CONDITIONS MIN TYP MAX UNIT

1
Fxtal Clock frequency 0.032768 -40 MHz
Clock frequency
Fxtal_err Over temperature, and aging -50 50 ppm
accuracy
Notes:
1. See also XTAL_DIV[10:0], PLL_DLT[12:0]

Table 6: Receiver Characteristics
(Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC).
SYMBOL PARAMETERS CONDITIONS MIN TYP MAX UNIT

SRX FM sensitivity (S+N)/N = 26dB 1.4 μVEMF
IP3 Input referred IP3 At maximum gain 120 dBμV
RejAM AM suppression 52 dB
Rin RF input impedance At pin RFI 5 kΩ
Adjacent channel
SRX_Adj 200 kHz offset 49 dB
rejection
Alternate channel
SRX_Alt 400 kHz offset 62 dB
rejection
MONO, Δf = 22.5 kHz1 58
SNRaudio_in Audio SNR STEREO, Δf = 67.5 kHz, Δfpilot = dB
67
6.75 kHz
MONO, Δf = 75 kHz 0.04 %
THDaudio_in Audio THD STEREO, Δf = 67.5 kHz, Δfpilot =
0.03 %
6.75 kHz
αLR in L/R separation 47 dB
AttPilot Pilot rejection 70 dB
L and R channel gain imbalance
BLR L/R channel imbalance 1 dB
at 1 kHz offset from DC
De-emphasis time PETC = 1 71.3 75 78.7 μs

τemph1
constant PETC = 0 47.5 50 52.5 μs
Vaudio out Audio output voltage Peak-Peak, single ended 1 1 V
Audio output Loading
RLOAD 32 Ω
Resistance
Audio output loading
CLOAD 20 pF
capacitance
RSSIerr RSSI uncertainty -3 3 dB
Audio THD after RLOAD=32Ω, 1 Vpp output 0.05

THDdriver %
earphone driver RLOAD=1kΩ, 1 Vpp output 0.03
Notes:
1. Guaranteed by design.
Table 7: Timing Characteristics


From power up to register

τpup Chip power-up time 1 20 ms
access.
Channel switching From any channel to any
τchsw 200 ms
time1 channel.
Receiver Timing
Wake-up time from
τwkup Standby to RX mode. 200 ms
standby to receive
τtune Tune time Per channel during CCA. 50 ms
Notes:
Table 8: I2C Interface Timing Characteristics


fSCL I2C clock frequency 400 kHz
tLOW Clock Low time 1.3 μs
tHI Clock High time 0.6 μs
SCL input to SDA
tST 0.8 μs
falling edge start 1,3
SDA falling edge to
tSTHD 0.8 μs
SCL falling edge start3
trc SCL rising edge3 Level from 30% to 70% 300 ns
3
tfc SCL falling edge Level from 70% to 30% 300 ns
SCL falling edge to
tdtHD 20 ns
next SDA rising edge3
SDA rising edge to
tdtc 900 ns
next SCL rising edge3
SCL rising edge to
tstp 0.6 μs
SDA rising edge 2,3
tw Duration before restart3 1.3 μs
SCL, SDA capacitive
Cb 10 pF
loading3
Notes:
1. Start signaling of I2C interface.
2. Stop signaling of I2C interface.

Figure 2 I2C Serial Control Interface Timing Diagram

3 Functional Description
The QN8075 is a high performance, low power, single chip FM receiver IC that supports worldwide FM broadcast band (60
to 108MHz).
Figure 3 QN8075 Functional Blocks
The QN8075 integrates FM receive functions, including

RF front-end circuits (LNA, Mixer and channel 3.1 FM Receiver
selective filter etc), a fully digitized FM demodulator, The QN8075 receiver uses a highly digitized low-IF
MPX decoder, de-emphasis and audio processing (SM, architecture, allowing for the elimination of external
HCC, and SNC). Advanced digital architecture enables components and factory adjustments.
superior receiver sensitivity and crystal clear audio. The
QN8075's Auto Seek function enables automatically The received RF signal is first amplified by an integrated
selecting the channel of better sound quality. LNA and then down converted to an intermediate
frequency (IF) via a quadrature mixer. To improve image
The QN8075 supports a small footprint, high level of rejection (IMR), the quadrature mixer can be
integration and multiple crystal clock frequencies. programmed to be at high-side or low-side injection. An
These features make it easy to be integrated into a integrated IF channel filter rejects out-of-channel
variety of small form-factor, low-power portable interference signals. AGC is also performed
applications. Low phase noise digital synthesizers and simultaneously to optimize the signal to noise ratio as
extensive on-chip auto calibration ensures robust and well as linearity and interference rejection. The filtered
consistent performance over temperature and process signal is digitized and further processed with a digital
variations. An integrated voltage regulator enables FM demodulator and MPX decoder. Audio processing is
direct connection to a Li-ion battery and provides high then performed based on received signal quality and
PSRR for superior noise suppression. A low-power channel condition. Two high-quality audio DACs are
IDLE and Standby mode extends battery life. integrated on chip to drive the audio output.
A receive signal strength indicator (RSSI) is provided

and can be read from RSSIDB [7:0]. Figure 4 shows the
curve of RSSI vs. different RF input levels. Auto seek
utilizes RSSI to search for available channels.

The following figure is measured at FM=88MHz. The RSSI Curve is not varied by FM frequency.
Figure 4 RSSI vs RF Input
3.2 Audio Processing In receive mode, stereo noise cancellation (SNC) for
FM only, high cut control (HCC) and soft mute (SM)
are supported. Stereo noise suppression is achieved by
The MPX signal after FM demodulation is comprised gradually combining the left and right signals to be a
of left and right channel signal, pilot in the following mono signal as the received signal quality degrades.
way: SNC, HCC and SM are controlled by SNR and
multipath channel estimation results. The three
functions will be archived automatically in the device.
Here, L(t) and R(t) correspond to the audio signals on The QN8075 has an integrated mono or stereo audio
the left and right channels respectively, f = 19 kHz, θ is status indicator. There is also a Read ST_MO_RX
the initial phase of pilot tone and α is the magnitude of (Reg04h [0]) bit to get status. In addition, there also is a
the pilot tone. In stereo mode, both L and R are force mono function to constrain output mono in
recovered by de-MPX. In mono mode, only the L+R Reg00h[2].
portion of audio signal exists. L(t) and R(t) are
recovered by de-MPX. Two selectable de-emphasis time constants (75us and
50us) supported.

Figure 5 Audio Response
The audio output can be muted with the MUTE_EN

(Reg14h[7]) bit and the output can also be replaced by 3.3 Auto Seek (CCA)
an internally generated 1KHz tone whenever the RFI
has a RF signal input. In receive mode, the QN8075 can automatically tune to
stations with good signal quality. The auto seek
function is referred to CCA (Clear Channel
Assessment).

4 Control Interface Protocol
The QN8075 supports the standard I2C serial interfaces. The QN8075 acknowledges each byte after completion
At power-on, all register bits are set to default values. of each transfer. The I2C master terminates the write
operation by generating a stop condition (P).
I2C Serial Control Interface
The read operation consists of two phases. The first
2 phase is the address phase. In this phase, an I2C master
QN8075 provides an I C-compatible serial interface. It initiates a write operation to the QN8075 by generating a
consists of two wires; serial bi-directional data line start condition (S) followed by the QN8075 slave address,
(SDA) and input clock line (SCL). It operates as a slave MSB first, followed by a 0 to indicate a write cycle.
on the bus and the slave address is 0010000. The data After receiving ACK from the QN8075, the master sends
transfer rate on the bus is up to 400 Kbit/s. the sub-address of the register or the first of a block of
registers it wants to read. After the cycle is
SDA must be stable during the high period of SCL, acknowledged, the master terminates the cycle
except for start and stop conditions. SDA can only immediately by generating a stop condition (P).
change with SCL being low. A high-to-low transition on
SDA while SCL is high indicates a start condition. A The second phase is the data phase. In this phase, an I2C
low-to-high transition on SDA while SCL is high master initiates a read operation to the QN8075 by
indicates a stop condition. generating a start condition followed by the QN8075
slave address, MSB first, followed by a 1 to indicate a
An I2C master initiates a data transfer by generating a read cycle. After an acknowledge from the QN8075, the
start condition followed by the QN8075 slave address, I2C master receives one or more bytes of data from the
MSB first, followed by a 0 to indicate a write cycle. QN8075. The I2C master acknowledges the transfer at the
After receiving an ACK from the QN8075 (by pulling end of each byte. After the last data byte to be sent has
SDA low), the master sends the sub-address of the been transferred from the QN8075 to the master, the
register, or the first of a block of registers it wants to master generates a NACK followed by a stop.
write, followed by one or more bytes of data, MSB first.
The timing diagrams below illustrate both write and read operations.
Figure 6 I2C Serial Control Interface Protocol

Notes:
1. The default IC address is 0010000.
2. “20” for a WRITE operation, “21” for a READ operation.

5 Typical Application Schematic
VCC_3.3V
U3
1 16
10K 10K 2 GPIO1 GPIO2 15 0603
3 GND GPIO3 14 4.7uF/16V
Antenna 4 GND GND 13
RFI ARO ARO
5 12
330nH 6 GND ALO 11
1000p GND GND ALO
0603 0402 SCL 7 10
SDA 8 SCL VCC 9 4.7uF/16V
SDA XCLK 0603 VCC_3.3V
Qn8075 56p/10V
0.1uF/10V
0402
XCLK
Figure 7 Typical Application Schematic

QN8075
6 Ordering Information
Part Number Description Package

The QN8075- TCNE is Single-Chip Low-Power FM 9.9 x6 mm Body
QN8075-TCNE
receiver. [SOP16]
The QN8075- UCNE is Single-Chip Low-Power FM 4.9 x6 mm Body

QN8075-UCNE
receiver. [SSOP16]
Rev 0.1 (07/11) Copyright ©2011 by Quintic Corporation Page 14

7 Package Description
16-Lead plastic Quad Flat, No Lead Package (ML) – 9.9 x6 mm Body [SOP]
Figure 8 QN8075 SOP16 Mechanical Drawing

Carrier Tape Dimensions
Figure 9 9.9x6 SOP16 Carrier Tape
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2.
2. Camber in compliance .
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole.
4. A0 = 6.70±0.10
B0 = 10.40±0.10
K0 = 2.10±0.10

8 Solder Reflow Profile
8.1 Package Peak Reflow Temperature
QN8075 is assembled in a lead-free SOP16 and SSOP16 packages. Since the geometrical size of QN8075 is 9.9× 6 × 1.75
mm and 4.9 × 6 × 1.75 mm, the volume and thickness is in the category of volume<350 mm3 and thickness<1.6 mm in
Table 4-2 of IPC/JEDEC J-STD-020C. The peak reflow temperature is:
Tp = 260 o C
The temperature tolerance is +0oC and -5oC. Temperature is measured at the top of the package.
8.2 Classification Reflow Profiles
Profile Feature Specification*

Average Ramp-Up Rate (tsmax to tP) 3°C/second max.
Temperature Min (Tsmin) 150°C
Pre-heat: Temperature Max (Tsmax) 200°C
Time (ts) 60-180 seconds

Time Temperature (TL) 217°C
maintained
above: Time (tL) 60-150 seconds
Peak/Classification Temperature (Tp) 260°C
Time within 5°C of Actual Peak

20-40 seconds
Temperature (tp)
Ramp-Down Rate 6°C/second max.
Time 25°C to Peak Temperature 8 minutes max.
*Note: All temperatures are measured at the top of the package.

Figure 1: Reflow Temperature Profile
8.3 Maximum Reflow Times

All package reliability tests were performed and passed with a pre-condition procedure that repeat a reflow profile, which
conforms to the requirements in Section 8.2, three (3) times.


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QN8075

Single-Chip Low-Power FM Receiver for Portable Devices

__________________________ General Description __________________________

_______________________________ Key Features ___________________________

___________________________ Typical Applications ________________________

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 1

2 Electrical Specifications ..................................................................................................................................4

3 Functional Description ....................................................................................................................................9

3.1 FM Receiver ............................................................................................................................... 9

4 Control Interface Protocol .............................................................................................................................12

5 Typical Application Schematic .....................................................................................................................13

7 Package Description ......................................................................................................................................15

8 Solder Reflow Profile ....................................................................................................................................18

8.1 Package Peak Reflow Temperature .......................................................................................... 18

0.1 Draft 2011-7-14

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 2

Figure 1 QN8075 Pin Out SOP16/SSOP16

Table 1: Pin Descriptions

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 3

Table 2: Absolute Maximum Ratings

SYMBOL PARAMETER CONDITIONS MIN MAX UNIT

Vbat Supply voltage VCC to GND -0.3 5 V

VIO1 Logic signal level SCL, SDA to GND -0.3 3.6 V

Table 3: Recommended Operating Conditions

Vcc Supply voltage VCC to GND 2.7 3.3 5.0 V

RFin RF input level1 Peak input voltage 0.3 V

VIO2 Digital I/O voltage 1.6 3.6 V

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 4

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

IRX Receive mode supply current 12.8 mA

IIDLE Idle mode supply current Idle mode 660 μA

ISTBY Standby mode supply current Standby mode 58 μA

VOL Low level output voltage 0.1*VIO1 V

VIH High level input voltage 1.1 V

VIL Low level input voltage 0.3 V

SYMBOL PARAMETERS CONDITIONS MIN TYP MAX UNIT

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 5

SYMBOL PARAMETERS CONDITIONS MIN TYP MAX UNIT

De-emphasis time PETC = 1 71.3 75 78.7 μs

Audio THD after RLOAD=32Ω, 1 Vpp output 0.05

Table 7: Timing Characteristics

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 6

From power up to register

Table 8: I2C Interface Timing Characteristics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 7

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 8

Figure 3 QN8075 Functional Blocks

The QN8075 integrates FM receive functions, including

A receive signal strength indicator (RSSI) is provided

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 9

Figure 4 RSSI vs RF Input

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 10

The audio output can be muted with the MUTE_EN

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 11

Figure 6 I2C Serial Control Interface Protocol

Rev 0.2c (09/02) Copyright ©2011 by Quintic Corporation Page 12

General Description

_____ Key Features _

___ Typical Applications