Application Report

SPRA902A – July 2005

Average Current Mode Controlled Power Factor

Correction Converter using TMS320LF2407A
Shamim Choudhury ......................................... Digital Power, C2000 DSP and System Power Management

ABSTRACT

Low cost, high performance DSP controllers with integrated peripherals such as,
analog-to-digital (A/D) converters and pulse width modulator (PWM), have enabled the
power supply designers with a new tool for implementing control for their power
conversion functions. However, the power designers with mostly analog control
experience are faced with new challenges as they start to adopt this new technology
and make transition from the existing analog space to its new digital environment.
This application report identifies some of the basic differences between the two
approaches and shows a step-by-step implementation of a DSP controlled average
current mode power factor correction (PFC) converter. Different control loop par-
ameters in the analog control space are redefined prior to their digital implementation.
The loop is analyzed and the required voltage and current loop compensators are
derived. Finally, the discretization of these compensators and their implementation in
software are also presented.

Contents
1 Introduction .......................................................................................... 2
2 PFC Stage Hardware Interface to TMS320LF2407A .......................................... 3
3 PFC Stage Digital Controller Design ............................................................ 4
4 PFC Stage Digital Controller Design Example ................................................ 10
5 Experimental Results ............................................................................. 13
6 References ......................................................................................... 14

List of Figures
1 TMS320LF2407A Controlled Power Factor Correction (PFC) Stage ........................ 3
2 Control Loop Block Diagram of the DSP Controlled PFC Stage ............................. 4
3 Frequency and Average Component Calculation .............................................. 6
4 Bode Plot For Current Loop Compensation ..................................................... 9
5 Input Current and Voltage Waveforms (224Vrms) ............................................ 13
6 Input Current and Voltage Waveforms (100Vrms) ............................................ 14

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Introduction

1 Introduction
Digital Signal Processors (DSPs) designed for closed loop control implementations are extensively used in
areas of motor control, uninterruptible power supplies (UPS), and motion control applications.
With the availability of low cost, high performance DSP controllers featuring high CPU bandwidth and
integrated power electronics peripherals such as, analog-to-digital (A/D) converters, pulse width modulator
(PWM) with built-in dead-time and asynchronous power stage protection, power supply designers have
started to consider this technology as a suitable option for their real-time power conversion and control
applications.
Compared to traditional analog control, DSP controllers provide many distinctive advantages:
• standard control hardware design for multiple platforms
• less susceptibility to aging and environmental variations
• better noise immunity
• ease of implementations of sophisticated control algorithms
• flexible design modifications to meet a specific customer need
• single chip solution for both control and communication functions
The use of DSPs in power supply applications brings new challenges to many analog designers in their
effort to change the design from the existing analog space to its new digital environment.
For a DSP controlled power supply, many pertinent factors in the design and implementation of its digital
control loop need to be addressed. Redefinition of the analog control blocks and the associated
parameters in digital domain are essential for the analog designers to change the control design from the
analog hardware to its digital software counterpart. This application report discusses the different
implementation aspects of a DSP based average current mode control of a power factor correction (PFC)
stage with input voltage feed-forward. Different control loop parameters in analog domain are redefined
prior to their digital implementation. The modifications in the analog feed-forward circuits and its
implementation in software are discussed in detail. For the 16-bit fixed-point DSP(TMS320LF2407A)
based implementation, the scaling and normalization needed to implement the universal input operating
range (85Vac-265Vac, 47Hz-63Hz) is explained. The loop is analyzed in s-domain and the required
voltage and current loop compensators are derived. The discretization of these compensators and their
implementation in software are also presented.
An example design is explained to illustrate the DSP implementation of the PFC converter. Finally, test
results from a laboratory prototype are presented to validate the performance of the digital implementation.

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PFC Stage Hardware Interface to TMS320LF2407A

2 PFC Stage Hardware Interface to TMS320LF2407A

Iin L D
Vin Vo

Q
EMI C
FILTER RL
Vac

GATE
DRIVE

Rs

VCC

Verr Iref
Vref + +
Gvea Gca PWM1
−
− A Iin
Vo
ADCIN0
B

ADCIN2
C Signal
Conditioning
Calc Calc
1/Vdc^2 Vdc
ADCIN1
TMS320x2407A

Figure 1. TMS320LF2407A Controlled Power Factor Correction (PFC) Stage

Figure 1 shows a power factor correction (PFC) stage interfaced to a TMS320LF2407A DSP. This is an
ac-dc boost converter stage, which converts the ac input voltage to a high voltage dc bus and maintains
sinusoidal input current at high input power factor. As indicated in Figure 1, three signals are required to
implement the control algorithm. These are, the rectified input voltage Vin, the inductor current Iin, and the
dc bus capacitor voltage Vo. The converter is controlled by two feedback loops. The average output dc
voltage is regulated by a slow response ‘outer loop’ ;whereas, the inner loop that shapes the input current
is a much faster loop.

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PFC Stage Digital Controller Design

The instantaneous signals Vin, Vo and Iin, are all sensed and conditioned by the respective voltage and
current sense circuits. The sensed signals are then fed back to the DSP via three ADC channels ADCIN0,
ADCIN1, and ADCIN2 respectively. The rate at which these signals are sensed and converted by the ADC
is called the control loop sampling frequency fs. The digitialized sensed bus voltage Vo is compared to the
desired reference bus voltage Vref. The difference signal (Vref - Vo) is then fed into the voltage loop
controller Gvea. The digitized output of the controller Gvea, indicated as ‘B’, is multiplied by two other
components, ‘A’ and ‘C’, to generate the reference current command for the inner current loop. In
Figure 1, the component ‘A’ represents the digitized instantaneous sensed signal Vin. The component ‘C’
is calculated as,


 
 
 
where, Vdc is the calculated average component of the sensed digitized signal
Vin. In Figure 1, Iref is the reference current command for the inner current loop. Iref has the shape of a
rectified sinewave and it’s amplitude is such that it maintains the output dc voltage at a reference level
Vref, against variation in load and fluctuation in line voltage. The sensed digitized inductor current Iin is
compared with the reference current Iref. The difference between Iref and Iin is passed into the current
controller Gca. The output of this controller is finally used to generate the PWM duty ratio command for
the PFC switch.

3 PFC Stage Digital Controller Design

Iin
L +
C
Vin RL Vo
−
Kf Ks Kd

d
PWM MOD

Ks.Iin
− Uca
Gca
Kavg
A Iref B
Unv
KmABC Gvea

C Vref
TMS320LF2407A

Figure 2. Control Loop Block Diagram of the DSP Controlled PFC Stage

Figure 2 shows the control loop block diagram of the DSP controlled PFC converter shown in Figure 1. In
this figure, the voltage and current sense/conditioning circuits are replaced by their respective gain blocks.
These blocks are indicated as Kf, Ks, and Kd. The multiplier gain Km is also added to the control block.
Km allows adjustments of the reference signal Iref based on the converter input operating voltage. The
inner loop is the current loop, which is programmed by the reference current signal Iref. The input to the
current loop power stage is the duty ratio command d and it’s output is the inductor current Iin. The current
controller Gca is designed to generate the appropriate control output Uca such that the inductor current Iin
follows the reference current Iref. The outer voltage loop is programmed by the reference voltage
command Vref. The input to the voltage loop power stage is Unv (voltage controller output) and its output
is the dc bus voltage Vo. The voltage controller Gvea is designed to generate the appropriate Unv to

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PFC Stage Digital Controller Design

control the amplitude of the reference current Iref such that for the applied load current and line voltage,
the bus voltage Vo is maintained at the reference level. For this control implementation it is necessary to
calculate these voltage and current controllers. This in turn requires the identification of some of the blocks
in Figure 1, especially, when this control is implemented in software using a fixed point DSP controller
such as TMS32LF2407A.

3.1 Voltage and Current Sensing Gain

For the PFC stage shown in Figure 1, the instantaneous rectified input voltage Vin and the power factor
corrected rectified input current Iin are given by,
Vin
V m sin 2
t, 0  V m  V max , and, Iin
I m sin 2
t, 0  I m  Imax
Where, Vmax and Imax are the absolute maximum values of the peak amplitudes Vm and Im respectively.
For a DSP based PFC implementation these signals are sensed by the on-chip A/D converter, with
appropriate external conditioning circuits added to each channel, in order to bring these signals within the
range of the A/D converter. The user software reads the converted signals i.e., the digitized signals, from
the A/D converter result registers and saves them in temporary memory locations in a suitable fixed-point
format. For a fixed point DSP like TMS320LF2407A, these digitized signals are represented as numbers
with finite word length. Of the 16 available data bits of TMS320LF2407A, 15 least significant bits(LSB) are
used to represent the magnitude of the signal and the most significant bit(MSB) is used to represent its
sign. It is, therefore, necessary to select the range of the signal to be converted and then map the full
range of the converted results within the full range of the fixed-point representation. For TMS320LF2407A,
this range is 0 to 32767 for the positive going signals. Once this mapping is done correctly, the next step
is to choose a suitable fixed-point arithmetic notation for these digitized signals. For a 16-bit DSP, it is
advantageous to use Q15 notation as the fixed-point representation for these signals. With this
representation, the numbers within the range 0 to 32767, represents an absolute value between 0 to 1.
This means, with Q15 representation, the voltage and current signals are automatically saved as per-unit
(pu) numbers normalized with respect to their own maximum values.
Using this approach, the feed-forward voltage sensing circuit in Figure 2 yields,
A
VinK f  A| max
V max K f  1
V max K f
where, Vmax is the absolute maximum amplitude of the rectified input voltage Vin. Therefore, the
feed-forward voltage sensing gain Kf is defined as,
K f
1V max
In a similar manner the current sensing gain is calculated as,
K S
1I max
where, Imax is the absolute maximum amplitude of the rectified input current Iin. The dc bus voltage
sensing gain is calculated as,
K d
1V omax
where, Vomax is the absolute maximum value of the dc bus voltage. Note that, these definitions for the gain
blocks are applicable only if Q15 notation is used for the converted signals and their full range is mapped
over the full fixed-point range as explained earlier.

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PFC Stage Digital Controller Design

3.2 Software Implementation of Input Voltage Feed-forward
Input voltage feed-forward causes power input to remain constant at a specified level (determined by the
load) regardless of line voltage changes. To implement this, a voltage Vdc proportional to rms input
voltage is squared and divided into the control level. So we define the signal needed for feed-forward
implementation as,
C
1
V dc * V dc
This is the same signal mentioned before in Section 2. This is computed in software from the
measurement of the rectified input voltage signal Vin. To calculate the average component Vdc of the
rectified input Vin, it is necessary to calculate the frequency f (=1/T) of the signal and then integrate the
signal over one period. This is depicted in Figure 3.

Vthreshld_hi
Vin

Vac

Vthreshld_lo

t, t+T,
(nth sample) (n+T/Ts) th sample

Figure 3. Frequency and Average Component Calculation

3.2.1 Frequency Calculation

During the software implementation of the frequency and the subsequent average Vin calculation, the
number of samples (N) of Vin is counted and saved every time the signal crosses over a threshold level.
In Figure 3 this level is indicated as “Vthreshld_hi”. The lower threshold level “Vthreshld_lo” is used to
achieve noise immunity. This means N=T/Ts, is the number of times the signal Vin is sampled over its one
period(T) when the sampling loop frequency is fs=1/Ts. Once N is known, the per unit frequency fpu is
calculated as,
1 1
f T NTS N MIN
f PU

1

1


f max N
T MIN NMIN T S

Where, fmax is the maximum frequency of Vin and Nmin is the minimum number of samples of Vin over
one period(corresponding to it’s max frequency). The user software that calculates the frequency, uses the
value of N and first calculates an intermediate value 1/N. Then, this is multiplied by Nmin to find the pu
frequency. Now, in order to save the intermediate value 1/N with maximum accuracy without causing an
accumulator overflow, it is essential to know the value of Nmin, see Motor Speed Measurement
Considerations Using TMS320C24x DSPs (SPRA771). This means that the user should select the
maximum frequency of the signal to be measured, and based on that and the value of Ts, also determine
Nmin. Once Nmin is known, the quantity 1/N can be saved with maximum accuracy with the appropriate
fixed-point representation. For example, for a PFC converter with input operating frequency range of 47Hz
~ 63Hz, the maximum input frequency can be chosen as 70Hz. Then with fmax=140Hz (twice the input
frequency) and the value of Ts known from the sampling loop implementation, Nmin can be easily
calculated.

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PFC Stage Digital Controller Design

3.2.2 Feed-forward Component Calculation
Once the frequency of the signal Vin is known, its average component is calculated using,
t
T

Vdc  1
T
 Vin  dt
t

where, T is the time period corresponding to the frequency f of the rectified input voltage Vin. In discrete
form the average component is expressed as,
inTTs inTTs
Vdc  1
T
 Vin(i)
Ts   Vin(i)
1 
TT S
 Vin(i)
N1
in in

where, Vin(i) represents the digitized i-th sample of Vin.

Again when N is known, the integral under the Vin curve is computed by calculating the sum of the
products
 




over one period. This gives the average component Vdc of the input rectified voltage Vin. Since Vin is
measured as a per unit value normalized with respect to its maximum value Vmax, this calculated value of
Vdc is also a pu quantity with a base value of normalization of Vmax. However, for a sine-wave input
voltage the maximum value of the average component Vdc is only 2Vmax/π. Therefore, to achieve better
accuracy in the fixed-point representation of Vdc, the previously calculated value is converted to a pu
quantity normalized with respect to its own maximum value. This value is given by:

Vdc1   Vin(1)
N1
2VVmax
 ,  Vdc

2
max

Now, in calculating the inverse, Vinv, of Vdc1, i.e., Vinv=1/Vdc1, it is clear that Vinv is maximum when
Vdc1 is minimum and vice versa. Therefore, to achieve better accuracy in the fixed-point representation of
Vinv, it is necessary to represent this with a pu value normalized with respect to its own maximum value.
For a sine-wave input voltage, the minimum value of Vdc is 2Vmin/π, where, the minimum amplitude,
Vmin, of the rectified input voltage is selected based on the input operating voltage range of the PFC
converter. For example, to operate the PFC converter with a low line voltage of 90Vrms, the chosen value
of Vmin should be less than or equal to 127V. With the selected value of Vmin, the maximum value of
Vinv is (π/2Vmin) and the corresponding pu value of Vinv with respect to its own maximum value is:
1 1 V dc_MIN V
Vinv 
 1
 1
min
V dc1
V dc_MAX V inv_MAX V dc1 V dc_MAX V dc1 V max

Once Vinv is calculated with the maximum accuracy, the feed-forward component C can be calculated
with the same accuracy as,
2
C
V inv

3.3 The Multiplier Gain Km

The multiplier gain Km is adjusted such that at the minimum input voltage, the reference current Iref is at
its maximum when the PFC converter delivers the maximum load. From the block diagram in Figure 2,
2
I ref
K m ABC
K m VinK f (Unv )V inv

With the current loop closed,

I ref
IinK S  I ref MAX
I MAX K S
1

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PFC Stage Digital Controller Design

As explained in Section 3.2.2, at the minimum operating voltage Vinv =1. Again, for full load power the
voltage controller output will be at its maximum, i.e., Unv =1. Therefore, at minimum operating voltage, to
generate maximum reference current the required value of Km is,

 1
 V max
Km
I ref MAX 2


V min
 min f
V K UnvV inv

3.4 Voltage and Current Loop Compensators

High frequency approximation of the current loop power stage(1/sC = 0) is,

I in VO
G id


sL
d
From the PFC control block diagram in Figure 2, the loop gain equation for the current loop is,
T i
G id K S G CA F m
Where the modulator gain is,

Fm
d

U CA
This modulator is implemented partly in software and partly using the DSP PWM hardware. The software
uses the modulator input, i.e., the current controller output Uca, and calculates a duty ratio value for the
PWM hardware module in TMS320LF2407A. The PWM hardware uses the duty ratio value and generates
the appropriate PWM signal for the PFC switch. The software is implemented such that, when the
modulator input, Uca, is 1, the modulator output, i.e., the PWM duty ratio d, is 100%. This means, the
modulator gain in this case is Fm = 1. Therefore, for a current loop crossover frequency of fci, the required
current error amplifier compensator is,
2
f ci L
G CA

K SV O
Once the current loop is closed, the voltage loop power stage transfer function can be calculated as,
2

G VC
V O U nv


Km  
V min
2K f K S V max
Zf
VO

where, Zf represents the equivalent impedance of the parallel branch consisting of the bus capacitor C,
the PFC stage output impedance rO and the load impedance ZL, and is given by,
Zf  1
1 1
ro
ZL

sC

For a constant power load Po, the load impedance ZL and the output impedance rO are related by,

VO 2
ZL  
ro
PO
For resistive load RL, the load impedance ZL and the output impedance rO are related by,
VO
ZL
RL

ro
IO

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PFC Stage Digital Controller Design

From the block diagram in Figure 2, the loop gain equation for the voltage loop is,
T V
K d G VEAGVC
Using this loop gain equation, for a voltage loop crossover frequency of fcv, the required voltage error
amplifier compensator is,
2

G VEA
 
2K f K S V max
K d K m V min
VO
Zf | f
fcv

3.5 Software Implementation of the Voltage and Current Loop Compensators

The voltage and current loop controllers, given in previous section, are transformed to an equivalent digital
form as explained below, before they are implemented in software using TMS320LF2407A. For example,
the current controller can be written as,
  



 


   
    
  

 



Where, Kp is the magnitude of the current compensator calculated in Section 3.4 and E is the current
error signal.
The location of the compensator zero, ωz =2πfz= 1/TI, is usually chosen somewhere below the crossover
frequency fci to maintain adequate phase margin. The current loop compensator design is illustrated
graphically by the current loop bode plot shown in Figure 4. The top trace in Figure 4 represents the gain
plot for all the control blocks in the current loop, i.e, Gid, Fm and Ks, except the current compensator Gca.
The gain plot for the compensator Gca, shown in the middle trace in Figure 4, is derived to achieve the
desired loop gain Ti shown in the bottom trace. In Figure 4 the power stage has a –1 slope. Therefore,
placing the compensator zero fz, at the desired crossover frequency of fci, results in a phase margin of 45
deg. However, in a digital implementation some of this phase margin can be lost because of the control
loop sampling and computation delay. To compensate for this loss, it might be necessary to place the
compensator zero somewhere below the crossover frequency as indicated in Figure 4.

| Gid.Fm.Ks |

fci −1
0
| Gca | f
0 fz
Kp f
−1

| Ti |

−2
0
−1 f
fo fci

Figure 4. Bode Plot For Current Loop Compensation

In discrete form, the current controller mentioned before, can be expressed as,
n
U CA(n )  K P E( n )
K IT S  E( j )
jO

where, Ts is loop sampling time. This is implemented with output saturation and integral component
correction using the following three equations:

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PFC Stage Digital Controller Design Example

U CA(n)  K0 * E(n)
I(n  1),
I(n)  I(n  1)
K1 * E(n)
Kcorr * Epi
Epi  Us  U CA(n)
where,
Us
U CAmax when U CA(n )  U CAmax
Us
U CAmin when U CA(n )  U CAmin
otherwise,
Us
U CA (n )
Here, Us represents the final output of the current controller with saturation and integral component
correction. The coefficients in the last three equations, representing the discrete form of the analog current
compensator, are defined as,
K0
K P , K1
K IT S , K CORR
K1K0
These equations can be easily implemented in software using TMS320LF2407A.

4 PFC Stage Digital Controller Design Example

The system parameters used in this design are:

Output power Po=825 W,

DC bus voltage Vo =380V,
Switching frequency fsw=120kHz;
Digital loop sampling frequency fs = 60kHz
L=100uH, C=390uF,
Volt loop bandwidth fcv=10Hz, Current loop bandwidth fci=8kHz,
Maximum frequency of rectified input voltage fmax=200Hz
Vmax=410V, Vmin=109.95V, Vomax=410V

To deliver the maximum output power at the minimum input voltage, the maximum value of the input
current (neglecting the losses in the PFC converter) is, Imax=2Po/Vmin = 15A Different gain parameters
are calculated as,
Kf = 1/410, Kd = 1/410, Ks = 1/15, Km = 410/109.95 = 3.7286

4.1 Current Controller Implementation Example

For fci = 8kHz, the magnitude of the current controller is, GCA = 0.1985 Set current loop PI compensator
zero at 800Hz. So, the integral time constant for the current compensator is, TIC = 1/(2π.800) =
198.94x10-6 Therefore, the complete current loop controller is,
G CA(s )  0.1985
1  198.94
10
6s
198.94
10 s
6

K U (s)
 GCA( s )  K Pi  sIi  i
Ei (s )
where, KPi = 0.1985 and KIi = 997.77
The discrete controller is implemented using the following equations,
Ui(n )  K0i * Ei(n )
Ii( n  1 ),
Ii(n )  Ii(n  1 )
K1i * Ei( n )
Kcorri * Epii
Epii  Usi  Ui(n )
where,

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PFC Stage Digital Controller Design Example

Usi
Ui max when Ui(n )  Ui max

Usi
Ui min when Ui(n )  Ui min
otherwise,
Usi
Ui(n )
The coefficients for the discrete current controller are,
K0i
K Pi
0.1985
6504(Q15 )
K1i
K Ii T S
0.016629
545(Q15 )

Kcorri
K1i
0.08376
2745(Q15)

K0i
where, TS = 16.667x 10-6 sec.
The code segment that implements the above controller is given below:

PFC_I_CONTROL_INIT:
;PFC current control loop initialization
LDP # K0i
SPLK #6504,K0i ;Q15
SPLK #545,K1i ;Q15
SPLK #2745,Kcorri ;Q15
RET
PFC_I_CONTROL:
;PFC current control loop using feed-forward technique
SETC SXM
SETC OVM
spm #0
LDP #Iref
LACC Iref ;Q15
SUB Ipfc ;Q15
SACL En0i ;Q15
LACC Uni,15 ;Q30,32-bit
LT En0i ;Q15
MPY K0i ;Q15*Q15
APAC ;Q30
SACH GPR0_pfc
ADDH GPR0_pfc ;Q31
SACH Upii ;Q15
SACH Usi ;Q15
UiMAX .set 7ffeh
UiMIN .set 0
LACC Upii
BCND SAT_UiMIN, LT ;
LACC Upii
SUB #UiMAX
BCND SAT_UiMAX, GEQ ;
B FWD_i
SAT_UiMIN SPLK #UiMIN,Usi
B FWD_i
SAT_UiMAX SPLK #UiMAX,Usi
FWD_i: LACC Usi ;Q15
SUB Upii ;Q15
SACL Epii ;Q15
LT Epii ;Q15
MPY Kcorri ;Q15
LTP En0i ;Q15
MPY K1i ;Q15
APAC ;Q30
ADD Uni,15
SACH GPR0_pfc
ADDH GPR0_pfc ; Q31

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PFC Stage Digital Controller Design Example

SACH Uni ;Q15, Controller final output
RET

4.2 Voltage Controller Implementation Example

For constant power load, ZL = -175.03. For fcv = 10Hz, the magnitude of the voltage controller is, GVEA =
4.63. Set the volt loop PI compensator zero at 10Hz. Then the integral time constant is, TIV = 1/(2π.10) =
15.9155x10-3. Therefore, the complete voltage loop controller is,
Gvea(s )  4.7517
1  15.9155
10
3s
15.9155
10 s
3

K Uv(s )
 Gvea(s)  K Pv  sIv 
Ev(s)
where, KPV = 4.63 and KIV = 290.91
The discrete controller is implemented using the following equations,
Uv(n )  K0v * Ev(n )
Iv( n  1 ),
Ivi(n )  Iv(n  1 )
K1v * Ev( n )
Kcorrv * Epiv
Epiv  Usv  Uv(n )
where,
Usv
Uv max when Uv(n )  Uv max
Usv
Uv min when Uv(n )  Uv min
otherwise,
Usv
Uv(n )
The coefficients for the discrete voltage controller are,
K0v
K Pv
4.7517
19463(Q12 )
K1v
K Iv T S
0.004976
163(Q15 )

Kcorrv
K1v
0.001047
34(Q15)

K0v
where, TS = 16.667x 10-6 sec.
The code segment that implements the above controller can be written in the same way as shown in
Section 4.1.

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Experimental Results

5 Experimental Results

Figure 5. Input Current and Voltage Waveforms (224Vrms)

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References

Figure 6. Input Current and Voltage Waveforms (100Vrms)

Figure 5 shows the input current (5A/div) and input voltage (224Vrms) waveforms of the PFC converter.
Figure 6 shows the same waveforms for the same output load, but at a different input voltage (100Vrms).
In this case, the PFC stage is used to drive a dc/dc stage, which delivers 48V output at 10A of load
current.

6 References
1. L.H. Dixon, “Average Current Mode Control of Switching Power Supplies”, Unitrode Power Supply
Design Seminar Manual SEM700, 1990
2. R.B. Ridley, “Average small-signal analysis of the boost power factor correction circuit”, Proceedings of
the Virginia Power Electronics Center Seminar (VPEC), Blacksburg, VA, Sept., 1989.
3. Motor Speed Measurement Considerations when Using TMS320C24x/24xx (SPRA771).

14 Average Current Mode Controlled Power Factor SPRA902A – July 2005

Correction Converter using TMS320LF2407A
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