9/18/2013
Dr. Zhonghai Lu ()
School for ICT
KTH Royal Institute of Technology
C++ Basics
SystemC
Introduction
and Get
Started
Modules
and
Processes
Concurrency
and Time
Channels
and
Interfaces
Transaction
Level
Modeling
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
SystemC
Data Types
and
Debugging
SystemC
Summary
9/18/2013
IL2452 System Design Languages
Aim
Understand SystemC data types and master how
to use them
Content
Overview of SystemC data types
Integer and vector types
Type conversion
Resolved signals (bus resolution)
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
9/18/2013
SystemC
Native C/C++ Types
SystemC Types: Data types oriented for hardware
modeling
SystemC
supports
Types
2 value (0,1) logic/logic vector
4 value (0,1,Z,X) logic/logic vector
Arbitrary sized integer (Signed/Unsigned)
Fixed Point types (Templated/Untemplated)
Using
namespace sc_dt
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IL2452 System Design Languages
sc_fix is the base class for sc_fixed. The size of an object of type
sc_fix is set when the object is created (i.e. by the constructor)
as opposed to sc_fixed where the size is set by the compiler
(using the template parameter).
Type
Description
sc_int<>
Signed Integer from 1-64 bits: sc_int<n>
Integer types
sc_uint<>
Unsigned Integer from 1-64 bits
sc_bigint<>
Arbitrary size signed integer: sc_bigint<n>
sc_biguint<>
Arbitrary size unsigned integer
Logic and Vector types
sc_logic
Simple bit with 4 values(0/1/X/Z)
sc_bv<>
Arbitrary size 2-values vector: sc_bv<n>
sc_lv<>
Arbitrary size 4-values vector
sc_fixed<>
templated signed fixed point
sc_ufixed<>
templated unsigned fixed point
sc_fix
untemplated signed fixed point
sc_ufix
untemplated unsigned fixed point
Fixed point types
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
9/18/2013
Four integer types: signed, unsigned, limited
width and big width.
sc_int<n>, sc_uint<n>
n 64
Regardless of the bit width n given by the template
parameter, internally stored with 64 bits of precision
sc_bigint<n>, sc_biguint<n>
No max. for n (unbounded)
Internally stored with as many as necessary to hold the
result
All integers are stored as binary numbers. Signed
numbers are stored in twos complement format.
sc_int<n>,
sc_lv<n>, sc_bv<n>
IL2452 System Design Languages
Operators
Overloaded operators: bitwise, arithmetic, assignment,
equality, relationship
Special operators like HDL: bit select, part select, and
concatenation
int
Bitwise operators (&(and), |(or), ^(xor), ~(not), <<, >> )
Arithmetic operators ( +, -, *, /, %(modulo) )
Assignment (=) and compound assignment (+=, -=, *=, /=, %=,
>>=, <<=, &=, ^=, |=)
Equality operators (==, !=)
Relationship operators (>, <, >=, <=)
in C++
The size depends on the machine
Faster in the simulation
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
9/18/2013
Assignment to any of the integer types causes
the value to be truncated to the given number of
bits without warning.
sc_uint<4> a, b, c;
sc_uint<8> d;
a = b = 15;
c = a + b;
d = a + b;
sc_uint<4>
sc_int<>
c=14
sc_int<4>
Truncation!
d=30
Precision of intermediate results determined
only by the operands.
problematic
sc_uint<64> j = 0x7fff ffff ffff ffff;
sc_biguint<128> k;
Truncated to 64 bits.
k = j * j;
k = sc_biguint<64> (j) * j;
stored with arbitrary precision
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IL2452 System Design Languages
Give an example of implicit
type conversion, which a
user expects to occur?
Due
to implicit type conversion,
it allows to mix the SystemC integer types sc_int
and sc_uint with C++ fundamental types int.
Any two SystemC types can be converted by
assignment operator =, which is overloaded.
Signed/unsigned conversion loses sign without
warning.
sc_int<16> a, b;
int d;
sc_int<8> a;
sc_bigint<64> B;
sc_int<8> s;
sc_uint<8> u;
d = a & b;
a = b + d;
B = a;
a = B;
s = -1;
u = s;
s = u;
Cannot add an sc_int to
an sc_logic.
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
u = 255
s = -1
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sc_logic
is a 4-valued data type, similar to
VHDL type std_logic
Bitwise
&
Assignment
&=
!=
^=
4 values: 0, 1, X, Z
Equality
==
Initial value is X
Similar to std_logic in VHDL.
Slower than bool
!=
sc_logic a, b;
a = 1;
b = Z;
b = a & b;
Vectors
sc_lv<n> arbitrary length vector of sc_logic
sc_bv<n> arbitrary length vector of bool
Used for vectors longer than 64 bits where no need
arithmetic operators (shift <<, >> is Ok).
Faster than sc_biguint<>
For vectors of 64 bits or less, sc_uint<> is faster and
more convenient.
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IL2452 System Design Languages
Concatenation means composing two or more vectors endto-end to create a single longer vector.
Two ways of concatenation
Overloaded comma operator
Function concat()
A concatenation can be used as an l-value, i.e., on the left
hand side of an assignment.
sc_uint<4> a, b, d, e;
sc_unit<8> c;
c = (a, b);
(d, e) = c;
1100
1101
11001101
c
(a, b, c) = (c, b, a);
concat(a, concat(b,c)) = concat(concat(c,b), a);
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Languages Lecture 5
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To support bit select, the index operator [] is overloaded.
To support part select, use the method range() for sc_int,
sc_uint, sc_lv<>, sc_bv<> with 2 arguments.
For sc_int, sc_uint, the 1st argument the 2nd argument.
For sc_lv<>, sc_bv<>, if the first argument is less than the second, the
bits are read out of the vector in the reverse order.
Range() can be abbreviated by calling the overloaded operator()(int, int).
sc_int<8> a;
bool b;
a.range(7,4) = a.range(3,0);
sc_lv<4> v = ZX10;
cout << v.range(0,3);
b = a[7]
a[6] = b;
bit reversal, 01XZ
a(7, 4) = a(3, 0);
v = (v(1,0), v(3,2));
cout << v.range(0,3);
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IL2452 System Design Languages
Numbers can be written as
strings by prefixing the
string literal with the
number base.
0b for binary, 0d
decimal, 0x(0X)
hexadecimal
For sc_bv<> an sc_lv<>,
strings are interpreted as
binary by default.
A raw string without a
prefix assigned to a
sc_int<> is interpreted as
decimal.
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
10ZX
sc_lv<4> lv;
sc_bv<4> bv = lv;
sc_int<4> si = lv;
X Z cause warning
or run time error.
lv = 01XZ; //raw string to sc_lv
bv = 0101; //raw string to sc_bv
si = 1011; //raw string to sc_int, decimal !
si = 0b1011 //binary number
si = 0d9; //decimal number
lv = 0xf; //hexadecimal number
lv = 0xf; //hexadecimal number
lv = 00xx0
What if I want to use
0x as logic values for
the two bits?
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9/18/2013
Two SystemC data types can be
converted by assignment
(implicit type conversion). This
does not hold for converting to
C++ types.
To convert from sc_bv<>,
sc_lv<> to int, need explicit
type conversion to_int().
Function to_string() convert to
a formatted text string.
The 1st argument gives the
representation
The 2nd argument indicates
whether to include a prefix
showing the number base.
sc_lv<8> lv = 0xff;
sc_bv<8> bv = 0xff;
sc_bigint<96> si = 0xff;
int i;
i = lv.to_int( ); // return -1
i = bv.to_uint( ); //return 255
i = bi.to_long(); //return 255
cout << bv.to_string(SC_DEC);
//return 0d255
cout << bv.to_string(SC_HEX);
//return 0x0ff
cout << bv.to_string(SC_BIN);
//0b11111111
cout << bv.to_string(SC_BIN, false);
//0b11111111
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IL2452 System Design Languages
To
pass the value 0
or 1 to the write()
method,
Explicitly cast the
literal to type
sc_logic.
Use built-in
constants,
SC_LOGIC_0,
SC_LOGIC_1
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
SC_CTOR(Driver){
SC_THREAD(p1);
SC_THREAD(p2);
}
sc_signal<sc_logic> s;
void p1( ){
s.write(sc_logic(0));
//s = sc_logic(0);
}
void p2( ){
s.write(SC_LOGIC_0);
//s = SC_LOGIC_0;
}
}
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sc_fix var_1( 16, 4, SC_RND, SC_SAT);
sc_fix var_2( 16, 4, SC_RND, SC_SAT);
sc_fix var_3( 16, 4, SC_RND, SC_SAT);
var_1 = 0.5;
var_2 = 1.125;
var_3 = 0.7;
Due
to their compile-time overhead, fixedpoint types are omitted from the default
SystemC include file.
To enable fixed-point types, SC_INCLUDE_FX
must be defined prior to including the
#define SC_INCLUDE_FX
SystemC header file.
#include systemc.h
sc_fixed<5, 3>
}
Integer word length
Word length
value in [- 4, 3.75], precision 0.25
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IL2452 System Design Languages
To model bus contention
(multiple drivers on a tristate bus wire), use a
different data type
sc_signal_resolved (not
sc_signal).
When multiple processes
write to an instance of the
sc_signal_resolved, the
values are resolved
according to a resolution
table.
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
SC_CTOR(Driver){
SC_THREAD(p1);
SC_THREAD(p2);
}
sc_signal_resolved s;
void p1( ){
s.write(sc_logic(0));}
void p2( ){
s.write(SC_LOGIC_1);
wait(10, SC_NS);
s.write(SC_LOGIC_Z);}
}
Resolved
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sc_signal_resolved
is a specialized channel of
sc_signal<> for type sc_logic
class sc_signal_resolved : public sc_signal<sc_logic> { }
sc_signal_rv<>
is a vector version of this
channel.
template<int W>
class sc_signal_rv : public sc_signal< sc_lv<W> > { }
There
are specialized ports, but they can
only be bound to resolved signals.
sc_in< >
sc_inout< >
sc_out< >
IL2452 System Design Languages
sc_in_resolved
sc_inout_resolved
sc_out_resolved
sc_in_rv< >
sc_inout_rv< >
sc_out_rv< >
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What
if a user-defined data type passed over
using sc_signal<T>?
Must define a default constructor
Must overload operators =, ==, << and function
sc_trace().
sc_signal<packet> sp;
class packet {
public:
packet();
const char* text() const {return data;}
const packet& operator= (const packet& pkt);
bool operator== (const packet& pkt);
friend ostream& operator<< (ostream& os, const packet& pkt);
friend void sc_trace(sc_trace_file *f, const packet& pkt, const std::string& name)
private:
..
};
IL2452 System Design Languages
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Languages Lecture 5
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Overview of SystemC data types: integer, vector, fixed
point types
Integer types
Note their differences with int
sc_int, sc_lv, sc_bv
Type conversion
Implicit conversion
Use explicit type cast
Resolved signals (bus resolution)
sc_signal_resolved and sc_signal_rv<>
Need specialized ports to connect to resolved channels
User defined type passed over sc_signal<T>
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Try
the type conversion, assignment and
truncation, bit/part select examples.
Try the signal resolution example.
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Languages Lecture 5
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www.systemc.org
www.doulos.com
SystemC:
From the Ground Up by D. C. Black,
J. Donovan, B. Bunton, and A. Keist.
System Design with SystemC by T. Grtker, S.
Liao, G. Martin, and S. Swan
Others
IL2452 System Design Languages
KTH IL2452 System Design
Languages Lecture 5
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