11/1/2010

Microsequencer Control Unit

Design
Chapter 7 – John D. Carpinelli

Chapter Outline
• Basic Microsequencer Design
• Very Simple Microsequencer
• Relatively Simple Microsequencer
• Reducing the Number of
Microinstructions
• Microcoded vs. Hardwired Control
• Pentium Microprocessor

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Micro--stuff
Micro
‘Registers and data paths are the
same as before’

• Micro
Micro--operations (register transfers)

• Microinstructions ((μ
μ-operations +
sequencing information)

• Microprogram (collection of all

microinstructions for a processor)

Generic Microsequencer

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Generating the Next Address

Possible next addresses:
• Current Address + 1(sequential
( q states))
• Address specified by microinstruction
(jump after every execute routine)
• Mapping hardware (to jump to correct
execute routine after fetch)
• Microsubroutine
Mi b ti register
i t (t(to iimplement
l ta
common routine for several instructions)

Microinstruction Format

SELECT: Indicates the source of the next address 
(absolute or a derived address)
p
ADDR: Specifies an absolute address
μ‐OPERATIONS: lists the μ‐OPS to be carried out

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Micro--operations for VS CPU

Micro
“AR” ARÅ
AR ÅPC; ARÅ
ARÅDR[5..0]
[ ]
“PC” PCÅPC + 1; PCÅ
PCÅ PCÅDR[5..0]
“DR” DRÅM
DRÅ
“IR” IRÅDR[7..6]
IRÅ
“AC” ACÅAC + DR;; ACÅ
ACÅ ACÅAC^DR;; ACÅ
ACÅAC
+1

Types of Microcode
• Horizontal (a bit is allocated in the
microinstruction for each μ-OP of the
processor) – could be long
long, only one/a
few are used at a time, 16 μ-Ops =>
• Vertical ((μ-Ops are grouped and
assigned a code) 16 μ-Ops =>
H & V need control signals to be derived
from μ-Ops
• Direct
Di t ((stores
t the
th control
t l signals,
i l suchh
as -ld, inc,.. in memory-
memory- and directly
generates them)

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Very Simple CPU Specification

FETCH1: AR ← PC
FETCH2: DR ← M,
M PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
ADD1: DR ← M
ADD2: AC ← AC + DR
AND1: DR ← M
AND2: AC ← AC ^ DR
JMP1: PC ← DR[5..0]
INC1: AC ← AC + 1

Very Simple CPU State Diagram

‘To  
sequence 
through 
g
these states 
and to 
generate the 
μ‐ops
For that 
state’

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A Very Simple Microsequencer

Size of micro 
code memory?
code memory?
Register?
Mux. In/out?

State Assignments

Instruction First State IR Counter Value

ADD ADD1 00 1000 (8)

AND AND1 01 1010 (10)

JMP JMP1 10 1100 (12)

INC INC1 11 1110 (14)

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Mapping Logic

State Addresses
State Address
FETCH1 0000 (0)
FETCH2 0001 (1)
FETCH3 0010 (2)
ADD1 1000 (8)
ADD2 1001 (9)
AND1 1010 (10)
AND2 1011 (11)
JMP1 1100 (12)
INC1 1110 (14)

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Partial Microcode (sequencing)

microinstruction
State Address SEL NXT. ADDR
FETCH1 0000 (0) 0 0001
FETCH2 0001 (1) 0 0010
FETCH3 0010 (2) 1 XXXX
ADD1 1000 (8) 0 1001
ADD2 1001 (9) 0 0000
AND1 1010 (10) 0 1011
AND2 1011 (11) 0 0000
JMP1 1100 (12) 0 0000
INC1 1110 (14) 0 0000

Very Simple CPU Specification

FETCH1: AR ← PC
FETCH2: DR ← M,
M PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
ADD1: DR ← M
ADD2: AC ← AC + DR
AND1: DR ← M
AND2: AC ← AC ^ DR
JMP1: PC ← DR[5..0]
INC1: AC ← AC + 1

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Micro--operations
Micro
Mnemonic Micro-
Micro-Operation
ARPC ARÅ
AR ÅPC
ARDR ARÅ
AR ÅDR[5..0]
PCIN PCÅ
PC ÅPC + 1
PCDR PCÅ
PC ÅDR[5..0]
DRM DRÅ
DRÅM
IRDR IRÅ
IRÅDR[7..6]
PLUS ACÅ
AC ÅAC + DR
AND ACÅ
AC ÅAC^DR
ACIN ACÅ
AC ÅAC + 1

Preliminary Horizontal Microcode

‘μ‐ops field’ in micro instruction accommodates all μ‐ops

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Optimized Horizontal Microcode

ARDR and IRDR has the same value in all states ‐ combine

Control Signals
‘Derived from the RTL code of all the states’

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Control Signals

Regroup
g p operations
p by
y destination

“AR” ARÅ
AR ÅPC; ARÅ
ARÅDR[5..0]
“PC” PCÅPC + 1; PCÅ
PCÅ PCÅDR[5..0]
“DR” DRÅM
DRÅ
“IR” IRÅDR[7..6]
IRÅ
“AC” ACÅAC + DR; ACÅ
ACÅ ACÅAC^DR; ACÅ
ACÅAC + 1

Control Signals
Savings in logic: 
DRLOAD,
MEMBUS

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Generic Vertical Microcode

Decoding
‘Lots of zeros
in horizontal
μcode - most
are inactive’
Grouped into
fi ld no more
fields:
than one μ-op
in a field is
active in a
state

Field Assignment Guidelines

‘Other part of the design remains the
same’

• Simultaneous micro-
micro-operations in
different fields

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Field Assignment Guidelines

• Simultaneous micro-
micro-operations in
different fields
• Include a NOP in each field

Field Assignment Guidelines

• Simultaneous micro-
micro-operations in
different fields
• Include a NOP in each field
• Group together micro-
micro-operations that
modify
od y the e same
sa e register
eg s e

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Field Assignment Guidelines

• Simultaneous micro-
micro-operations in
different fields
• Include a NOP in each field
• Group together micro-
micro-operations that
modify
od y the e same
sa e register
eg s e
• Distribute remaining micro-
micro-operations to
minimize total number of bits required

Very Simple CPU

Specification
FETCH1: AR ← PC
FETCH2 DR ← M,
FETCH2: M PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
ADD1: DR ← M
ADD2: AC ← AC + DR
AND1: DR ← M
AND2: AC ← AC ^ DR
JMP1: PC ← DR[5..0]
INC1: AC ← AC + 1

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Micro--operations
Micro
Mnemonic Micro-
Micro-Operation
ARPC ARÅ
AR ÅPC
AIDR ARÅ
AR ÅDR[5..0]
PCIN PCÅ
PC ÅPC + 1
PCDR PCÅ
PC ÅDR[5..0]
DRM DRÅ
DR ÅM
PLUS ACÅ
AC ÅAC + DR
AND ACÅ
AC ÅAC^DR
ACIN ACÅ
AC ÅAC + 1

Micro--operation Assignments
Micro

M1 M2
NOP NOP
DRM PCIN

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Micro--operation Assignments
Micro
M1 M2
NOP NOP
DRM PCIN
ACIN PCDR
PLUS ARPC
AND AIDR
(Data related) (Address related)

Micro--operation Assignments
Micro

M1 M2
NOP NOP
DRM PCIN
ACIN PCDR
PLUS ARPC
AND
AIDR

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Micro--operation Assignments
Micro
and Field Values

Vertical Microcode

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Micro--operation Generation
Micro

Nanoinstructions
128 μ-instructions with 32 μ-
operations need 128*32bits.
16 unique combinations: nano-
memory 16*32,
Access these 16 locations
using 4-bits.
Microcode memory is then
128*4

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Directly Generating Control

Signals
• Output control signals instead of micro
micro--
operations
• No external decoding required
• No external hardware required to
generate
ge e a e co
control
o ssignals
g as
• More difficult to code

Final Register Section

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Very Simple CPU

Specification
FETCH1: AR ← PC
FETCH2 DR ← M,
FETCH2: M PC ← PC + 1
FETCH3: IR ← DR[7..6], AR ← DR[5..0]
ADD1: DR ← M
ADD2: AC ← AC + DR
AND1: DR ← M
AND2: AC ← AC ^ DR
JMP1: PC ← DR[5..0]
INC1: AC ← AC + 1

Preliminary Direct Microcode

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Optimize Direct Microcode

DRLOAD, MEMBUS, READ have same values- combine

Relatively Simple
Microsequencer
• No changes to
– Instruction set
– Data paths
– ALU

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Modified State Diagram

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State Assignments
Mapping:IR
[
[3..0]00
]

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Microsequencer Hardware
Three sources of
next address
->
> larger mux
mux.,
To support
conditional jump,
‘+1’ circuit is
necessary
Error in figure?

Condition Values
Condition

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Branch Types

Branch Logic

Expressions for S1 and S0 of top MUX?

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Partial Microcode (Sequencing)

Partial Microcode (continued)

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Micro--operations
Micro
‘22-bits for them’

Horizontal Microcode

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Horizontal Microcode

Horizontal Microcode

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Control Signals

Reducing the Number of

Microinstructions
‘Sharing
Sharing common operations’
operations
• Microsubroutines
• Microcode Jumps

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Microsubroutines

Revised State Assignments

SUB1, SUB2,
SUB3 does same
as LDAC1,
LDAC1
LDAC2, LDAC3

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Microsequencer with
Microsubroutines

Revised Branch Types

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Revised Branch Logic

Revised Microcode

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Microcode Jumps
‘Sharing states under certain condition’

Revised Microcode

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Microprogrammed Control vs.

Hardwired Control
• Complexity of the instruction set
- more instructions implies more states,
means more complex logic to generate
control signals in HW control unit
- as long as the micro-
micro-operations are
the same, increasing state implies more
memory locations
l i b
but no iincrease iin
logic to generate control signals in
MS/MP control unit

Control Signals
‘Derived from the RTL code of all the
states’

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Microprogrammed Control vs.

Hardwired Control
• Complexity of the instruction set
• Ease of modification
- generally it is easier to add
instructions, that is states in MS/MP
control
co o u
units
s than
a HW co control
o u
units.
s This
s
implies expandability for MS/MP control
unit.

Microprogrammed Control vs.

Hardwired Control
• Complexity of the instruction set
• Ease of modification
• Clock speed
- as HW control unit is built from
combinatorial circuits
circuits, generally the
instruction execution is faster. MP/MS
control unit involves access delay for
the Look
Look--up ROM.

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The Pentium Microprocessor

Summary
• Basic Microsequencer Design
• Very Simple Microsequencer
• Relatively Simple Microsequencer
• Reducing the Number of
Microinstructions
• Microcoded vs. Hardwired Control
• Pentium Microprocessor

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Current Address Op-code Conditions Absolute Next Address

Next Address Generation

Address Register

Microcode Memory (Micro-

operations and Next
Address)

Partial Product 0 Partial Product 1 Partial Product 2

5-bit Carry Save Adder

Carry Sum

6-bit Binary Parallel Adder

Final Product

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Data
Read Mask Register
Write

Data Register

Match
Memory Register

Output Register

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