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Design of I2C Protocol in VHDL PDF

This instructable discusses designing a simple I2C master in VHDL. It provides an overview of the I2C bus protocol, describes the RTL design using a finite state machine for optimal performance, and details simulation and testing of the design using a third-party I2C slave IP on an FPGA board. Important notes are provided on testing considerations such as pull-up resistors and bidirectional signal behavior. Attached files include the RTL code, test bench, slave code, and documentation.

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437 views3 pages

Design of I2C Protocol in VHDL PDF

This instructable discusses designing a simple I2C master in VHDL. It provides an overview of the I2C bus protocol, describes the RTL design using a finite state machine for optimal performance, and details simulation and testing of the design using a third-party I2C slave IP on an FPGA board. Important notes are provided on testing considerations such as pull-up resistors and bidirectional signal behavior. Attached files include the RTL code, test bench, slave code, and documentation.

Uploaded by

Likourgos Leisos
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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instructables

Design of I2C Master in VHDL

by AmCoder

In this instructable, Designing a simple I2C master in VHDL is discussed.

NOTE: click on each image to see full image.

Step 1: I2C Bus Overview

•Stands for Inter Integrated Circuit.

•Synchronous , Half duplex.

•Two Wire Interface - SDA and SCL.

•SDA – Serial Data line controlled by Master and Slave

•SCL – Serial Clock generated by Master

•Multi-master , Multi-slave protocol.

•Two modes - 100 kbits/sec and 400 kbits/sec : slow and fast.

Design of I2C Master in VHDL: Page 1


Step 2: RTL Design in VHDL

Design Specs of our I2C Master

8-bit data frame.


SCL uni-directional control only.
7-bit slave address.
Supports both slow and fast modes.
Single Master, Multi-slave.
Complied with original I2C specs by Philips.

Pure RTL code is used. So the IP is easily portable across all FPGAs. Compact FSM based design using
internally generated clock ensures optimal area and performance.

Step 3: Simulation and Testing

Test Environment

Functional simulation and testing using third-party I2C Slave IP.


Synthesised using Xilinx Vivado tool set.
Implemented and tested on Artix-7 FPGA board.
Timing verified design for 100 MHz.
Tested waveforms on DSO/CRO.
Successfully tested communication with Arduino UNO as I2C Slave.

Step 4: Important Notes

While testing Master using I2C Slave IP, configure the slave code as per your requirements. You
may want to change the default clock frequency and slave address. Clock frequency should be
configured in the Master code too.
While on-board testing, don't forget pull-up resistors as SDA line is common drain output !!! Check
google for recommended pull-up resistor for different i2c speeds. I used 2.2K for 100 kHz.
If not using test bench and simulating the Master independently, carefully simulate SDA signal, as it
is a bi-directional signal (inout) signal. It has two drivers, master side and slave side. You should
know when to 'force' and when to 'unforce'.
SCL is unidirectional line. No need of pull-up.
Please go thru the IP Documentation thoroughly.

Design of I2C Master in VHDL: Page 2


Step 5: Files Attached

All RTL codes of I2C Master.


Test bench, I2C Slave codes as well, for testing.
IP Documentation.

for queries contact --

iammituraj@gmail.com

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Design of I2C Master in VHDL: Page 3

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