I/O (32) 34V16 Pal Central Switch Matrix: 2.2.2 Advanced Micro Devices (Amd) Cplds
I/O (32) 34V16 Pal Central Switch Matrix: 2.2.2 Advanced Micro Devices (Amd) Cplds
I/O (32) 34V16 Pal Central Switch Matrix: 2.2.2 Advanced Micro Devices (Amd) Cplds
I/O (32)
I/O (32)
AMD offers a CPLD family with five sub-families called Mach 1 to Mach 5. Each Mach device
comprises multiple PAL-like blocks: Mach 1 and 2 consist of optimized 22V16 PALs, and Mach 3
and 4 comprise several optimized 34V16 PALs, and Mach 5 is similar but offers enhanced speed-
performance. All Mach chips are based on EEPROM technology, and together the five sub-fami-
lies provide a wide range of selection, from small, inexpensive chips to larger state-of-the-art
ones. This discussion will focus on Mach 4, because it represents the most advanced currently
Figure 11 depicts a Mach 4 chip, showing the multiple 34V16 PAL-like blocks, and the inter-
connect, called Central Switch Matrix, for connecting the blocks together. Chips range in size
from 6 to 16 PAL blocks, which corresponds roughly to 2000 to 5000 equivalent gates and are in-
circuit programmable. All connections in Mach 4 between one PAL block and another (even from
a PAL block to itself) are routed through the Central Switch Matrix. The device can thus be
Page 18 of 41