Commercial/

Industrial

PEEL™ 18CV8 -5/-7/-10/-15/-25

CMOS Programmable Electrically Erasable Logic Device
Features
■ Multiple Speed Power, Temperature Options ■ Architectural Flexibility
- VCC = 5 Volts ±10% - Enhanced architecture fits in more logic
- Speeds ranging from 5ns to 25 ns - 74 product terms x 36 input AND array
- Power as low as 37mA at 25MHz - 10 inputs and 8 I/O pins
- Commercial and industrial versions available - 12 possible macrocell configurations
- Asynchronous clear
■ CMOS Electrically Erasable Technology - Independent output enables
- Superior factory testing -- 20 Pin DIP/SOIC/TSSOP and PLCC
- Reprogrammable in plastic package
- Reduces retrofit and development costs
■ Application Versatility
■ Development / Programmer Support - Replaces random logic
- Third party software and programmers - Super sets PLDs (PAL, GAL, EPLD)
- ICT PLACE Development Software and PDS-3 - Enhanced Architecture fits more logic than ordinary
programmer PLDs
- PLD-to-PEEL™ JEDEC file translator
General Description
The PEEL™18CV8 is a Programmable Electrically Eras- The PEEL™18CV8 architecture allows it to replace over 20
able Logic (PEEL™) device providing an attractive alterna- standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
tive to ordinary PLDs. The PEEL™18CV8 offers the vides additional architecture features so more logic can be
performance, flexibility, ease of design and production prac- put into every design. ICT’s JEDEC file translator instantly
ticality needed by logic designers today. converts to the PEEL™18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
The PEEL™18CV8 is available in 20-pin DIP, PLCC, SOIC programming support for the PEEL™18CV8 is provided by
and TSSOP packages with speeds ranging from 5ns to popular third-party programmers and development soft-
25ns with power consumption as low as 37mA. EE-Repro- ware. ICT also offers free PLACE development software
grammability provides the convenience of instant repro- and a low-cost development system (PDS-3).
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory test-
ability, thus assuring the highest quality possible.

Figure 2 Pin Configuration Figure 3 Block Diagram

I/CLK 1 20 VCC
I 2 19 I/O
™
I 3 18 I/O
I 4 17 I/O
I 5 16 I/O
I 6 15 I/O
I 7 14 I/O
I 8 13 I/O
I 9 12 I/O
GND 10 11 I

DIP TSSOP

PLCC SOIC

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 PEELTM 18CV8

Figure 4 PEEL™18CV8 Logic Array Diagram

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 PEELTM 18CV8

Function Description the AND array. (Note that PEEL™ device programmers
automatically program all of the connections on unused
The PEEL™18CV8 implements logic functions as sum-of- product terms so that they will have no effect on the output
products expressions in a programmable-AND/fixed-OR
function).
logic array. User-defined functions are created by program-
ming the connections of input signals into the array. User-
configurable output structures in the form of I/O macrocells Programmable I/O Macrocell
further increase logic flexibility. The unique twelve-configuration output macrocell provides
complete control over the architecture of each output. The
Architecture Overview ability to configure each output independently permits
users to tailor the configuration of the PEEL™18CV8 to the
The PEEL™18CV8 architecture is illustrated in the block
precise requirements of their designs.
diagram of Figure 3. Ten dedicated inputs and 8 I/Os pro-
vide up to 18 inputs and 8 outputs for creation of logic func-
tions. At the core of the device is a programmable Macrocell Architecture
electrically-erasable AND array which drives a fixed OR Each I/O macrocell, as shown in Figure 4, consists of a D-
array. With this structure, the PEEL™18CV8 can implement type flip-flop and two signal-select multiplexers. The config-
up to 8 sum-of-products logic expressions. uration of each macrocell is determined by the four
EEPROM bits controlling these multiplexers. These bits
Associated with each of the 8 OR functions is an I/O mac- determine output polarity, output type (registered or non-
rocell which can be independently programmed to one of registered) and input-feedback path (bidirectional I/O, com-
12 different configurations. The programmable macrocells binatorial feedback). Refer to Table 1 for details.
allow each I/O to create sequential or combinatorial logic
functions of active-high or active-low polarity, while provid- Equivalent circuits for the twelve macrocell configurations
ing three different feedback paths into the AND array. are illustrated in Figure 4. In addition to emulating the four
PAL-type output structures (configurations 3,4,9, and 10),
AND/OR LOGIC ARRAY the macrocell provides eight additional configurations.
When creating a PEEL™ device design, the desired mac-
The programmable AND array of the PEEL™18CV8
rocell configuration generally is specified explicitly in the
(shown in Figure 4) is formed by input lines intersecting
design file. When the design is assembled or compiled, the
product terms. The input lines and product terms are used
macrocell configuration bits are defined in the last lines of
as follows:
the JEDEC programming file.
■ 36 Input Lines:
- 20 input lines carry the true and complement of the Output Type
signals applied to the 10 input pins
- 16 additional lines carry the true and complement val- The signal from the OR array can be fed directly to the out-
ues of feedback or input signals from the 8 I/Os put pin (combinatorial function) or latched in the D-type flip-
flop (registered function). The D-type flip-flop latches data
■ 74 product terms: on the rising edge of the clock and is controlled by the glo-
- 64 product terms (arranged in groups of 8) are used bal preset and clear terms. When the synchronous preset
to form sum of product functions term is satisfied, the Q output of the register will be set
- 8 output enable terms (one for each I/O) HIGH at the next rising edge of the clock input. Satisfying
- 1 global synchronous preset term the asynchronous clear will set Q LOW, regardless of the
- 1 global asynchronous clear term clock state. If both terms are satisfied simultaneously, the
clear will override the preset.
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not Output Polarity
there is a logical connection at that intersection. Each prod- Each macrocell can be configured to implement active-high
uct term is essentially a 36-input AND gate. A product term or active-low logic. Programmable polarity eliminates the
that is connected to both the true and complement of an need for external inverters.
input signal will always be FALSE and thus will not affect
the OR function that it drives. When all the connections on
a product term are opened, a “don’t care” state exists and Output Enable
that term will always be TRUE. The output of each I/O macrocell can be enabled or dis-
abled under the control of its associated programmable out-
When programming the PEEL™18CV8, the device pro- put enable product term. When the logical conditions
grammer first performs a bulk erase to remove the previous programmed on the output enable term are satisfied, the
pattern. The erase cycle opens every logical connection in output signal is propagated to the I/O pin. Otherwise, the
the array. The device is configured to perform the user- output buffer is switched into the high-impedance state.
defined function by programming selected connections in

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 PEELTM 18CV8

Under the control of the output enable term, the I/O pin can Registered Feedback
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output Feedback also can be taken from the register, regardless of
enable term will permanently enable the output buffer and whether the output function is to be combinatorial or regis-
yield a dedicated output. Conversely, if every connection is tered. When implementing a combinatorial output function,
intact, the enable term will always be logically false and the
registered feedback allows for the internal latching of states
I/O will function as a dedicated input.
without giving up the use of the external output.
Input/Feedback Select
Design Security
The PEEL™18CV8 macrocell also provides control over
the feedback path. The input/feedback signal associated The PEEL™18CV8 provides a special EEPROM security
with each I/O macrocell may be obtained from three differ- bit that prevents unauthorized reading or copying of
ent locations; from the I/O input pin, from the Q output of designs programmed into the device. The security bit is set
the flip-flop (registered feedback), or directly from the OR by the PLD programmer, either at the conclusion of the pro-
gate (combinatorial feedback). gramming cycle or as a separate step, after the device has
been programmed. Once the security bit is set it is
impossible to verify (read) or program the PEEL™ until the
Bi-directional I/O entire device has first been erased with the bulk-erase
The input/feedback signal is taken from the I/O pin when function.
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output func- Programming Support
tion with a bi-directional I/O.)
ICT’s JEDEC file translator allows easy conversion of exist-
ing 20 pin PLD designs to the PEEL™18CV8, without the
Combinatorial Feedback need for redesign. ICT supports a broad range of popular
The signal-select multiplexer gives the macrocell the ability third party design entry systems, including Data I/O
to feedback the output of the OR gate, bypassing the output Synario and Abel, Logical Devices CUPL and others. ICT
buffer, regardless of whether the output function is regis- also offers (for free) its proprietary PLACE software, an
tered or combinatorial. This feature allows the creation of easy-to-use entry level PC-based software development
asynchronous latches, even when the output must be dis- system.
abled. (Refer to configurations 5,6,7 and 8 in Figure 4.)
Programming support includes all the popular third party
programmers; Data I/O, Logical Devices, and numerous
others. ICT also provides a low cost development program-
Figure 4 Block Diagram of the mer system, the PDS-3.
PEEL™18CV8

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 PEELTM 18CV8

Figure 4 Equivalent Circuits for the Twelve Configurations of the PEEL™18CV8 I/O Macrocell

Configuration
Input/Feedback Select Output Select
# A B C D
1 1 1 1 1 Active Low
Register
2 0 1 1 1 Active High
Bi-directional I/O
3 1 0 1 1 Active Low
Combinatorial
4 0 0 1 1 Active High
5 1 1 1 0 Active Low
Register
6 0 1 1 0 Active High
Combinatorial Feedback
7 1 0 1 0 Active Low
Combinatorial
8 0 0 1 0 Active High
9 1 1 0 0 Active Low
Register
10 0 1 0 0 Active High
Register Feedback
11 1 0 0 0 Active Low
Combinatorial
12 0 0 0 0 Active High

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 PEELTM 18CV8

This device has been designed and tested for the specified
operating ranges. Proper operation outside of these levels
is not guaranteed. Exposure to absolute maximum ratings
may cause permanent damage.
Absolute Maximum Ratings
Symbol Parameter Conditions Rating Unit
VCC Supply Voltage Relative to Ground -0.5 to + 6.0 V
VI, VO Voltage Applied to Any Pin2 Relative to Ground1 -0.5 to VCC + 0.6 V

IO Output Current Per Pin (IOL, IOH) ±25 mA

TST Storage Temperature -65 to +150 °C
TLT Lead Temperature Soldering 10 Seconds +300 °C

Operating Range
Symbol Parameter Conditions Min Max Unit
Commercial 4.75 5.25 V
Vcc Supply Voltage
Industrial 4.5 5.5 V
TA Commercial 0 +70 °C
Ambient Temperature
Industrial -40 +85 °C
TR Clock Rise Time See Note 3. 20 ns
TF Clock Fall TIme See Note 3. 20 ns
TRVCC VCC Rise Time See Note 3. 250 ms

D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)

Symbol Parameter Conditions Min Max Unit

VOH Output HIGH Voltage - TTL VCC = Min, IOH = -4.0 mA 2.4 V
VOHC Output HIGH Voltage - CMOS12 VCC = Min, IOH = -10 µA VCC - 0.3 V

VOL Output LOW Voltage - TTL VCC = Min, IOL = 16mA/24mA 13 0.5 V

VOLC Output LOW Voltage - CMOS12 VCC = Min, IOL = 10 µA 0.15 V

VIH Input HIGH level 2.0 VCC + 0.3 V

VIL Input LOW Voltage -0.3 0.8 V
Input, I/O Leakage Current LOW
IIL VCC = Max, VIN = GND, I/O = High Z -10 µA
Input and I/O pull-ups disabled
Input, I/O Leakage Current LOW
IIP VCC = Max, VIN = GND, I/O = High Z -100 µA
Input and I/O pull-ups enabled
IIH Input, I/O Leakage Current HIGH VCC = Max, VIN = VCC, I/O = High Z 0 (Typical) 40 µA
ISC9 Output Short Circuit Current VCC = 5V, VO = 0.5V, TA = 25°C -30 -135 mA
-5 90

VIN = 0V or VCC, -7 90
ICC10 VCC Current, f=25MHz f = 25 MHz -10/I-10 90/100 mA
All Outputs disabled4 -15/I-15 45/55
-25/I-25 37/50
CIN 7 Input Capacitance TA = 25°C, VCC = 5.0V 6 pF

COUT7 Output Capacitance @ f = 1 MHz 12 pF

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 PEELTM 18CV8

A.C. Electrical Characteristics

Over the operating range 8

-5 -7 -10/I-10 -15/I-15 -25/I-25

Symbol Parameter Units
Min Max Min Max Min Max Min Max Min Max
tPD Input5 to non-registered output 5 7.5 10 15 25 ns

tOE Input5 to output enable6 5 7.5 10 15 25 ns

tOD Input5 to output disable6 5 7.5 10 15 25 ns

tCO1 Clock to Output 4 7 7 12 15 ns

tCO2 Clock to comb. output delay

7.5 10 12 25 35 ns
via internal registered feedback
tCF Clock to Feedback 2.5 3.5 4 8 15 ns
tSC Input5 or feedback setup to clock 3.5 5 5 12 20 ns
tHC Input5 hold after clock 0 0 0 0 0 ns
tCL, tCH Clock low time, clock high time8 3 3.5 5 10 15 ns
tCP Min clock period Ext (tSC + tCO1) 7 12 12 24 35 ns
fMAX1 Internal feedback (1/tSC+tCF)11 166.7 117.6 111 50 28.5 MHz
fMAX2 External Feedback (1/tCP)11 133 83.3 83.3 41.6 28.5 MHz
fMAX3 No Feedback (1/tCL+tCH)11 166.7 142.8 100 50 33.3 MHz
tAW Asynchronous Reset Pulse Width 5 7.5 10 15 25 ns
tAP 5
Input to Asynchronous Reset 5 7.5 10 15 25 ns
tAR Asynchronous Reset recovery time 5 7.5 10 15 25 ns
tRESET Power-on reset time for registers
5 5 5 5 5 µs
in clear state

Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset

Clock

Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs

Notes:
8. Test conditions assume: signal transition times of 3ns or less from the
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V for
10% and 90% points, timing reference levels of 1.5V (Unless otherwise
periods less than 20 ns.
specified).
2. VI and VO are not specified for program/verify operation.
9. Test one output at a time for a duration of less than 1 second.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10%
10. ICC for a typical application: This parameter is tested with the device
and 90% levels.
programmed as an 8-bit Counter.
4. I/O pins are 0V and VCC.
11. Parameters are not 100% tested. Specifications are based on initial
5. “Input” refers to an input pin signal.
characterization and are tested after any design process modification that
6. tOE is measured from input transition to VREF±0.1V, TOD is measured
might affect operational frequency.
from input transition to VOH-0.1V or VOL+0.1V; VREF=VL.
12. Available only for 18CV8 -15/I-15/-25/I-25 grades
7. Capacitances are tested on a sample basis.
13. 24mA available for 18CV8-5/-7. All other speeds are 16mA.

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 PEELTM 18CV8

PEEL™ Device and Array Test Loads

Standard 5V Thevenin VL
Load Equivalent

R1 RL
Output Output

CL R2 CL

Technology R1 R2 RL VL CL
CMOS 12 480kΩ 480kΩ 228kΩ 2.375V 33 pF

TTL -10/-15/-25 235Ω 159Ω 95Ω 2.02V 33 pF

TTL -5/-7 159Ω 118Ω 68Ω 2.129V 33 pF

Ordering Information
Part Number Speed Temperature Package
PEEL18CV8J-5 5 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8P-7 7.5 ns Commercial 20-pin Plastic 300 mil DIP
PEEL18CV8J-7 7.5 ns Commercial 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8S-7 7.5 ns Commercial 20-pin SOIC
PEEL18CV8P-10 Commercial
10 ns 20-pin Plastic 300 mil DIP
PEEL18CV8PI-10 Industrial
PEEL18CV8J-10 Commercial
10 ns 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-10 Industrial
PEEL18CV8S-10 Commercial
10 ns 20-pin SOIC
PEEL18CV8SI-10 Industrial
PEEL18CV8T-10 Commercial
10 ns 20-pin TSSOP 170 mil
PEEL18CV8TI-10 Industrial
PEEL18CV8P-15 Commercial
15 ns 20-pin Plastic 300 mil DIP
PEEL18CV8PI-15 Industrial
PEEL18CV8J-15 Commercial
15 ns 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-15 Industrial
PEEL18CV8S-15 Commercial
15 ns 20-pin SOIC
PEEL18CV8SI-15 Industrial
PEEL18CV8T-15 Commercial
15 ns 20-pin TSSOP 170 mil
PEEL18CV8TI-15 Industrial
PEEL18CV8P-25 Commercial
25 ns 20-pin Plastic 300 mil DIP
PEEL18CV8PI-25 Industrial
PEEL18CV8J-25 Commercial
25 ns 20-pin Plastic (J) Leaded Chip Carrier (PLCC)
PEEL18CV8JI-25 Industrial
PEEL18CV8S-25 Commercial
25 ns 20-pin SOIC
PEEL18CV8SI-25 Industrial
PEEL18CV8T-25 Commercial
25 ns 20-pin TSSOP 170 mil
PEEL18CV8TI-25 Industrial

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 PEELTM 18CV8

Part Number

Device Suffix
PEEL™18CV8 PI-25

Speed
–5 = 5ns tPD
Package –7 = 7.5ns tPD
P = 20-pin Plastic 300mil DIP –10 = 10ns tPD
J = 20-pin Plastic (J) Leaded Chip Carrier (PLCC) –15 = 15ns tPD
S = 20-pin SOIC 300 mil Gullwing –25 = 25ns tPD
T = 20-pin TSSOP 170 mil
Temperature Range
(Blank) = Commercial 0 to +70°C
I = Industrial -40 to +85 °C

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