ECE 2300
Digital Logic & Computer Organization
Spring 2018
Timing Analysis
Lecture 11: 1
Announcements
• Lab report guidelines are uploaded on CMS
– As part of the assignment for Lab 3 report
• Lab 4(A) prelab due tomorrow
Lecture 11: 2
Synchronous Circuits
combinational
logic
CLOCK
• The changes in the state of the memory
elements are synchronized by a clock signal
– All flip-flops (FFs) are synchronized to capture the
inputs “simultaneously” on the clock tick
• Must ensure the output of the combinational
logic has settled before the next clock tick
Lecture 11: 3
Review: Glitches in Synchronous Circuits
X
Y
S
S’
S•Y
S’•X
F
CLOCK
X S’•X
S F
S•Y
Y
CLOCK
Lecture 11: 4
Stable FF Situation
tclk
stable stable
tsetup thold
tffpd
Flip-flop propagation delay (or clock-to-Q delay):
the time it takes for the FF output to be stable
after the clock edge
Lecture 11: 5
What if This Happens?
Q1 combinational D2
IN D Q D Q
CLK1 CLK logic CLK2
CLK
IN
CLK1
Q1
D2
CLK2
D2 input still transitioning
May capture neither
HIGH nor LOW
Lecture 11: 6
Metastable State
unstable
tsetup thold
• Q stuck in the undefined region
between 0 and 1
metastable
• Eventually moves to a stable state, but may
take a while (metastable resolution time)
Lecture 11: 7
But What About This Situation?
X
Y
S
S’
S•Y
S’•X
F
CLOCK
Wrong value captured
X S’•X
S F
S•Y
Y
CLOCK
Lecture 11: 8
Avoiding Timing Failure
• Possible causes of metastability and wrong
value capture
– Clock pulse that is too narrow
– Input changes too soon before a clock edge
– Input changes too soon after a clock edge
• Avoid by meeting setup time, hold time, and
minimum clock pulse width specifications
Lecture 11: 9
Sequential Circuit Timing Analysis
• Timing analysis involves calculating the time
delays between all FF pairs within the circuit
• To determine the maximum operating frequency
and ensure that setup time requirements are met
– The clock cannot be too fast
• To ensure that hold time requirements are met
– The minimum propagation delay of the combinational
logic (contamination delay) cannot be too small
– Independent of clock frequency
Lecture 11: 10
Important Timing Parameters
combinational
logic
CLOCK
tclk
tffpd
tcomb
tsetup thold
Lecture 11: 11
Setup Time Constraint
• tsetup is the minimum amount of time before
the triggering edge during which FF input must
be stable
tclk
tffpd
tcomb
tsetup thold
Lecture 11: 12
Determining Clock Cycle Time
combinational
FF1 logic FF2
CLOCK
• tffpd(max) + tcomb(max) + tsetup ≤ tclk
Every circuit path between every pair of FFs must satisfy the
above equation to run the circuit at a frequency of 1/tclk
• The longest timing path (worst case) determines the
maximum clock frequency
– Worst case temperature and voltage
– Worst case manufacturing variations
Lecture 11: 13
Example: Setup Time Calculations
combinational
FF1 logic FF2
CLOCK
Prop Delay (ns) Setup Hold
min max Time Time
(ns) (ns)
FF 1 7 3 1
Comb 3 9 - -
• What’s the best achievable cycle time?
Lecture 11: 14
Example: Setup Time Calculations
combinational
FF1 logic FF2
CLOCK
Prop Delay (ns) Setup Hold
min max Time Time
(ns) (ns)
FF 1 7 3 1
Comb 3 9 - -
• tclk >= tffpd(max) + tcomb(max) + tsetup = 7 + 9 + 3 = 19ns
Lecture 11: 15
Hold Time Constraint
combinational
FF1 logic FF2
CLOCK
• thold is the minimum amount of time after the triggering
edge during which FF input must remain stable
– Otherwise, the receiving flip-flop may be contaminated with an
unexpected value
• Need to consider minimum propagation delays
(contamination delays) for hold time calculations
tffpd(min) + tcomb(min) ≥ thold
Lecture 11: 16
Example: Hold Time Constraint
very short wire (assume
Q1 negligible delay) D2
IN Q2
FF1 FF2
CLOCK
IN
CLOCK tffpd tffpd
Q1
D2
Q2
Hold time windows (thold)
D2 must be held stable for FF2
tffpd(min) + tcomb(min) = tffpd(min)+0 ≥ thold
Lecture 11: 17
Example: Hold Time Calculations
combinational
FF1 logic FF2
CLOCK
Prop Delay (ns) Setup Hold
min max Time Time
(ns) (ns)
FF 1 7 3 1
Comb 3 9 - -
• Hold time at FF2 met?
Lecture 11: 18
Clock Skew Complicates
Matters Further
• Clock may not reach all flip-flops simultaneously
combinational
FF1 logic FF2
CLK2
CLK1
[long wire] CLOCK
(assume nontrivial delay)
tskew
CLK1 (delayed)
CLK2
tskew(max) : Maximum clock skew
tskew(min) : Minimum clock skew
Lecture 11: 19
Cycle Time With Clock Skew
Q1 D2
IN Combinational
FF1 logic FF2
CLK1 CLK2
[long wire]
CLOCK
IN
CLK1(delayed)
Q1 (delayed)
D2 (delayed)
CLK2
tskew tsetup
Lecture 11: 20
Negative Clock Skew
Q1 D2
IN Combinational
FF1 logic FF2
CLK1 CLK2
[long wire]
CLOCK
IN
CLK1(delayed) tffpd
Q1 (delayed) tcomb
D2 (delayed)
CLK2
tskew tsetup
Sending FF receives clock later than receiving FF
tffpd(max) + tcomb(max) + tsetup ≤ tclk – tskew(max)
Harmful skew for meeting setup time constraint
Lecture 11: 21
Positive Clock Skew
Q1 D2
IN Combinational
FF1 logic FF2
CLK1 CLK2
CLOCK [long wire]
IN
CLK1
Q1
D2
CLK2 (delayed)
tskew tsetup
Receiving FF receives clock later than sending FF
tffpd(max) + tcomb(max) + tsetup ≤ tclk + tskew(min)
Beneficial skew for meeting setup time constraint
Lecture 11: 22
Hold Time With Positive Clock Skew
Q1 D2
IN Combinational
FF1 logic FF2
CLK1 CLK2
CLOCK [long wire]
IN
CLK1
Q1
D2
CLK2 (delayed)
tskew thold (hold time window
effectively widened)
Receiving FF receives clock later than sending FF
tffpd(min) + tcomb(min) ≥ thold + tskew(max)
Harmful skew for meeting hold time constraint
Lecture 11: 23
Hold Time With Negative Clock Skew
Q1 D2
IN D Q Combinational D Q
logic
CLK1 CLK CLK2 CLK
[long wire]
CLOCK
What if sending FF receives clock later than
receiving FF?
tffpd(min) + tcomb(min) ≥ thold - tskew(min)
Beneficial skew for meeting hold time constraint
Lecture 11: 24
Example: Setup Analysis with Clock Skew
combinational
FF1 logic FF2
CLOCK
Clock may arrive at FF1 up to 1ns later than FF2
Prop Delay (ns) Setup Hold Time
min max Time (ns) (ns)
FF 1 7 3 1
Comb 3 9 - -
• What’s the best achievable cycle time?
tffpd(max) + tcomb(max) + tsetup <= tclk - tskew(max)
tclk >= 7 + 9 + 3 + 1 = 20ns
Lecture 11: 25
Before Next Class
• H&H 5.1-5.2.3, 5.5
Next Time
Binary Arithmetic
Lecture 11: 26
