PCF8574

www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008

REMOTE 8-BIT I/O EXPANDER FOR I2C BUS

1FEATURES
• Low Standby-Current Consumption of • Compatible With Most Microcontrollers
10 µA Max • Latched Outputs With High-Current Drive
• I2C to Parallel-Port Expander Capability for Directly Driving LEDs
• Open-Drain Interrupt Output • Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
RGY PACKAGE
(TOP VIEW)
DGV OR PW PACKAGE

INT
RGT PACKAGE (TOP VIEW)

P7
DW OR N PACKAGE
(TOP VIEW)
(TOP VIEW)
1 20
16 SDA
15 SCL

INT 1 20 P7
14 INT
13 P7

A0 1 16 VCC SCL 2 19 P6 2
SCL 19 P6
A1 2 15 SDA NC 3 18 NC
NC 3 18 NC
A2 3 14 SCL VCC 1 12 P6
SDA 4 17 P5
SDA 4 17 P5
P0 4 13 INT VCC 5 16 P4 5 16
A0 2 11 P5 VCC P4
P1 5 12 P7 A0 6 15 GND 6 15
A1 3 10 P4 A0 GND
P2 6 11 P6 A1 7 14 P3 7 14
A2 4 9 GND A1 P3
P3 7 10 P5 NC 8 13 NC
8 13
NC NC
A2 12 P2
P0 5
P1 6

P3 8
P2 7

9 12
GND 8 9 P4 A2 9 P2
10 11 10 11
P0 P1
P0

P1
NC – No internal connection
NC – No internal connection

DESCRIPTION/ORDERING INFORMATION
This 8-bit input/output (I/O) expander for the two-line bidirectional bus (I2C) is designed for 2.5-V to 6-V VCC
operation.
The PCF8574 provides general-purpose remote I/O expansion for most microcontroller families via the I2C
interface [serial clock (SCL), serial data (SDA)].
The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-current drive
capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use
of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to VCC is
active. An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device turns
on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high
before being used as inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2001–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCF8574

SCPS068G – JULY 2001 – REVISED MAY 2008 ............................................................................................................................................................... www.ti.com

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The PCF8574 provides an open-drain output (INT) that can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time, tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed
to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in
the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the
acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge
clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of
the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or
writing to, another device does not affect the interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C bus. Therefore, the PCF8574 can remain a simple slave
device.

ORDERING INFORMATION
TA PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
PCF8574N
PDIP – N Tube of 25 PCF8574N
PCF8574NE4
QFN – RGT Reel of 3000 PCF8574RGTR ZWJ
PCF8574RGYR
QFN – RGY Reel of 1000 PF574
PCF8574RGYRG4
PCF8574DW
Tube of 40
PCF8574DWE4
SOIC – DW PCF8574
–40°C to 85°C PCF8574DWR
Reel of 2000
PCF8574DWRE4
PCF8574PW
Tube of 70
PCF8574PWE4
TSSOP – PW PF574
PCF8574PWR
Reel of 2000
PCF8574PWRE4
PCF8574DGVR
TVSOP – DGV Reel of 2000 PF574
PCF8574DGVRE4

(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.

2 Submit Documentation Feedback Copyright © 2001–2008, Texas Instruments Incorporated

Product Folder Link(s): PCF8574

 PCF8574

www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008

LOGIC DIAGRAM (POSITIVE LOGIC)

PCF8574
13 Interrupt
INT LP Filter
Logic

1 4
A0 P0
2
A1 5
3 P1
A2 6
P2
14
SCL 7
Input I2C Bus P3
Shift I/O
15 Filter Control 8 Bit
SDA Register Port 9
P4
10
P5
11
P6
12
P7

Write Pulse

16 Read Pulse
VCC Power-On
8 Reset
GND

Pin numbers shown are for the DW and N packages.

SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT

Write Pulse VCC

100 µA

Data From
D Q
Shift Register
FF
CI P0−P7
S
Power-On
Reset
D Q
GND
FF
CI
Read Pulse S

To Interrupt
Data to Logic
Shift Register

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PCF8574

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I2C Interface
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent,
most-significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general
call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA
I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values
read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte
is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the
acknowledge, they are ignored by this device. Data are output only if complete bytes are received and
acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the
clock cycle for the acknowledge.
A stop condition, which is a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the
master.

Interface Definition
BIT
BYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
2
I C slave address L H L L A2 A1 A0 R/W
I/O data bus P7 P6 P5 P4 P3 P2 P1 P0

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Figure 1 and Figure 2 show the address and timing diagrams for the write and read modes, respectively.
Integral Multiples of Two Bytes

SCL 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
ACK
Start From Slave
ACK ACK
Condition From Slave From Slave
R/W
Slave Address Data Data

SDA S 0 1 0 0 A2 A1 A0 0 A P7 P6 1 P0 A P7 P0 A

P5
Write to
Port

Data Output Data A0

and B0
Voltage
Valid
tpv

P5 Output
Voltage

P5 Pullup IOH
Output IOHT
Current

INT

tir

Figure 1. Write Mode (Output)

SCL 1 2 3 4 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
5

ACK ACK ACK

R/W From Slave From Master From Master

SDA S 0 1 0 0 A2 A1 A0 1 A P7 P6 P5 P4 P3 P2 P1 P0 A P7 P6 P5 P4 P3 P2 P1 P0 A P7 P6

Read From
Port

Data Into
Port
P7 to P0 P7 to P0

th tsu

INT

tiv tir tir

A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by
a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.

Figure 2. Read Mode (Input)

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SCPS068G – JULY 2001 – REVISED MAY 2008 ............................................................................................................................................................... www.ti.com

Address Reference
INPUTS
I2C BUS SLAVE ADDRESS
A2 A1 A0
L L L 32 (decimal), 20 (hexadecimal)
L L H 33 (decimal), 21 (hexadecimal)
L H L 34 (decimal), 22 (hexadecimal)
L H H 35 (decimal), 23 (hexadecimal)
H L L 36 (decimal), 24 (hexadecimal)
H L H 37 (decimal), 25 (hexadecimal)
H H L 38 (decimal), 26 (hexadecimal)
H H H 39 (decimal), 27 (hexadecimal)

Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
VI Input voltage range (2) –0.5 VCC + 0.5 V
VO Output voltage range (2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –20 mA
IOK Input/output clamp current VO < 0 or VO > VCC ±400 µA
IOL Continuous output low current VO = 0 to VCC 50 mA
IOH Continuous output high current VO = 0 to VCC –4 mA
Continuous current through VCC or GND ±100 mA
DGV package (3) 92
DW package (3) 57
N package (3) 67
θJA Package thermal impedance °C/W
PW package (3) 83
RGT package (4) 53
RGY package (4) 37
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) The package thermal impedance is calculated in accordance with JESD 51-5.

Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 2.5 6 V
VIH High-level input voltage 0.7 × VCC VCC + 0.5 V
VIL Low-level input voltage –0.5 0.3 × VCC V
IOH High-level output current –1 mA
IOL Low-level output current 25 mA
TA Operating free-air temperature –40 85 °C

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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
VIK Input diode clamp voltage II = –18 mA 2.5 V to 6 V –1.2 V
VPOR Power-on reset voltage (2) VI = VCC or GND, IO = 0 6V 1.3 2.4 V
IOH P port VO = GND 2.5 V to 6 V 30 300 µA
IOHT P-port transient pullup current High during acknowledge, VOH = GND 2.5 V –1 mA
SDA VO = 0.4 V 2.5 V to 6 V 3
IOL P port VO = 1 V 5V 10 25 mA
INT VO = 0.4 V 2.5 V to 6 V 1.6
SCL, SDA ±5
II INT VI = VCC or GND 2.5 V to 6 V ±5 µA
A0, A1, A2 ±5
IIHL P port VI ≥ VCC or VI ≤GND 2.5 V to 6 V ±400 µA
Operating mode VI = VCC or GND, IO = 0, fSCL = 100 kHz 40 100
ICC 6V µA
Standby mode VI = VCC or GND, IO = 0 2.5 10
Ci SCL VI = VCC or GND 2.5 V to 6 V 1.5 7 pF
SDA 3 7
Cio VIO = VCC or GND 2.5 V to 6 V pF
P port 4 10

(1) All typical values are at VCC = 5 V, TA = 25°C.

(2) The power-on reset circuit resets the I2C-bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).

I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
MIN MAX UNIT
fscl I2C clock frequency 100 kHz
tsch 2
I C clock high time 4 µs
tscl I2C clock low time 4.7 µs
tsp I2C spike time 100 ns
2
tsds I C serial data setup time 250 ns
tsdh I2C serial data hold time 0 ns
ticr I2C input rise time 1 µs
ticf I2C input fall time 0.3 µs
2
tocf I C output fall time (10-pF to 400-pF bus) 300 ns
tbuf I2C bus free time between stop and start 4.7 µs
tsts I2C start or repeated start condition setup 4.7 µs
tsth 2
I C start or repeated start condition hold 4 µs
tsps I2C stop condition setup 4 µs
tvd Valid data time SCL low to SDA output valid 3.4 µs
2
Cb I C bus capacitive load 400 pF

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Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 4)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
tpv Output data valid SCL P port 4 µs
tsu Input data setup time P port SCL 0 µs
th Input data hold time P port SCL 4 µs
tiv Interrupt valid time P port INT 4 µs
tir Interrupt reset delay time SCL INT 4 µs

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 PCF8574

www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008

PARAMETER MEASUREMENT INFORMATION

VCC

RL = 1 kΩ

Pn
DUT

CL = 10 pF to 400 pF

LOAD CIRCUIT

2 Bytes for Complete Device

Programming

Stop Start Bit 0 Stop

Condition Condition Bit 7 Bit 6 LSB Acknowledge Condition
(P) (S) MSB (R/W) (A) (P)

tscl tsch

0.7 × VCC
SCL
0.3 × VCC
ticr tPHL tsts
tbuf ticf
tsp tPLH
0.7 × VCC
SDA
0.3 × VCC
ticf ticr tsdh tsps
tsth tsds Repeat
Start Stop
Start or
Condition Condition
Repeat
Start
Condition VOLTAGE WAVEFORMS
2
Figure 3. I C Interface Load Circuit and Voltage Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

Acknowledge
From Slave
Start Acknowledge
Condition From Slave
R/W
Slave Address Data From Port Data From Port

S 0 1 0 0 A2 A1 A0 1 A Data 1 A Data 3 1 P

1 2 3 4 5 6 7 8 A A

tir B
tir
B

INT

A
tiv tsps
A
Data
Into Data 1 Data 2 Data 3
Port

0.7 × VCC 0.7 × VCC

INT SCL
R/W A
0.3 × VCC 0.3 × VCC

tiv tir

0.7 × VCC 0.7 × VCC

Pn INT
0.3 × VCC 0.3 × VCC

View A−A View B−B

Figure 4. Interrupt Voltage Waveforms

0.7 × VCC
SCL W A D
0.3 × VCC
Slave
Acknowledge

SDA
ÎÎÎ
ÎÎÎ
ÎÎÎ
tpv

Pn
ÎÎÎ
ÎÎÎ Last Stable Bit
Unstable
Data

Figure 5. I2C Write Voltage Waveforms

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 PCF8574

www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008

PARAMETER MEASUREMENT INFORMATION (continued)

VCC VCC

RL = 1 kΩ RL = 4.7 kΩ

DUT SDA DUT INT

CL = 10 pF to 400 pF CL = 10 pF to 400 pF

GND GND
SDA LOAD CONFIGURATION INTERRUPT LOAD CONFIGURATION

Figure 6. Load Circuits

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Product Folder Link(s): PCF8574
 PACKAGE OPTION ADDENDUM

www.ti.com 21-Dec-2009

PACKAGING INFORMATION

Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
PCF8574DGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DW ACTIVE SOIC DW 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DWE4 ACTIVE SOIC DW 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DWR ACTIVE SOIC DW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574N ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
PCF8574NE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
PCF8574PW ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574RGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCF8574RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PCF8574RGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 21-Dec-2009

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Dec-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PCF8574DGVR TVSOP DGV 20 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
PCF8574DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCF8574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PCF8574RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
PCF8574RGYR VQFN RGY 20 3000 180.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Dec-2009

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCF8574DGVR TVSOP DGV 20 2000 346.0 346.0 29.0
PCF8574DWR SOIC DW 16 2000 346.0 346.0 33.0
PCF8574PWR TSSOP PW 20 2000 346.0 346.0 33.0
PCF8574RGTR QFN RGT 16 3000 370.0 355.0 55.0
PCF8574RGYR VQFN RGY 20 3000 190.5 212.7 31.8

Pack Materials-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30
0,65 0,10 M
0,19
14 8

0,15 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25
1 7
0°– 8°
A 0,75
0,50

Seating Plane

1,20 MAX 0,15 0,10

0,05

PINS **
8 14 16 20 24 28
DIM

A MAX 3,10 5,10 5,10 6,60 7,90 9,80

A MIN 2,90 4,90 4,90 6,40 7,70 9,60

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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