The NC-Verilog® Simulator is the industry’s premier Verilog® simulator, delivering
high performance and capacity with transaction/signal viewing and integrated
coverage analysis. The NC-Verilog Simulator is fully compatible with the Cadence®
Incisive™ Unified Simulator, providing an easy upgrade path to comprehensive
digital verification from system design to system design-in for nanometer-scale ICs.
INCISIVE FUNCTIONAL IP Incisive verification IP VERIFICATION PLATFORM Algorithm The functional verification of development CoWare SPW nanometer-scale ICs requires speed Analog/ and efficiency. Yet today's fragmented Mixed-signal Incisive AMS methodologies make it impossible to Acceleration/ optimize either. Each verification Emulation Incisive Palladium systems stage has its own methodology, tools, Acceleration- models, and user interface. Engineers on-Demand Incisive must re-create almost everything at XLD Unified test every stage. The Incisive verfication generation Incisive platform is the world's first functional Unified HDL analysis verification platform that supports a Simulator unified methodology to deliver the Assertions fastest, most efficient verification in Comprehensive the industry. coverage Transaction support NC-SC Simulator Debug/analysis NC-VHDL NC- Simulation Simulator Verilog Simulator Third-party EDA support
Figure 1: The NC-Verilog Simulator is the fully compatible Verilog simulator
in the Cadence Incisive functional verification platform NC-VERILOG SIMULATOR performance by identifying the areas INTEGRATED CODE COVERAGE that consume the most simulation The NC-Verilog Simulator provides The NC-Verilog Simulator delivers time. NC-Verilog 64-bit capacity access to a wide variety of coverage high-performance, high-capacity simulates designs larger than 100 metrics to help determine how well Verilog simulation with transaction/ million gates. tests have exercised the design. These signal viewing and integrated coverage analysis. It is fully compatible with the include block coverage, path coverage, UNIFIED ENVIRONMENT AND DEBUG expression coverage, state variable Incisive functional verification platform, so design teams can easily The unified NC-Verilog simulation coverage, state transition coverage, upgrade to the Incisive Unified and debug environment makes it easy state sequence coverage, and toggle Simulator and Incisive XLD team to manage multiple simulation runs coverage. Integrated coverage analysis verification, with native support for and analyze the design and testbench. and display tools speed the process of Verilog, VHDL, SystemC®, SystemC Its transaction/waveform viewer determining which additional tests Verification Library, PSL/Sugar assertions, and schematic tracer quickly trace will need to be developed. and Acceleration-on-Demand. design behavior back to the source. The NC-Verilog source viewer lets FLEXIBLE OPTIONS designers examine their design, set BENEFITS Upgrade the NC-Verilog Simulator to complex breakpoints to control the Incisive platform: • Speeds verification with premier simulation execution, and access simulation performance results in both interactive and post- • Supports multilanguage simulation processing debug modes. Tcl/Tk (Verilog, VHDL, SystemC, SystemC • Designs chips in excess of 100M gates support enables customization and Verification Library, and PSL/Sugar) with 64-bit capacity integration of applications into the • Speeds performance 100 times through • Maximizes efficiency with unified environment. Industry-standard native transaction-level simulation transaction/signal viewer application programming interfaces • Speeds performance up to 100 times • Ensures comprehensive verification like VPI, PLI, OMI, and compiled SDF with Acceleration-on-Demand with integrated code coverage enable user-defined checks and analyses so that the project team • Reduces testbench development by • Provides a quick, fully compatible need learn only one environment. up to 50% through transaction-level upgrade to the Incisive platform support, unified test generation, • Ensures accuracy with certified libraries and verification component re-use from more than 30 ASIC vendors
FEATURES
PREMIER PERFORMANCE AND CAPACITY The NC-Verilog Simulator provides the industry’s premier simulation performance for Verilog designs using the unique native-compiled architecture of the Incisive Unified Simulator. It produces efficient native machine code directly from Verilog for high-speed execution. Linked list scheduling of the resulting data structures pre-processes signal actions and maximizes the effectiveness of modern caching algorithms available in today’s computing platforms. The NC-Verilog performance profiler identifies bottlenecks. Designers find areas of high activity by viewing how each module contributes to overall performance. Minor changes can greatly improve simulation
