AXI Protocol v3

AGENDA

1. Introduction

2. Access Control

3. Low Power Interface

4. Interoperability
 Basic Notations

Symbol Channel

AR Address Read

R Read Data

AW Write Address

W Write Data

B Write Response

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Exclusive Accesses

Semaphore type operation.

Doesnt impact bus latency.
Max. achievable BW remains same.
AxLOCK is used to achieve this.
RRESP and BRESP to indicate the success or failure.
Mechanism to detect if a slave doesnt support the exclusive access.
 Master performs an exclusive read operation from a memory.
Process
After sometime, it performs a write operation, with AWID and ARID same
Indicate
A success, if the no other master has written to that memory location.
Updates the value

A failure, if the memory address is already used after the access is requested.
Fails to update the value.

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Masters perspective:
Master gives an exclusive access request.
The slave gives an EXOKAY if the request is accepted and an OKAY if the exclusive access is not supported.
OKAY response means that the slave doesnt support.
After sometime it gives an EXCLUSIVE write operation.
If the location is undisturbed, then EXOKAY is given and the memory is updated.
If the contents have changed, then OKAY response is returned and the location is not updated.
But the location is still monitored till a new request comes from the same ARID.

Slaves perspective:
No support, send an OKAY and not care about the AxLOCK signal.
Else record the ARID and the address requested and monitor the address through Exclusive Access Monitor.
If an Exclusive Write comes from the same AWID, then depending on the address, if the address isnt recorded
or the memory location has changed, then it gives an OKAY.
Else, the address is updated and an EXOKAY is returned.

WHY?
 The burst size and burst length of an exclusive write with a given ID must be the same as the burst size
Access Restriction
and burst length of the preceding exclusive read with the same ID.
The address of an exclusive access must be aligned to the total number of bytes in the transaction, that
is, the product of the burst size and burst length.
The addresses for the exclusive read and the exclusive write must be identical.
The ARID value of the exclusive read must match the AWID value of the exclusive write.
The control signals for the exclusive read and exclusive write transactions must be identical.
The number of bytes to be transferred in an exclusive access burst must be a power of 2, that is, 1, 2, 4,
8, 16, 32, 64, or 128 bytes.
The maximum number of bytes that can be transferred in an exclusive burst is 128.
The value of the AxCACHE signals must guarantee that the slave that is monitoring the exclusive
access sees the transaction. For example, an exclusive access must not have an AxCACHE value that
indicates that the transaction is Cacheable.
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 Locked Accesses
Only in AXI3 and not in AXI4.
AxLOCK signal, then the interconnect ensures that the slave region is blocked.
Before a master starts a lock, it must ensure that all the previous locks are
released.
All the locked sequence transaction must have the same AxID.
Recommendations:
Keep the locked transaction within a single 4KB address region.
Limit the sequence to 2 transactions.

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 Low Power Interface
Classes:
No power down sequence and can indicate when clock can be turned off
With a power down sequence and needs clock to be turned off when the power down is
completed
Needs a system clock controller to indicate when to initiate the power down sequence, with an
acknowledgement signal.

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1. Indicates when the clock needs to be enables or disabled
CACTIVE
2. High indicates the requirement of clock and low indicates the contrary.

CSYSREQ
1. Initiate the request to enter or exit low power state.

CSYSACK
1. Enters the low state when receives the request and returns back to
high when it receives an exit request.
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Acceptance of an enter signal

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Denial of an enter signal

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Exit low power system controller initiated

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Exit low power Peripheral initiated

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1. Every component must support all kinds of inputs.
Default signaling and Interoperability
2. Each component need not generate all kinds of outputs.
1. So, all the components work with all the other components

Optional Outputs
1. if the component might require a value other than the default value, then it must have
the output signal
2. if the component always requires the value that doesnt match the default value, it is
not required that the component has the signal present

Optional Inputs
1. An input can be omitted when the slave or the master doesnt need the signal to
complete the functional operation 17
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 Addressing
1. There is no restriction on the address size sent by the master / slave.
1. If the slave address bus is wider than the master, by default all zeros are added to the
remaining higher order bits
2. In contrary, if the address is narrow, then the higher order bits must be left
unconnected.

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Memory slaves

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