L6208

FULLY INTEGRATED STEPPER MOTOR DRIVER

PRELIMINARY DATA

OPERATING SUPPLY VOLTAGE FROM 8 TO 52V

5A PEAK CURRENT (2.8A DC)

RDS(ON) 0.3 TYP. VALUE @ Tj = 25 C

BUILT-IN DECODING LOGIC

BUILT-IN CONSTANT OFF-TIME PWM

CURRENT CONTROL

PowerDIP24
PowerSO36
(20+2+2)
ORDERING NUMBERS:

FAST/SLOW DECAY MODE SELECTION

HIGH SIDE OVER CURRENT PROTECTION

5.6A TYP.

CROSS CONDUCTION PROTECTION

THERMAL SHUTDOWN

OPERATING FREQUENCY UP TO 100KHz

INTRINSIC FAST FREE WHEELING DIODES

UVLO: UNDER VOLTAGE LOCKOUT

L6208N

DESCRIPTION
The L6208 is a fully integrated stepper motor driver
manufactured with multipower BCD technology,
which combines isolated DMOS power transistors
with CMOS and bipolar circuits on the same chip.

SO24
(20+2+2)

L6208PD

L6208D

The logic inputs are CMOS/TTL and P compatible.

The device also includes all the circuitry needed to
drive a stepper motor, that is the constant off time
PWM control that performs the chopping current control and the state machine that generates the stepping sequence. Other features are the protection of
the high side switches against unsafe over current
conditions and the thermal shutdown.
The L6208 is assembled in PowerDIP24(20+2+2),
PowerSO36 and SO24(20+2+2) packages.

BLOCK DIAGRAM
OUT1A
GND

SENSEA

OUT2A

VS A

VS A
VS A

VS A

GND
GND
Vref A

GND

PWMA
RCA

EN

Logic
&
Drivers

Reset
Clock

VBOOT
Charge
Pump

VCP

CW/CCW
Vref B

PWMB

HALF/FULL

RCB
Control

VS B
VS B

VS B

OUT1 B

SENSE B

OUT2B

VS B

January 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice.

1/15

L6208
FUNCTIONAL BLOCK DIAGRAM

Vboot

VCP

Voltage
Regulator

Thermal
Protection

10V

EN

VSA

Charge
Pump

Vboot

Vboot

Vboot

5V

Over
Current
Detection

CONTROL

OUT1A

HALF/FULL

10V

10V

OUT2A

Clock
RESET

Input
Interface

SENSE A
Decoding
Logic

CW/CCW
RCA

Masking
Tim e

One Shot

Sense
Comparator

P W M

VrefA

BRIDGE A

VSB
OUT1B
BRIDGE B

RCB

OUT2B
SENSE B

VrefB

ABSOLUTE MAXIMUM RATINGS

Symbol

Value

Unit

60

Input and Enable Voltage Range

-0.3 to +7

VrefA, VrefB

Voltage Range at Vref pins

-0.3 to +7

V RCA,RCB

Voltage Range at RCA and RCB

pins

-0.3 to +7

VS
VIN,V EN

Parameter

Test conditio ns

Supply Voltage

V SENSE

DC Sensing Voltage Range

-1 to +4

VBOOT

Bootstrap Peak Voltage

V S + 10

IS(peak)

Pulsed Supply Current (for each

VS pin), internally limited by the
overcurrent protection.

7.1

IS

DCvSupply Current (for each VS

pin)

2.8

VOD

Differential Voltage Between

VS A, OUT1A, OUT2A, SENSEA and
VS B, OUT1B, OUT2 B, SENSEB

60

-40 to 150

Tstg, TOP

2/15

Storage and Operating

Temperature Range

tPULSE < 1ms

L6208
RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

VS

Supply Voltages

VOD

Differential Voltage Between

VS A, OUT1A, OUT2A, SENSEA and
VS B, OUT1B, OUT2B, SENSEB

VSENSE

MIN

MAX

Unit

12

52

52

-6
-1

6
1

V
V

-0.1

Sensing voltage
(pulsed tw<trr)
(DC)

Vref

Vref Operating Voltage

IOUT

DC Output Current

Tj

Operating Junction Temperature

fc

Commutation Frequency

-25

2.8

+125

100

kHz

PIN CONNECTIONS (Top View)

GND

36

GND

NC

2
3

35
34

NC

NC
VS A

33

VS B

OUT2A

32

OUT2B

NC

Clock

24

CW/CCW

23

Vref A
Reset

SENSEA

2
3

22

VCP

NC

31

NC

RCA

21

OUT2A

VCP

30

VBOOT

OUT1A

20

VS A

19

GND

29
28

EN

GND

Reset
Vref A

GND

18

GND

Clock

OUT1B
RCB

8
9

17
16

VS B

10
11

SENSEB
Vref B

10
11

15
14

VBOOT
EN

HALF/FULL

12

13

Control

PDIP24/SO24

OUT2B

CW/CCW
SENSEA
RCA

12
13

27

Control
HALF/FULL

26

Vref B

25
24

SENSEB
NC

RCB

NC
OUT1A

15

23
22

NC
NC

16
17

21
20

NC

GND

18

19

GND

14

OUT1B
NC

PowerSO36

3/15

L6208
PIN DESCRIPTION
Name

PowerSO36

PDIP24/
SO24

VS A

20

Supply voltage of the bridge A.

VS B

33

17

Supply voltage of the bridge B. Must be connected to VS A.

OUT1A
OUT2A

15
5

5
21

Bridge A outputs.

OUT1B
OUT2B

22
32

8
16

Bridge B outputs.

SENSE A

12

Sense resistor for the bridge A.

SENSE B

25

10

Sense resistor for the bridge B.

GND

1, 18, 19, 36

6, 7,
18, 19

EN

29

14

Chip Enable. A Low logic level applied to this pin switches Off all the
power DMOSs.

HALF/FULL

27

12

Logic input. When high, HALF STEP operation is selected; a Low logic
level selects FULL STEP operation.
ONE-PHASE-ON FULL STEP MODE ( wave mode) is obtained by
selecting FULL when the state machine is at an even numbered state.
TWO-PHASE-O N FULL STEP MODE ( normal mode) is obtained by
selecting FULL when the state machine is at an odd numbered state.

Reset

23

Logic input. A Low logic level restores the home state (state 1) on the
state machine.

Clock

10

Logic input. Step Clock. The step occurs on the rising edge of this signal.

CW/CCW

11

Logic input. Logic High sets clockwise direction. Logic Low sets
counterclockwise direction.

Control

28

13

Logic input. Selects chopping style. FAST DECAY is selected with logic
Low. A logic High selects SLOW DECAY.

Vref A

24

A voltage applied to these pins sets the reference voltage of the sense
comparators, determining the output current in PWM current control.

Vref B

26

11

VCP

22

Bootstrap oscillator. Oscillator output for the external charge pump.

VBOOT

30

15

Supply voltage to overdrive the upper DMOSs.

RCA

13

RCB

24

A parallel RC network connected to these pins sets the OFF time of the
low-side power DMOS of the correspondent bridge. The pulse generator
is a monostable triggered by the output of the sense comparator of the
bridge (tOFF = 0.69 RC).

4/15

Function

Common ground terminals. In Powerdip and SO packages, these pins

are also used for heat dissipation toward the PCB.

L6208
THERMAL DATA
Symbol

Description

PDIP24

SO24

PowerSO36

Unit

R th-j-pins

MaximumThermal Resistance
Junction-Pins

18

14

C/W

R th-j-case

Maximum Thermal Resistance

Junction-Case

C/W

Rth-j-amb1

MaximumThermal Resistance
Junction-Ambient (1)

42

50

35

C/W

Rth-j-amb2

Maximum Thermal Resistance

Junction-Ambient (2)

58

77

62

C/W

<(1)>Mounted on a multiplayer PCB with a dissipating copper surface on the bottom side of 2 x 12mm x 25mm (with a thickness of
at least 35 m).
<(2)>Its the same condition of the point above, without any heatsinking surface on the board.

ELECTRICAL CHARACTERISTICS
(Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol

Parameter

VS

Supply Voltage

IS

Quiescent Supply Current

Tj

Thermal Shutdown Temperature

Test Conditions

Min

Typ

8
All Bridges OFF

5.5

Max

Unit

52

10

mA
C

150

Output DMOS Transistors

I DSS

mA

0.34

0.4

Tj =125 C

0.53

0.59

Tj = 25 C

0.28

0.34

Tj =125 C

0.47

0.53

Forward ON Voltage

ISD = 2.8A, EN = LOW

1.2

1.4

trr

Reverse Recovery Time

If = 2.8A

300

ns

t fr

Forward Recovery Time

200

ns

RDS(ON)

Leakage Current

V S = 52V

High-side Switch ON Resistance

Tj = 25 C

Low-side Switch ON Resistance

Source Drain Diodes

VSD

Switching Rates
tD(on)

Output to out Turn ON Delay

Time (3)

ILOAD =2.8A

110

250

400

ns

Output Rise Time (3)

ILOAD =2.8A

20

105

300

ns

Enable to out Turn OFF Delay

Time (3)

ILOAD =2.8A

240

580

760

ns

tOFF

Output Fall Time (3)

ILOAD =2.8A

20

78

300

ns

tDCLK

Clock to output delay time (3)

ILOAD =2.8A

tON
tD(OFF)

5/15

L6208
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol
tdt
tblank
fCP

Parameter

Test Conditions

Min

Typ

Max

Unit
s

Dead Time Protection

Internal Blanking Time on SENSE

pins

1.5

0.75

MHz

Charge pump frequency

UVLO comp
Vth(ON)

Turn ON threshold

6.6

7.4

Vth(OFF)

Turn OFF threshold

5.6

6.4

Logic Input
VINL

Low level logic input voltage

-0.3

0.8

VINH

High level logic input voltage

IINH

High level logic input current

V IN, EN = 5 V

70

IINL

Low level logic input current

V IN, EN = GND

-10

tCLK

Minimum clock time (4)

see Fig. 2

tS

Minimum set up time (4)

tH

Minimum hold time (4)

tR

Minimum reset time (4)

Minimum reset to clock delay (4)

7.1

0.4

tRCLK

0.1

Over Current Protection

IS OVER
VDIAG

Input supply over current

protection threshold

Tj = 25 C

Open drain low level output

voltage

I = 4 mA

5.6

Comparator and Monostable

IRCA, RCB Source current at RC pins

V ref

Input common mode comparator

voltage range

Vth

Comparator threshold voltage on

SENSE pins

tprop

V RC=2.5 V

mA

-0.1

V ref A, B = 0.5 V

Vref - 5mV

Vref + 5mV

Turn OFF propagation delay (5)

V ref A, B = 0.5 V

0.1

tOFF

PWMRecirculation time

20 k < R < 100 k

0.1 nF < C < 100 nF

Ibias

Input bias current at Vref pins

0.2

0.3

0.67RC 0.69RC 0.71RC

0.2

<(3)>Resistive load used. See Fig. 1.

<(4)>See Fig. 2.
<(5)>Defined as the time between the voltage at the input of the current sense reaching the V ref threshold and the lower DMOS
switch beginning to turn off. The voltage at SENSE pin is increased instantaneously from V ref -10 mV to Vref +10 mV.

6/15

L6208
Figure 1. Switching Rates Definition
En

50 %
t

IOUT
90 %
10 %

t
CLK

tD(OFF) tOFF

tD(ON) t(ON)

50 %
t

IOUT

t
tDCLK

Figure 2. Minimum Timing Definition

CLOCK
tCLK

CLOCK

tCLK

Logic Inputs

tS

tH

RESET

tR

tRCLK

7/15

L6208
Figure 3. Typical Quiescent Current vs. Supply
Voltage

Figure 6. Typical High-Side RDS(ON) vs.

Supply Voltage

Iq [mA]

RDS(ON) []

5.6

fc = 1kHz

0.380

Tj = 25C

0.376

Tj = 85C

5.4

0.372

Tj = 25C

0.368

Tj = 125C

0.364

5.2

0.360
0.356

5.0

0.352
0.348

4.8

0.344
0.340
0.336

4.6
0

10

20

30
V S [V]

40

50

60

10

15

20

25

30

V S [V]

Figure 7. Normalized RDS(ON) vs.Junction

Temperature (typical value)

Figure 4. Normalized Typical Quiescent

Current vs. Switching Frequency

R DS(ON) / (RD S(ON) @ 25 C)

Iq / (Iq @ 1 kHz)

1.7

1.8

1.6
1.6

1.5
1.4

1.4

1.3
1.2

1.2
1.1

1.0

1.0
0.8

0.9
0

20

40

60

80

100

20

40

60

80

100

120

140

Tj [C]

fSW [kHz]

Figure 5. Typical Low-Side RDS(ON) vs. Supply

Voltage

Figure 8. Typical Drain-Source Diode Forward

ON Characteristic

RDS(ON) []

ISD [A]

0.300

3.0

0.296

2.5

Tj = 25C
Tj = 25C

0.292

2.0

0.288

1.5

0.284

1.0

0.280

0.5
0.0

0.276
0

8/15

10

15
V S [V]

20

25

30

700

800

900

1000
VSD [mV]

1100

1200

1300

L6208
CIRCUIT DESCRIPTION
The L6208 is a fully integrated bipolar stepper motor driver with two full bridge having power DMOS with a typical
RDSON of 0.3 each. All the circuitry to implement the phase generation (decoding logic) is integrated, as well
as a constant Toff PWM control for the current, separately for any of the two winding of the driven motor.
The decoding logic generates three different sequences, selected by the HALF/FULL input. These are normal
(two phases ), wave drive (one phase energized) and half-step (alternately one phase/two phases energized).
The decoding logic generates three different sequences, selected by the HALF/FULL input. These are normal
(two phases energized), wave drive (one phase energized) and half-step (alternately one phase/two phases energized).
The constant Toff PWM current control consists in a sense comparator and a monostable.
When the current in each phase of the motor reaches the value set by the correspondent Vref voltage (Vref / RSENSE),
it will be forced to decrease for a constant Toff time, set by the RC network applied to the RC
A and RCB pins. If the
Control pin is at a High logic level, during the off-time the voltage applied to the motor phase will be approx. 0 V, turning
on the high-side MOSFETs of the bridge (slow decay recirculation ); if control is Low, instead, the voltage applied to
the phase will be reversed, turning off the low side MOSFET that was on and turning on the opposite low-side (fast
decay recirculation ).

Figure 9.
VS

VS

VS

On Time

Off Time in
Slow-Decay Recirculation

Off Time in
Fast-Decay Recirculation

Figure 10. PWM Chopping Current Control

IOUT
TON
Vref / RSENSE
Threshold

TOFF

(Recirculation)

9/15

L6208
A non-dissipative current sensing on the high side power DMOSs, an internal reference and an internal open
drain, with a pull down capability of 4mA (typical value), that goes LOW under fault conditions, ensure a protection against short circuit to GND or between two phases of each of the two full bridges. The trip point of this
protection is internally set at 5.6 A (typ. value). By using an external R-C on the EN pins, the off time before
recover normal operation conditions after a fault can be easily programmed, by means of the accurate threshold
of the logic inputs. Note that protection against short to the supply rail is typically provided by the PWM current
control circuitry.
These features make the L6208 a complete bipolar stepper motor driver that outperforms the components currently available on the market

MOTOR DRIVING PHASE SEQUENCE

The decoding logic integrated in the L6208 generates the sequences for normal drive, wave drive and half step
modes. The state machine sequences and the output currents (neglecting, for simplicity, the PWM control) are
shown below, in the case of clockwise rotation. For counterclockwise rotation the sequences are simply reversed. The state machine advances on the rising edge of the Clock signal, and a Low logic level on the Reset
input restores the logic to state 1.
HALF STEP MODE
Half step mode is selected by a high logic level on the HALF/FULL pin.

Figure 11.
IOUT1A

IOUT2A
3

IOUT1B

7
IOUT2B

Clock

10/15

L6208
NORMAL DRIVE MODE (Full-step two-phase-on)
Normal drive mode is selected by a Low level on the HALF/FULL input when the state machine is at an odd
numbered state.

Figure 12.
IOUT1A

IOUT2A
3

IOUT1B

7
IOUT2B

Clock

WAVE DRIVE MODE (Full-step one-phase-on)

Wave drive mode is selected by a Low level on the HALF/FULL input when the state machine is at an even
numbered state.

Figure 13.
IOUT1A

5
IOUT2A

6
IOUT1B

7
IOUT2B

Clock

11/15

L6208

mm

DIM.
MIN.

TYP.

A
A1

inch
MAX.

MIN.

TYP.

0.170

4.320
0.380

A2

0.015
3.300

0.130

0.410

0.460

0.510

0.016

0.018

0.020

B1

1.400

1.520

1.650

0.055

0.060

0.065

0.200

0.250

0.300

0.008

0.010

0.012

31.62

31.75

31.88

1.245

1.250

1.255

7.620

8.260

0.300

e
E1

2.54
6.350

6.600

3.180

0.325
0.100

6.860

0.250

0.260

0.270

0.300

7.620

e1

OUTLINE AND
MECHANICAL DATA

MAX.

3.430

0.125

0.135

Powerdip 24

0 min, 15 max.

E1

A2

A1

L
B

B1

e1

24

13
c

12
M
SDIP24L

12/15

L6208

mm

DIM.
MIN.

TYP.

inch
MAX.

MIN.

TYP.

MAX.

2.35

2.65

0.093

0.104

A1

0.10

0.30

0.004

0.012

A2

2.55

0.100

0.33

0.51

0.013

0.0200

0.23

0.32

0.009

0.013

15.20

15.60

0.598

0.614

7.40

7.60

0.291

0.299

1.27

0,050

10.0

10.65

0.394

0.419

0.25

0.75

0.010

0.030

OUTLINE AND
MECHANICAL DATA

0 (min.), 8 (max.)

0.40

1.27

0.016

SO24
0.050

0.10mm

A2

h x 45

A1

A1

.004

Seating Plane

13

12

24

SO24

13/15

L6208

DIM.
A
a1
a2
a3
b
c
D (1)
D1
E
e
e3
E1 (1)
E2
E3
E4
G
H
h
L
N
S

MIN.

mm
TYP.

0.10
0
0.22
0.23
15.80
9.40
13.90

MAX.
3.60
0.30
3.30
0.10
0.38
0.32
16.00
9.80
14.50

inch
TYP.

MIN.
0.004
0
0.008
0.009
0.622
0.370
0.547

0.65
11.05
10.90

0.0256
0.435
11.10 0.429
2.90
6.20 0.228
3.20 0.114
0.10
0
15.90 0.610
1.10
1.10 0.031
10(max.)
8 (max.)

5.80
2.90
0
15.50
0.80

OUTLINE AND
MECHANICAL DATA

MAX.
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570

0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043

PowerSO36

(1): D and E1 do not include mold flash or protrusions

- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are a3, E and G.

N
a2
e

A
DETAIL A

c
a1

DETAIL B

e3
H

DETAIL A

lead

D
slug

a3
36

BOTTOM VIEW

19

E3
B
E1

E2

D1

DETAIL B
0.35

Gage Plane

-C-

S
h x 45

14/15

0.12

SEATING PLANE
G

AB

PSO36MEC

(COPLANARITY)

L6208

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2001 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain
- Sweden - Switzerland - United Kingdom - U.S.A.
http:/ /www.st.com

15/15

This datasheet has been downloaded from:

www.DatasheetCatalog.com
Datasheets for electronic components.