The document describes the specifications of an ESA 86/88-2 Microprocessor trainer kit, including its 80286 CPU, 128KB each of EPROM and RAM memory, 8255 and 8253 peripherals, and interfaces for parallel and serial I/O. The trainer kit is used to study the architecture and instruction set of the 8086/8088 microprocessor.
The document describes the specifications of an ESA 86/88-2 Microprocessor trainer kit, including its 80286 CPU, 128KB each of EPROM and RAM memory, 8255 and 8253 peripherals, and interfaces for parallel and serial I/O. The trainer kit is used to study the architecture and instruction set of the 8086/8088 microprocessor.
The document describes the specifications of an ESA 86/88-2 Microprocessor trainer kit, including its 80286 CPU, 128KB each of EPROM and RAM memory, 8255 and 8253 peripherals, and interfaces for parallel and serial I/O. The trainer kit is used to study the architecture and instruction set of the 8086/8088 microprocessor.
The document describes the specifications of an ESA 86/88-2 Microprocessor trainer kit, including its 80286 CPU, 128KB each of EPROM and RAM memory, 8255 and 8253 peripherals, and interfaces for parallel and serial I/O. The trainer kit is used to study the architecture and instruction set of the 8086/8088 microprocessor.
Aim: To study the ESA 86/88-2 Microprocessor trainer kit Apparatus required: ESA 86/88-2 Microprocessor trainer kit and its User manual
Specifications: CPU: 8086/8088 CPU @ 5MHz (Supplied with 8086 CPU). The Processor is configured in maximum mode. CO PROCESSOR: 8087 Numeric Data Processor (optional) MEMORY: 8 JEDEC sockets provide the following memory configuration: EPROM: 128K bytes of system firmware using 27256s. (32K X 4) RAM: 128K bytes using 62256 (32K X 4) Memory Map PROM System Application: F8000 FFFFF H User Expansion: F0000 F7FFF H SRAM Supplied with Kit: 00000 0FFFF H Available for User Expansion: 10000 1FFFF H PERIPHERALS: 8255: PPI, Two Nos, Each 24 I/O lines. I/O Addresses: FFE7, FFE1, FFE3, FFE5 (High Port) and FFE6, FFE0, FFE2, FFE4 (Low Port) 8253: PIT, (Three16 bit programmable timers). Timer0 is used for baud clock. Timer1 and Timer2 are available for user I/O Addresses: FFFF, FFF9, FFFB, FFFD (Continued in page no: 6) SSN EC / BE ECE / V / EC6513: Microprocessor and Microcontroller Lab
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Fig. 1. 8086 in Maximum Mode Generation of System Bus Signals
Fig. 2. ESA 86/88-2 in Trainer Kit
SSN EC / BE ECE / V / EC6513: Microprocessor and Microcontroller Lab
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Table-1 Hexadecimal keypad legend Interpretation
Hexadecimal Key
Command Acronym
Name
Register Acronym
Name
0 EB / AX
EB
Examine Byte
AX
Accumulator
1 ER / BX
ER
Examine Register
BX
Base Register
2 GO / CX
GO
Go
CX
Count Register
3 ST / DX
ST
Single Step
DX
Data Register
4 IB / SP
IB
Input Byte
SP
Stack Pointer
5 OB / BP
OB
Output Byte
BP
Base Pointer
6 MV / SI
MV
Move
SI
Source Index
7 EW / DI
EW
Examine Word
DI
Source Index
8 IW / CS
IW
Input Word
CS
Code Segment
9 OW / DS
OW
Output Word
DS
Data Segment
A / SS
SS
Stack Segment
B / ES
ES
Extra Segment
C / IP
IP
Instruction Pointer
FL
Flag Register
D / FL
EB
Examine Byte
E F
SSN EC / BE ECE / V / EC6513: Microprocessor and Microcontroller Lab
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Table-2 Function Key Operation
Function Key RESET
Operation The RESET key allows the user to terminate any present activity and to return the kit to an initialized state. When pressed, a sign-on message appears in the display and the kit is ready for a command entry
KB / INT
The KB/INT key is used to generate an immediate, non-maskable
type 2 interrupt
The + (plus) key allows the user to add two hexadecimal values.
The - (minus) key allows the user to subtract one hexadecimal value from another.
The : (colon) key is used to separate an address to be entered in
two parts; a segment value and an offset value.
REG
The REG key allows the user to use the contents of any of the Processors registers as an address or data value.
NEXT (,)
The NEXT key is used to separate keypad entries and to increment
the address field to the next consecutive memory locations
PREV
The PREV key is used to decrement the address field to previous
memory location
EXEC (.)
The dot key is the command terminator. When pressed, the current command is executed.
SSN EC / BE ECE / V / EC6513: Microprocessor and Microcontroller Lab
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Table-3 Summary of Monitor Commands
Command Group Examine / Modify
Command Examine Byte
Function / Format Displays / modifies memory byte locations
address> Note: [X] Indicates a keyboard key; [V] Indicates V is optional; [V]* - Indicates one or more optional occurrences of V; <V> - Indicates that V is a parameter to be entered by the user.
SSN EC / BE ECE / V / EC6513: Microprocessor and Microcontroller Lab
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8251: Programmable communication interface for serial communication supporting
all standard baud rates from 110 to 19200 I/O Addresses: FFF2 (Command / Status port) and FFF0 (Data port) 8259: Programmable interrupt controller provides interrupt vectors for 8 sources I/O Addresses: FFF4 (Command / Status port) and FFF6 (Data port) 8279: Keyboard / Display controller Interfaces 4*8 matrix keyboard and 8-digit LED display I/O Addresses: FFEB (Command / Status port) and FFE9 (Data port) 8288: Bus-controller used to generate control signals 8284: Clock-generator used to generate clock for processor and associated peripherals INTERRUPTS External: NMI connected to INTR key switch of keyboard. INTR controlled by 8259A PIC for 8 sources. (8251 TXRDY & RxRDY; 8253 Out1 & Out2; 8255 PC0 & PC3 in Handshake mode) Internal: Interrupt Vectors 1 (single step) and 3 (breakpoint) reserved for monitor. INTERFACING SIGNALS: CPU Bus: De-multiplexed and fully buffered, TTL compatible, Address, Data & Control signals are available on two 50-pin ribbon cable connectors. Parallel I/O: 48 programmable parallel I/O lines (TTL compatible) through two 26 pin ribbon cable connectors. Serial I/O: RS 232C through on-board 9-pin D-type female connector. POWER SUPPLY REQUIREMENT: +5V @ 3A (max) RESULT:
SSN EC / BE ECE / V / EC6513: Microprocessor and Microcontroller Lab
PPI 8255 is a general purpose programmable IO device designed to interface the CPU with its outside world such as ADC, DAC, keyboard etc. We can program it according to the given condition. It can
PPI 8255 is a general purpose programmable IO device designed to interface the CPU with its outside world such as ADC, DAC, keyboard etc. We can program it according to the given condition. It can
