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CS 2202 - Digital Principles and Systems Design PDF

This document contains questions that appear to be from a digital principles and systems design exam. It includes 15 multiple choice and short answer questions covering topics like: 1) Code conversions between binary, octal, hexadecimal 2) Representing signed binary numbers 3) Designing full adders and decoders using logic gates 4) Differences between PAL and PLA 5) Hazards in combinational circuits 6) Boolean algebra simplification using K-maps 7) Designing binary multipliers and understanding carry propagation 8) Implementing decoders and multiplexers using logic gates 9) Describing read operations in RAM and designing MOD 16 up counters 10) Explaining state reduction, assignment and race

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velkarthi92
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© Attribution Non-Commercial (BY-NC)
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188 views3 pages

CS 2202 - Digital Principles and Systems Design PDF

This document contains questions that appear to be from a digital principles and systems design exam. It includes 15 multiple choice and short answer questions covering topics like: 1) Code conversions between binary, octal, hexadecimal 2) Representing signed binary numbers 3) Designing full adders and decoders using logic gates 4) Differences between PAL and PLA 5) Hazards in combinational circuits 6) Boolean algebra simplification using K-maps 7) Designing binary multipliers and understanding carry propagation 8) Implementing decoders and multiplexers using logic gates 9) Describing read operations in RAM and designing MOD 16 up counters 10) Explaining state reduction, assignment and race

Uploaded by

velkarthi92
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Reg. No.

Question Paper Code :

55293

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011. Third Semester

Computer Science and Engineering

CS 2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN (Common to Information Technology) (Regulation 2008) Time : Three hours

PART A (10 2 = 20 marks) 1. Perform the following code conversions:


(1010 .10 )16 (?)2 (?)8 (?)10

2. 3. 4. 5. 6. 7. 8.

State the different ways for representing the signed binary numbers. With block diagram show how a full adder can be designed by using two half adders and one OR gate. List the modeling techniques available in HDL. Define decoder. Draw the block diagram and truth table for 2 to 4 decoder. What is the difference between Programmable array logic (PAL) and Programmable logic array (PLA)? How many flip flops are required for designing synchronous MOD60 counter? Write down the characteristic equation for JK and T flip flops. What is meant by Race condition in Asynchronous sequential circuit?

9.

10.

Define Hazard. List the Hazards in combinational circuit.

21

21

Answer ALL questions.

4 21
Maximum : 100 marks

PART B (5 16 = 80 marks) 11. (a) Simplify the following Boolean function F using Karnaugh map method: (i) (ii) (iii) (iv) F(A, B, C, D)= F(A, B, C, D) = F(A, B, C, D) =
(1,4,5,6,12,14,15)

(4) (4) (4)

(0,1,2,4,5,7,11,15)
(2,3,10,11,12,13,14,15)

F(A, B, C, D) = (0,2,4,5,6,7,8,10,13,15) Or

(b)

simplify the following Boolean expressions to a minimum number of literals: (i) (ii) (iii) (iv) (v)
AC + ABC + A C

XYZ + X Y + XY Z XY + YZ + X Y Z
A B + ABD + AB D + A C D + A B C BD + BC D + A B C D

12.

(a)

Consider the combinational circuit shown in Figure 1. (i) (ii) Derive the Boolean expressions for T 1 through T4. Evaluate the outputs F1 and F2 as a function of the four inputs. (4)

List the truth table with 16 binary combinations of the four input variables. Then list the binary values for T1 through T4 and outputs F1 and F2 in the table. Plot the output Boolean function obtained in part (ii) on maps and show that simplified Boolean expressions are equivalent to the ones obtained in Part (i)

21

4 21
(4) (2) (2) (2) (5) (5) (4) (8) (8) (8)

(iii)

21 4
(b) (i) (ii)

Figure 1. Or

With suitable block diagram explain Binary multiplier.

Write a detailed note on carry propagation. 2

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13.

(a)

Construct a 5 to 32 line decoder with four 3 to 8 line decoders with enable and a 2 to 4 line decoder. Use block diagrams for components.(16) Or

(b)

(i) Implement the following Boolean function with 16 1 multiplexer :

Use block diagram representation. (ii) (iii) 14. (a)

Write HDL gate level description for 3 to 8 line decoder.

With suitable timing diagram explain how Read operation is performed in Random access memory. (6) (16)

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(6) (4) (16) (16)

F ( A , B , C , D ) = (0 , 1, 3, 4 , 8 , 9 ,15 ) ,

[6] [16]

Design a MOD 16 up counter using JK Flip flops. Or

(b) 15. (a)

With suitable example explain state reduction and state assignment.(16) Write a detailed note on Race free state assignment. Or [16]

(b)

With suitable design example, explain ASM Chart.

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16J

4
3

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4
55293

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