An Optimum PWM Strategy for 5-Level Active NPC (ANPC) Converter Based on Real-time Solution for THD Minimization

Jun Li
Student Member, IEEE jli2@ncsu.edu

Yu Liu

Subhashish Bhattacharya

Alex Q. Huang
Fellow, IEEE aqhuang@ncsu.edu

Student Member, IEEE Member, IEEE yliu8@ncsu.edu sbhattacharya@ncsu.edu FREEDM Systems Center North Carolina State University Raleigh, NC, USA

Abstract -- The recently introduced active NPC (ANPC) converter is becoming an attractive topology of multilevel converter family. This paper presents the analysis of the 5-level ANPC converter with an optimum PWM strategy to achieve the minimized total harmonic distortion (THD) for high power or high frequency applications. Instead of relying on the conventional look-up table based on off-line calculated solutions, the switching angles of the optimum PWM are calculated through a real-time algorithm, which is time-efficient and therefore easy to implement in real-time by digital processors. The control scheme of balancing the floating capacitors voltages is also proposed. Simulation results verify the performance of the proposed strategies. Index TermsMultilevel converters, active NPC, optimum PWM, minimized THD, real-time, floating capacitor balancing.

minimized THD. Instead of relying on conventional look-up table scheme based on off-line calculated solutions, the switching angles of the optimum PWM are calculated by a real-time algorithm, which is time-efficient and therefore easy to implement in real-time by digital processors. This paper also proposes the method of maintaining the balance of the floating capacitors voltages. The principles of selecting the redundant switching states are discussed. Simulation results prove the correctness of the proposed methods. II. OPTIMUM PWM FOR 5-LEVEL ACTIVE NPC CONVERTER

I. INTRODUCTION As a new configuration of multilevel converter family, active neutral-point-clamped (ANPC) converter was firstly introduced in [1]. Derived from traditional NPC topology, it replaces the clamping diodes with active switches in order to achieve balanced losses distribution among the semiconductor devices, and thus increases the converter output power rating or switching frequency. The recent development of ANPC converter topologies has been presented in [2-5], which are mainly based on the hybrid concept to combine different two-level and multilevel converter topologies for performance improvement. Pulse-width-modulation (PWM) methods for multilevel converters have been extensively studied in literatures [6]. Among various PWM schemes, SHEPWM and optimum PWM are two effective solutions to restrict the switching losses in high power or high frequency applications, such as MVDC/HVDC systems, medium/high power rating DSTATCOM, high voltage high frequency plasma systems and high speed wind turbine generator drive [7-9]. Different from SHEPWM, which aims to fully eliminate certain low-orders harmonics, optimum PWM leaves a small amount of each harmonics, but minimizes the total harmonic distortion (THD) while realizing the proper fundamental component of voltage. This paper presents the analysis of the single-phase 5-level ANPC converter with optimum PWM strategy to achieve

The 5-level ANPC topology is the combination of flying capacitor and 3-level ANPC converter topologies. The halfbridge and full-bridge configuration of a single-phase 5-level ANPC converter are shown in Fig. 1(a) and Fig. 1(b) respectively.

(a)

Half-bridge 5-level ANPC converter

(b) Full-bridge 5-level ANPC converter Fig. 1. Configuration of single-phase 5-level ANPC converter

978-1-4244-2893-9/09/$25.00 2009 IEEE

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Fig. 2 shows the output voltage waveforms of the 5-level ANPC converter with the optimum PWM strategy.

THD is an important indices to quantify the waveform quality, and it is defined as:

2 2 THD = Vn /V1 n =3,5, 7...

(4)

(a) Output voltage of half-bridge configuration

(b) Output voltage of full-bridge configuration Fig. 2. Output voltage waveforms of a single-phase 5-level ANPC converter with optimum PWM strategy

In this paper, our goal is to implement optimum PWM for single-phase 5-level ANPC converter to achieve minimum THD while realizing the proper fundamental component of voltage by choosing a proper set of switching angles. To get the solutions of switching angles, the conventional methods usually need to solve non-linear and transcendental equation sets using Newton-Raphson iteration, symmetric polynomials and resultants, and so on [10-11]. These methods are based on off-line calculations and require storing the solutions in look-up table, which is very time-consuming and difficult to be implemented in real-time by digital processors. To overcome this drawback, a real-time algorithm to calculate the switching angles was previously presented and applied for cascaded multilevel converter [12]. Instead of repeating the derivation in detail, we only give the main calculation steps here: Step1: determine variable by solving equation (5) with Newton-Raphson iteration:

For a generalized derivation, we assume that using the optimum PWM, the output voltage waveform of the multilevel ANPC converter is similar to Fig. 2, and the number of the independent switching angles is s, which corresponds to 2s+1 output voltage levels. For the case of a single-phase 5-level ANPC converter, the s equals to 2 and 4 for half-bridge and full-bridge configuration respectively, and the voltage level number is 5 and 9 accordingly. In Fourier series form, the voltage waveform of the ANPC converter with optimum PWM is expressed by:

k =1

1 (

k 1/ 2 )2 = m s s 1/ 2

(5)

Step2: determine the switching angles by:

k = arcsin(

k 1/ 2 ), k = 1,2..., s s 1/ 2

(6)

V ( ) =

n =1,3,5...

sin (n )

(1)

If the initial value is chosen properly, one iteration is enough to get the sufficiently accurate value of . The total computational complexity of the algorithm is:

Here, n is the odd harmonic order, and Vn is the amplitude of nth order harmonic voltage and is given by:

Tsolve = (3 + 2 s ) Tmultiplica tion + Trootsquare + ( s + 1) Tdivision + s T arcsin

(7)

Vn =

4U s cos(nai ) n i =1
( 0 a1 a 2

(2)

Here, U is the height of voltage step, and i is the ith independent switching angle as shown in Fig. 2. The modulation index m is defined as: V1 , (3) ( 0 m 1) m= 4 s U Here, V 1 is the amplitude of the fundamental component voltage. The range of m is from 0 to 1.

as ) 2

Where Tmultiplication, Trootsquare, Tdivision, and Tarcsin are the time costs of multiplication, root square, division, and arcsin operations respectively. For full-bridge structure in Fig. 2(b), s is 4, and the computation only need 11 multiplications, 1 root square, 5 division and 4 arcsin operations to find the switching angle solution for 1 ~ 4, which is easy to implement in real-time using the digital processor, such as DSP or FPGA. For halfbridge structure in Fig. 2 (a), Newton-Raphson iteration is even unnecessary since only 2 angles need to be calculated. Instead, we can firstly calculate the variable h by (8), and then calculate switching angles a1 and a 2 by (9).

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h=

9m 4 + 16m 2 5m 2 ) / 2

(8) (9)

1 = arcsin(h / 2) 2 = arcsin(3h / 2)
IV. FLOATING CAPACITOR VOLTAGES CONTROL

The relation of switching states, output voltage and their effect on the floating capacitors of the 5-level ANPC converter is shown in Table I and II for half-bridge and fullbridge configuration, respectively. To maintain the balance of the floating capacitors voltages is very important for the normal operation of the 5-level ANPC converter [2].
TABLE I. Switching states, output voltage and their effect on floating capacitor voltage of half-bridge 5-level ANPC converter Cell3 Cell2 Cell1 Output S8 S7 S6 S5 S4 S3 S2 S1 Voltage 0 1 0 1 0 1 0 1 Vdc 0 1 0 1 0 1 1 0 Vdc/2 0 1 0 1 1 0 0 1 Vdc/2 0 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 -Vdc/2 1 0 1 0 1 0 0 1 -Vdc/2 1 0 1 0 1 0 1 0 -Vdc Effect on Cf I>0 I<0 n/a n/a + + n/a n/a n/a n/a + + n/a n/a Switching State V1 V2 V3 V4 V5 V6 V7 V8

In half-bridge configuration of 5-level ANPC converter, according to Table I, floating capacitor voltage VCf can be affected by 4 switching states: V2/V3 and V6/V7. V2 and V3 have opposite effect on VCf when output voltage level is Vdc/2, therefore, they can be used to control the balance of VCf. The conclusion is also valid for V6 and V7 when output voltage level is Vdc/2. Table III provides the method to choose the proper switching state to charge or discharge the floating capacitor Cf based on the voltage status of Cf and the converter output current direction.
TABLE III. System states and the chosen switching states for controlling the balance of VCf Output System states Selected Voltage switching state Vdc/2 (VCf -Vdc/2) I>0 (VCf -Vdc/2) I<0 (VCf -Vdc/2) I>0 (VCf -Vdc/2) I<0 V3 V2 V7 V6

-Vdc/2

Compared with half-bridge topology, the full-bridge 5level ANPC converter has a large amount of switching states redundancy, as shown in Table II, which means there are more choices and flexibility to control the two floating capacitor voltages VCf1 and VCf2 in the similar way as halfbridge topology. However, there are two points need to be noticed:

Here, +, -and n/a represent charging, discharging, and no effect respectively. TABLE II. Switching states, output voltage and their effect on floating capacitors voltages of full-bridge 5-level ANPC converter Switching state Phase-A Phase-B V1 V8 V1 V6 V1 V7 V2 V8 V3 V8 V1 V4/V5 V2 V6 V2 V7 V3 V6 V3 V7 V4/V5 V8 V1 V2 V1 V3 V2 V4/V5 V3 V4/V5 V4/V5 V6 V4/V5 V7 V6 V8 V7 V8 V1 V1 V2 V2 V2 V3 V3 V2 V3 V3 Vab 2Vdc 3Vdc/2 3Vdc/2 3Vdc/2 3Vdc/2 Vdc Vdc Vdc Vdc Vdc Vdc Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 Vdc/2 0 0 0 0 0 Effect on Cf1 I>0 I<0 n/a n/a n/a n/a n/a n/a + + n/a n/a + + + + n/a n/a n/a n/a n/a n/a + + n/a n/a n/a n/a + + n/a n/a + + + + Effect on Cf2 I>0 I<0 n/a n/a + + n/a n/a n/a n/a n/a n/a + + + + n/a n/a + + n/a n/a n/a n/a + + n/a n/a n/a n/a n/a n/a + + + + Switching state Phase-A Phase-B V4/V5 V4/V5 V6 V6 V6 V7 V7 V6 V7 V7 V8 V8 V2 V1 V3 V1 V4/V5 V2 V4/V5 V3 V6 V4/V5 V7 V4/V5 V8 V6 V8 V7 V4/V5 V1 V6 V2 V6 V3 V7 V2 V7 V3 V8 V4/V5 V6 V1 V7 V1 V8 V2 V8 V3 V8 V1 Vab 0 0 0 0 0 0 -Vdc/2 -Vdc/2 -Vdc/2 -Vdc/2 -Vdc/2 -Vdc/2 -Vdc/2 -Vdc/2 -Vdc -Vdc -Vdc -Vdc -Vdc -Vdc -3Vdc/2 -3Vdc/2 -3Vdc/2 -3Vdc/2 -2Vdc Effect on Cf1 I>0 I<0 n/a n/a + + + + n/a n/a + + n/a n/a n/a n/a + + n/a n/a n/a n/a n/a n/a + + + + n/a n/a + + n/a n/a n/a n/a n/a n/a Effect on Cf2 I>0 I<0 n/a n/a + + + + n/a n/a n/a n/a n/a n/a + + n/a n/a n/a n/a + + n/a n/a + + + + n/a n/a n/a n/a n/a n/a + + n/a n/a

Here, +, -and n/a represent charging, discharging, and no effect respectively.

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1) When output voltage is Vdc or 0, by choosing a proper pair of switching states from Phase-A and B, the balance of both VCf1 and VCf2 can be controlled at the same time. However when output voltage is Vdc/2 or 3Vdc/2, only one floating capacitor voltage can be controlled with a selected pair of switching state. In this case, two schemes can be used for the voltage balance control: a) The first scheme is that the controller prioritizes the two capacitors, and then the more deviated capacitor is given a higher priority so that even if the selected switching state doesnt have effect on the other capacitor, the corrective action is still applied; b) The second scheme is that the controller always controls a certain capacitor voltage at the corresponding output voltage level. Considering the control simplicity, the latter scheme is chosen in this paper. The principle is: at Vdc/2 level, we control VCf1, and at 3Vdc/2, we control VCf2. 2) When output voltage is Vdc/2 or 0, there exist two pairs of switching states having the same effect on the floating capacitors voltages. In this paper, the one that causes less switching actions or helps to balance the devices losses is chosen. V. SIMULATION RESULTS

90 75 A ngles (degrees) 60 45 30 15 0 0.3 a1 a2

0.4

0.5 0.6 0.7 0.8 Modulation index (m)

0.9

(b) 3 harmonic elimination

0.3

0.4 0.5 0.6 0.7 0.8 Modulation index (m)

0.9

A ngles (degrees)

The single-phase 5-level ANPC converters with optimum PWM are simulated in Matlab to prove the correctness of the presented control method. Simulation parameters are shown in Table IV.
TABLE IV. Simulation parameters Half of the DC link voltage Vdc=2000 V Capacitance of the floating capacitors Load Fundamental frequency Cf=1 mF Inductive load ( 10 ohm resistor +10 mH inductor) 500 Hz

(c) 5 harmonic elimination (i)

0.3

A.

Half-bridge 5-level ANPC converter results For comparison, the presented method is compared with the other two SHEPWM methods: 3rd harmonic elimination and 5th harmonic elimination for single-phase half-bridge 5level ANPC converter. Firstly, the angles solutions of the three methods are shown in Fig. 3: (a) the presented real-time optimum PWM; (b) 3rd harmonic elimination; (c)-(d) 5th harmonic elimination.
90 75 a1 a2

0.4 0.5 0.6 0.7 0.8 Modulation index (m)

0.9

(d) 5 harmonic elimination (ii) Fig. 3. Angles solutions of the three methods

Fig. 4 shows the THD comparison of the three methods, where the modulation index range is chosen from 0.472 to 0.866 for a better survey. It can be seen that the presented optimum PWM with the real-time algorithm has the smallest THD compared with other methods.
0.6
3rd harm onic is zero

0.5 0.4 0.3 0.2

5th harm onic is zero presented PWM

Angles (degrees)

60 45 30 15 0 0.3

0.4

0.5

0.6

0.7

0.8

0.9

THD
Modulation index (m)

0.1

(a) Presented optimum PWM

0.5

0.6 0.7 0.8 Modulation index (m) Fig. 4. THD comparison

0.9

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Fig. 5 shows harmonic content comparison of the three methods. The presented optimum PWM in Fig. 5(a) has much lower 5th harmonic than Fig. 5 (b) and much less 3rd harmonic than Fig. 5 (c), which explains the main reason of the minimized THD of the presented method.
3rd 5th 7th 9th 11th 13th

Fig. 6 shows the voltage and current waveforms of halfbridge 5-level ANPC converter at modulation index m=0.8 with the proposed method. Fig. 6(a)-(c) are the converter output voltage, output current and floating capacitor voltage respectively. As seen, the floating capacitor voltage VCf is well balanced at 1000 V, and the current THD is 2.2%.

0.25

H r o icc n n a m n o te t

0.2

0.15

0.1

0.05

0.5

0.6

0.7

0.8

0.9

(a) Output voltage

Modulation index (m) (a) Presented optimum PWM

0.25

H r o icc n n a m n o te t

0.2

3rd 5th 7th 9th 11th 13th

0.15

0.1

(b) Output current

0.05

0.5

0.6

0.7

0.8

0.9

Modulation index (m) (b) 3rd harmonic elimination

0.25

H rm n c n n a o ic o te t

0.2

3rd 5th 7th 9th 11th 13th

0.15

(c) Floating capacitor voltage Fig. 6. Voltage and current waveforms of half-bridge 5-level ANPC converter with the presented optimum PWM at m=0.8

0.1

B.

0.05

0.5

0.6

0.7

0.8

0.9

Modulation index (m) (c) 5th harmonic elimination Fig. 5. Harmonic content comparison

Full-bridge 5-level ANPC converter results For comparison, the presented method is then compared with SHEPWM method which eliminates 5th, 7th, 11th harmonics for single-phase full-bridge 5-level ANPC converter. Firstly, the angles solution of the presented optimum PWM for minimized THD with real-time algorithm is drawn in Fig. 7.

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90 75 Angles (Degrees) 60 45 30 15

a1 a2 a3 a4

0 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 Modulation index (m)
Fig. 7. Angles solutions of the presented method

(b) Output current

The THD comparison result is drawn in Fig. 8. It shows that the THD of the presented method is much lower than the SHEPWM method. The minimum THD appears around modulation index m=0.84, which implies that the rated operation point of the converter should be designed around this value so as to achieve better voltage waveform during the rated operation.
0.3
5th,7th,11th are zero presented PWM

0.25

THD

0.2

(c) Floating capacitors voltages Fig. 9. Voltage and current waveforms of full-bridge 5-level ANPC converter with the presented optimum PWM at m=0.8

0.15

0.1

As seen from the simulation results, the optimum PWM with real-time switching angles calculation enables to achieve minimized THD for the output voltage of single-phase 5-level ANPC converter, and the floating capacitors voltages can be well regulated by using the proposed method.
0.69 0.74 0.79 0.84 0.89

0.05 0.64

Modulation index (m)

Fig. 9 shows the voltage and current waveforms of fullbridge 5-level ANPC converter at modulation index m=0.8 with the proposed method. Fig. 9(a)-(c) are the converter output voltage, output current and the two floating capacitors voltages respectively. Both VCf1 and VCf2 are well controlled, and current waveform THD is 0.56%.

VI. CONCLUSION This paper presents the analysis of the single-phase 5-level ANPC converter with optimum PWM to achieve the minimized THD for high power or high frequency applications. Instead of using look-up table with off-line calculated solutions to find the switching angles, a real-time algorithm is used, which is time-efficient and easy to implement in real-time by digital processors. The method of balancing the floating capacitors voltages is proposed, and the principles of selecting the redundant switching states are analyzed Simulation results verify the performance of the proposed strategies. ACKNOWLEDGMENT This work made use of ERC shared facilities supported by the National Science Foundation under Award Number EEC08212121.

(a) Output voltage

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