This document is an exam for an FPGA design course. It contains 8 questions covering various topics related to FPGA design including:
1. MOS device parameters and logic gate implementations for FPGAs.
2. FPGA fabric interconnects, I/O circuit design, and Xilinx CLB architecture.
3. Delay modeling, power optimization, and glitch power consumption.
4. Hazard detection and removal, and finite state machine design styles.
5. VHDL coding, clocking rules, and clock skewing compensation.
6. Floorplanning optimization problems.
7. Barrel shifter VHDL code and design methodologies/encoding
This document is an exam for an FPGA design course. It contains 8 questions covering various topics related to FPGA design including:
1. MOS device parameters and logic gate implementations for FPGAs.
2. FPGA fabric interconnects, I/O circuit design, and Xilinx CLB architecture.
3. Delay modeling, power optimization, and glitch power consumption.
4. Hazard detection and removal, and finite state machine design styles.
5. VHDL coding, clocking rules, and clock skewing compensation.
6. Floorplanning optimization problems.
7. Barrel shifter VHDL code and design methodologies/encoding
This document is an exam for an FPGA design course. It contains 8 questions covering various topics related to FPGA design including:
1. MOS device parameters and logic gate implementations for FPGAs.
2. FPGA fabric interconnects, I/O circuit design, and Xilinx CLB architecture.
3. Delay modeling, power optimization, and glitch power consumption.
4. Hazard detection and removal, and finite state machine design styles.
5. VHDL coding, clocking rules, and clock skewing compensation.
6. Floorplanning optimization problems.
7. Barrel shifter VHDL code and design methodologies/encoding
This document is an exam for an FPGA design course. It contains 8 questions covering various topics related to FPGA design including:
1. MOS device parameters and logic gate implementations for FPGAs.
2. FPGA fabric interconnects, I/O circuit design, and Xilinx CLB architecture.
3. Delay modeling, power optimization, and glitch power consumption.
4. Hazard detection and removal, and finite state machine design styles.
5. VHDL coding, clocking rules, and clock skewing compensation.
6. Floorplanning optimization problems.
7. Barrel shifter VHDL code and design methodologies/encoding
M S RAMAIAH INSTITUTE OF TECHNOLOGY (AUTONOMOUS INSTITUTE, AFFILIATED TO VTU) BANGALORE - 560 054
SEMESTER END EXAMINATIONS - JUNE 2010
Course & Branch : Subject : Subject Code : M.Tech ( Digital Electronics and Semester : II Communication) FPGA Based System Design Max. Marks : 100 MDLEC03
Duration . 3 Hrs
Instructions to the Candidates: Answer any Five Full questions.
1. a) List the critical parameters considered when MOS devices are (05) designed. b) Realize the switch level for the following (07) i) Unbuffered AND gate
ii) XOR Gate c) Explain how 2-D FPGA fabric interconnects work. (08) 2. a) Explain the I/O circuit design for an FPGA platform. List some of (10)
FPGAs applications. b) Explain Xilinx's CLB architecture.
(10)
3. a) Explain delay model of a combinational network. How is reduction of (10) critical path length done? b) Discuss how we can algorithmically optimize power. Explain how (10) glitches add to power consumption with an example. 4. a) For the circuits given, what are the hazards that are generated and (10) how can they be removed. CL
(i)
b) What are the different design styles for implementing FSMs? Give an (10)
Page 1 of 2
MDLEC03 example.
5.
a) b)
Write a VHDL code for detection of: 1011.
List the various clocking rules. What is clock skewing? How should it be compensated?
(10) (10)
6.
a)
Discuss the different optimization problems in floor planning.
(10)
b)
Write the VHDL code for 16-bit barrel shifter. Consider circular shifts either left or right. Explain the various design methodologies for implementing a design. Which are the different encoding techniques used? With an example justify it.
(10)
7.
a) b)
(10) (10)
8.
Write short notes: (4x5=20) i) Fine vs coarse grained architecture ii) Logic mapping in FPGAs iii) Partitioning for multi - FPGA system iv) Novel architecture using FPGAs. ***************
