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Metals
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Research on Green and Environmentally Friendly Lead-Free Solder and Advanced...
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Research on Green and Environmentally Friendly Lead-Free Solder and Advanced Interconnect Technology in Electronic Packaging

A special issue of Metals (ISSN 2075-4701). This special issue belongs to the section "Welding and Joining".

Deadline for manuscript submissions: closed (30 July 2024) | Viewed by 872

Special Issue Editor

Prof. Dr. Limin Ma

E-Mail Website
Guest Editor
Faculty of Materials and Manufacturing, Beijing University of Technology, Beijing, China
Interests: intermetallic compounds; reliabiliy; surface coating; electromigration; solder; thermoelectric generator; stacking packaging; through silicon via; interfacial diffusion

Special Issue Information

Dear Colleagues,

In the process of connecting microelectronics, the industry not only needs to prohibit the doping of harmful elements from the source, but also ensure the reliability of the connection. This requires researchers to propose new strategies in terms of connection technology, materials and structural design. Since the end of the 1990s, many researchers have attempted to improve the reliability of tin-based solder and to regulate the properties of intermetallic compounds to weaken the brittle tendency of solder joints, whether they are from the solder itself, the interface coating or external conditions. In addition, the reuse of solid waste resources of electronic products is also a new theme of green connection, and the design of electronic products should also consider the convenience of recycling. Methods of recovering valuable rare elements from electronic products is also an important issue.

Prof. Dr. Limin Ma
Guest Editor

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Keywords

  • intermetallic compounds
  • microelectronics connection
  • reliability
  • tin-based solder
  • electronic solid waste
  • recycling

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Published Papers (1 paper)

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Research

27 pages, 30719 KiB  
Article
The Effect of Multiple Solder Reflows on the Formation of Cu6Sn5 Intermetallics and the Decomposition of SnAg3.0Cu0.5 Solder Joints in the Framework of Rework and Reuse of MLCC Components
by Erik Wiss and Steffen Wiese
Metals 2024, 14(9), 986; https://doi.org/10.3390/met14090986 - 29 Aug 2024
Viewed by 430
Abstract
A rework of electronic assemblies and the reuse of electronic components are the most effective ways to reduce electronic waste. Since neither components nor substrates were developed with the intention of multiple usage, the question of how the integrity of lead-free solder joints [...] Read more.
A rework of electronic assemblies and the reuse of electronic components are the most effective ways to reduce electronic waste. Since neither components nor substrates were developed with the intention of multiple usage, the question of how the integrity of lead-free solder joints is affected by multiple reflow operations is crucial for the implementation of any reuse strategy. Therefore, various types of 1206 multilayer ceramic capacitors (MLCCs) differing in their capacitance value and dielectric type (X5R, X7R, Y5V, NP0) were soldered on test printed circuit boards (PCBs) having a pure Cu-metallization surface in order to investigate the intermetallic reactions during multiple reflows. The metallization system on the MLCC-component side consisted of a thick film of Ni covered by galvanic-deposited Sn. The reflow experiments were conducted using a hypoeutectic SnAgCu solder. The results show the formation of a Cu6Sn5 intermetallic phase on both metallizations, which grows homogeneously with the number of reflows. Moreover, an ongoing decomposition of the solder into Ag-enriched and depleted zones was observed. The effect of these microstructural changes on the functionality of the solder joint was investigated by mechanical shear experiments and electrical four-point capacitance measurements. Full article
(This article belongs to the Special Issue Research on Green and Environmentally Friendly Lead-Free Solder and Advanced Interconnect Technology in Electronic Packaging)
►▼ Show Figures

Figure 1

Figure 1
<p>Layout of the electrical test-board (length 160 mm and width 100 mm) having a capacity to carry eight samples (C1–C8, solder pad layout for MLCC with 1206 size). Each pair of the MLCC soldering pads is connected to four pads on the right edge of the PCB to enable precise four-wire measurements of the MLCC’s capacitances.</p> Full article ">Figure 2
<p>Layout of a test-PCB for the samples that were subjected to a shear test. The pads are connected to two additional pads on the left side of the PCB to allow in-situ monitoring of the solder joint health state during the mechanical test. The three holes in the middle are used to align and attach the samples to the holder of the testing machine.</p> Full article ">Figure 3
<p>Time-temperature curve of the reflow profile that was used for the experiments. The graph summarizes the recordings of the subsequent reflow process in a typical and idealized form (without noise). Every reflow process had an identical profile. The reflow soldering has been carried out in a batch reflow oven, ProtoFlow S (LPKF), using a nitrogen-protective atmosphere.</p> Full article ">Figure 4
<p>Specially developed measurement adapter that is connected to the measurement device via four BNC connectors, which bring the shielded measurement connections to the adapter. These measurement connections are redistributed by the PCB to four pin heads, whose grid exactly matches one of the Cu pads. After the pin heads have been brought into contact with the pads, the measurement is initiated (manual trigger).</p> Full article ">Figure 5
<p>Equivalent circuit diagram of a real capacitor, consisting of a series resistance R<sub>s</sub>, a series inductance L<sub>s</sub>, a parallel resistance R<sub>p,</sub> and the capacitance C, adapted from [<a href="#B27-metals-14-00986" class="html-bibr">27</a>].</p> Full article ">Figure 6
<p>Overview of the mechanical test setup presented in [<a href="#B29-metals-14-00986" class="html-bibr">29</a>,<a href="#B30-metals-14-00986" class="html-bibr">30</a>]. The main components of the setup are labeled as follows: A: Actuator. B: Three-axis force sensor. C: Measurement amplifiers (for force sensors). D: Stereo zoom microscope with illumination units. E: Crack detection circuit.</p> Full article ">Figure 7
<p>Detailed view of the experimental setup. The displacement of the actuator and thus a force are transferred to the resistor via a small PCB, which is electrically isolated to not influence the electrical measurement. A crack formation within one of the solder joints results in an interruption of the electrical pathway between the two wires on the left side, which are connected to the crack detection circuit.</p> Full article ">Figure 8
<p>Light microscopy image of an X7R MLCC (Magnification: 5×). The red box between the MLCC and the Cu pad marks the location of the SEM and EDX analysis. A: PCB base material. B: Cu pad of the PCB. C: Solder joint. D: Cu metallization and Ni termination. E: MLCC ceramic body. F: Inner electrodes.</p> Full article ">Figure 9
<p>SEM images in SE mode with an enlarged view of the red box area of <a href="#metals-14-00986-f008" class="html-fig">Figure 8</a>. Path along which the line scans were performed after the (<b>a</b>) first, (<b>b</b>) second, (<b>c</b>) fourth, and (<b>d</b>) eighth reflow cycles, starting within the Ni-thick film layer (termination) of the MLCC and ending in the Cu metallization of the PCB.</p> Full article ">Figure 10
<p>EDX analysis of an X7R MLCC after the first reflow cycle with a magnification of 4000×. (<b>a</b>) SEM image in SE mode. (<b>b</b>) Combined EDX maps of Ni, Cu, Ag, and Sn. (<b>c</b>) EDX map of Ni. (<b>d</b>) EDX map of Cu. (<b>e</b>) EDX map of Ag. (<b>f</b>) EDX map of Sn.</p> Full article ">Figure 11
<p>EDX analysis of an X7R MLCC after the second reflow cycle with a magnification of 4000×. (<b>a</b>) SEM image in SE mode. (<b>b</b>) Combined EDX maps of Ni, Cu, Ag, and Sn. (<b>c</b>) EDX map of Ni. (<b>d</b>) EDX map of Cu. (<b>e</b>) EDX map of Ag. (<b>f</b>) EDX map of Sn.</p> Full article ">Figure 12
<p>EDX analysis of an X7R MLCC after the fourth reflow cycle with a magnification of 4000×. (<b>a</b>) SEM image in SE mode. (<b>b</b>) Combined EDX maps of Ni, Cu, Ag, and Sn. (<b>c</b>) EDX map of Ni. (<b>d</b>) EDX map of Cu. (<b>e</b>) EDX map of Ag. (<b>f</b>) EDX map of Sn.</p> Full article ">Figure 13
<p>EDX analysis of an X7R MLCC after the eighth reflow cycle with a magnification of 4000×. (<b>a</b>) SEM image in SE mode. (<b>b</b>) Combined EDX maps of Ni, Cu, Ag, and Sn. (<b>c</b>) EDX map of Ni. (<b>d</b>) EDX map of Cu. (<b>e</b>) EDX map of Ag. (<b>f</b>) EDX map of Sn.</p> Full article ">Figure 14
<p>Line scan overviews along the given path (compare <a href="#metals-14-00986-f009" class="html-fig">Figure 9</a>) of an X7R MLCC after the (<b>a</b>,<b>b</b>) first, (<b>c</b>,<b>d</b>) second, (<b>e</b>,<b>f</b>) fourth, and (<b>g</b>,<b>h</b>) eighth reflow cycle, showing the evolution of the Cu<sub>6</sub>Sn<sub>5</sub> IMC (left-hand side) and the distribution of Ag within the solder (right-hand side), standardized to a total concentration of 100% (<span class="html-italic">y</span>-axis). Green: Ni. Red: Cu. Gray: Sn. Blue: Ag. While a continuous IMC layer has already formed at the interface solder/PCB metallization after the first reflow cycle, it takes four reflow cycles to form a proper IMC layer at the interface solder/component termination. During several reflow cycles, the Ag depletion zones at the interfaces diminish, and the Ag seems to distribute more and more uniformly within the solder paste. The depicted diagrams were taken directly from the EDX software QUANTAX ESPRIT (version 2.0) without editing. The ordinate shows the concentration in %, and the abscise (‘Weg/µm’) shows the distance along the scanning path. The algorithm of the used EDX software seems not always to be able to standardize the total concentration to 100%, which causes the differences in the tin concentration in the center of the solder joints.</p> Full article ">Figure 15
<p>Averaged height of the Cu6Sn5 IMC at the interface between (<b>a</b>) the solder paste and the PCB metallization (R<sup>2</sup> = 0.96), and (<b>b</b>) the solder paste and the MLCC component (R<sup>2</sup> = 0.54). As the values were only measured after one, two, four, and eight reflow cycles, the remaining values were interpolated using a linear fit.</p> Full article ">Figure 16
<p>Cycle-Capacitance diagram of the measured values of KEMET C1206C106K4PAC7800+ (dielectric X5R, size 1206, nominal capacitance 10 µF ± 10%) for eight reflow cycles. The values behave in a similar way, including an increase after the first two reflow cycles, a decrease between the third and the fifth one, and further increases during the last three ones.</p> Full article ">Figure 17
<p>Cycle-Capacitance diagram of the measured values of KEMET C1206C474K5RACTU (dielectric X7R, size 1206, nominal capacitance 470 nF ± 10%) for eight reflow cycles. Except for sample number 6, the values behave in a similar way, including an increase after the first two reflow cycles, a decrease between the third and the fifth one, and further increases during the last three ones.</p> Full article ">Figure 18
<p>Cycle-Capacitance diagram of the measured values of Yageo CC1206ZPY5V7BB475 (dielectric Y5V, size 1206, nominal capacitance 4.7 µF ± 20%) for eight reflow cycles. The values behave in a similar way, including an increase after the first two reflow cycles, a decrease between the third and the fifth one, and further increases during the last three ones.</p> Full article ">Figure 19
<p>Cycle-Capacitance diagram of the measured values of Yageo CC1206JRNPO9BN681 (dielectric NP0, size 1206, nominal capacitance 680 pF ± 5%) for eight reflow cycles. The values remain mainly constant, with very small deviations.</p> Full article ">Figure 20
<p>Results of the shear test with respect to the number of reflow cycles conducted The green box marks the first and third quartiles, the black line within the box marks the median, and the red dot marks the mean.</p> Full article ">Figure 21
<p>EDX analysis of a shear tested resistor after one reflow cycle. (<b>a</b>) SEM image in SE mode with a magnification of 300× and (<b>b</b>) associated combined EDX map of Cu, Ni, Ag, Sn and Al. (<b>c</b>) Detailed SEM image in SE mode of the location between the ragged resistor and the Cu pad of the PCB with a higher magnification of 2000× and (<b>d</b>) associated combined EDX map of Cu, Ag, Sn, and Al (here, the Ni barrier neither adhered to the ceramic body nor to the solder). For each pair of pictures, the same settings were used.</p> Full article ">Figure 22
<p>EDX analysis of a shear tested resistor after two reflow cycles. (<b>a</b>) SEM image in SE mode with a magnification of 300× and (<b>b</b>) associated combined EDX map of Cu, Ni, Ag, Sn and Al. (<b>c</b>) Detailed SEM image in SE mode of the location between the ragged resistor and the Cu pad of the PCB with a higher magnification of 2000× and (<b>d</b>) associated combined EDX map of Cu, Ni, Ag, Sn, and Al. For each pair of pictures, the same settings were used.</p> Full article ">Figure 22 Cont.
<p>EDX analysis of a shear tested resistor after two reflow cycles. (<b>a</b>) SEM image in SE mode with a magnification of 300× and (<b>b</b>) associated combined EDX map of Cu, Ni, Ag, Sn and Al. (<b>c</b>) Detailed SEM image in SE mode of the location between the ragged resistor and the Cu pad of the PCB with a higher magnification of 2000× and (<b>d</b>) associated combined EDX map of Cu, Ni, Ag, Sn, and Al. For each pair of pictures, the same settings were used.</p> Full article ">Figure 23
<p>EDX analysis of a shear tested resistor after four reflow cycles. (<b>a</b>) SEM image in SE mode with a magnification of 300× and (<b>b</b>) associated combined EDX map of Cu, Ni, Ag, Sn and Al. (<b>c</b>) Detailed SEM image in SE mode of the location between the ragged resistor and the Cu pad of the PCB with a higher magnification of 2000× and (<b>d</b>) associated combined EDX map of Cu, Ni, Ag, Sn, and Al. For each pair of pictures, the same settings were used.</p> Full article ">Figure 24
<p>EDX analysis of a shear tested resistor after eight reflow cycles. (<b>a</b>) SEM image in SE mode with a magnification of 300× and (<b>b</b>) associated combined EDX map of Cu, Ni, Ag, Sn and Al. (<b>c</b>) Detailed SEM image in SE mode of the location between the ragged resistor and the Cu pad of the PCB with a higher magnification of 2000× and (<b>d</b>) associated combined EDX map of Cu, Ni, Ag, Sn, and Al. For each pair of pictures, the same settings were used.</p> Full article ">Figure 25
<p>Light microscopy images with a magnification of 5× of the non-ragged side of resistors after the shear test after (<b>a</b>) one, (<b>b</b>) two, (<b>c</b>) four, and (<b>d</b>) eight reflow cycles.</p> Full article ">
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