System BUS

Validation of a wireless radio on a standard prototyping platform is a major part of the development process. Typically the hardware is predefined in these platforms, which sometime requires bridge designs for bus protocol translation. This paper presents a system bus-to-SPI bridge design and its implementation.

Addresses the design and specification of a heterogeneous HW/SW architecture of a SOC (system-on-a-chip) for pattern recognition. In this design, a RISC processor is used along with specialized optimized coprocessors all articulated around a system bus (PI-bus). Once the algorithms involved are presented, we investigate the hardware/software codesign methodology, relying on the use of a system level simulator and extensive