MRI image processing

Currently, Field Programmable Gate Array (FPGA) goes beyond the low-level line-by-line hardware description language programming in implementing parallel multidimensional image filtering algorithms. High-level abstract hardware-oriented parallel programming method can structurally bridge this gap. This paper proposes a first step toward such a method to efficiently implement Parallel 2-D MRI image filtering algorithms using the Xilinx system generator. The implementation method consists of five simple steps that provide fast FPGA prototyping for high performance computation to obtain excellent quality of results. The results are obtained for nine 2-D image filtering algorithms. Behaviourally, two Virtex-6 FPGA boards, namely, xc6vlX240Tl-1lff1759 and xc6vlX130Tl-1lff1156 are targeted to achieve; lower power consumption of (1.57 W) and down to (0.97 W) respectively at maximum sampling frequency of up to (230 MHZ). Then, one of the nine MRI image filtering algorithms, has empirically improved to generate an enhanced MRI image filtering with moderate lower power consumption at higher maximum frequency. I. INTRODUCTION FPGAs are increasingly used in modern parallel algorithm applications such as medical imaging [1], DSP [2], image filtering [3], power consumption in portable image processing [4], MPEG-4 motion estimation in mobile applications [5], satellite data processing [6], new Mersenne Number Transform [7][8], high speed wavelet-based image compress [9] and even the global communication link [10]. However, most of the above FPGA-based solutions are typically programmed with low-level hardware description languages (HDL) inherited from ASIC design methodologies [11]. On the other hand, parallel multidimensional image filtering algorithms[12], for aerospace, defence, digital communications, multimedia, video and imaging industries, demand insatiable computationally complex operations [13] [14] at maximum sampling frequency. Traditional DSP processor arrays, with fixed architectures and relatively short life, can be costly programmed line-by-line with thousands of code's lines [15] [16]. Alternatively, this paper presents a high-level abstract implementation method to fill the present programming gap between parallel algorithms coding and final FPGA implementation. The proposed FPGA implementation method is architecturally based on the Xilinx system generator development tool [17] within the ISE 11.3 development

In this era, enhancement of Magnetic Resonance (MR) images is very important in clinical diagnosis as well as digital image processing. Noise hindrance as well as intensity inhomogeneity can adversely affect quantitative analysis of the image due to which accurate process of brain images is a very difficult task. Therefore, pre-processing of MR images is very essential before processing into an application. In this paper, we enhanced the images by applying bias field correction to reduce the intensity inhomogeneity. Although the bias field correction method enhanced the quality, it was not more effective in terms of performance and removing the noise. Therefore, we used denoising method on the bias field corrected image to reduce the noise and improve the quality of MR images. Furthermore, the quality of enhanced image by using these two methods is being analyzed through the performance parameters such as Peak Noise to Signal Ratio (PSNR), Mean Square Error (MSE) and Structural Similarity Index Map (SSIM).