Abstract Hardware resources can be shared to reduce the area of the resulting design. The synthesis system must ensure that no resource conflicts arise due to simultaneous access of a shared hardware,resource. With traditional scheduling...
moreAbstract Hardware resources can be shared to reduce the area of the resulting design. The synthesis system must ensure that no resource conflicts arise due to simultaneous access of a shared hardware,resource. With traditional scheduling formulations where operations are statically assigned to control steps, conflict resolution simply determines whether two operations can execute concurrently based on their control step assignment. In this case, operations are assumed,to have fixed execution delay. For hardware,models,that supports external synchronization and handshaking, however, operations may have unbounded execution delay , e.g., detecting the rising edge of a signal. The presence of unbounded,delay operations invalidates the traditional scheduling and conflict resolution approaches. We formulate in this paper conflict resolution as the task of serializing operations bound,to the same,hardware resource. A technique called constrained conflict resolution is presented to resolve resource conflicts such that the resulting design satisfies the required timing and handshaking,requirements. The timing constraint topology is used to reduce the computation,time of the algorithm. This technique extends the relative scheduling formulation to support resource sharing under timing constraints. We describe both exact and heuristic algorithms to resolve resource conflicts; these algorithms are implemented,in a synthesis system,called Hebe that is targeted towards the synthesis of Application-Specific Integrated Circuit designs. Results of applying the system to the design of benchmark,and complex,ASIC designs are presented. Keywords: Resource conflict resolution, high-level synthesis, automated synthesis, behavioral synthesis, hard-
