Fet

This paper discusses a comprehensive analytical study of electrical properties of sin-gle‐wall conventional carbon nanotube field‐effect transistor (CNTFET) devices of subthreshold swing (SS), transconductance (g m), and extension resistance. The analytical expressions for SS and g m have been derived based on channel modulated potential. In the study, it was observed that SS value of the CNTFET device is equal to 60 mV/decade, which is smaller than the conventional and double gate metal‐ oxide‐semiconductor field‐effect transistors. The subthreshold swing degrades at larger tube's diameter and gate‐source voltage due to increased source‐drain leakage current. Carbon nanotube field‐effect transistor devices achieve larger g m at large gate‐source voltage, which has a disadvantage of reducing the allowable voltage swing at the drain. The extension resistance of the device falls with diameter of the tube. The subthreshold swing (SS) is the important parameter to sustain the scaling of silicon transistor because leakage power is strongly influenced by SS of the device. Subthreshold swing value indicates the minimum gate‐source voltage (V gs) required to lower the subthreshold current by a factor of 10. Steep SS devices are of great interest due to demand of power and energy‐efficient digital circuits. As metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) scaled below 45 nm, the subthreshold leakage current becomes more significant due to short‐channel effects (SCEs), parameter variations, 1-3 and strong coupling between temperature and subthreshold leakage current. 4,5 The fundamental thermodynamic limit on the minimum operational voltage and switching energy of the conventional FETs is ideally 60 mV/decade at room temperature, but in practice , the gate oxide screens the gate fields and the coupling between the gate and channel is not perfect, which causes SS to be larger than the ideal value. 6-10 The carbon nanotube FET (CNTFET) is a promising candidate for future electron devices, and rapid progress in this field has made it possible to fabricate CNTFET‐based integrated circuits. In facts, CNTFET is the substitute of silicon MOS due to excellent control of SCEs 11-13 as well as physical and electrical properties. 14,15 Although the SS of the CNTFET device has been reported theoretically by researchers, 16-18 this parameter has not been discussed in detail compared with the other parameters. In nanotube junctions, the parasitic resistance (R P) is given as the sum of contact resistance (R C) and the extension resistance (R ext). The R ext contributes more in the R P than in the R C. Lower R ext improves the intrinsic performance of the device. 19 In the literature, less attention has been given on the study of R ext compared with R C. 20 In this paper, we studied the SS and R ext of CNTFET after using our previously derived drain current equation. 15 The SS is close to 60 mV/decade at room temperature in CNTFET device. We have also observed that the SS of the CNTFET device is

In this paper, we present a systematic study of the role of metal/semiconductor nanowire (NW) contact in back-gated Ge and Si NW Schottky-barrier (SB) FETs. Our results show that the performance of such devices is largely dominated by the carrier injection efficiency at the source contact, which, in turn, is controlled by metal contact depth and gate bias. Using low-temperature annealing of back-gated Ge and Si NW SB FETs with nickel (Ni) contacts as source and drain, we monitor the evolution of the device current as the contact metal progressively diffuses into the NWs. The drain current, which is measured at a given gate and drain bias, first increases as the contact metal diffuses into the NW, reaches a maximum, and subsequently decreases. These results can be explained by the interplay between carrier injection efficiency through the metal/NW SB, which increases with the metal contact depth, and the number of available states in the NW between contact and the bottom oxide, which decreases with the metal contact depth.