Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112 Contents lists available at ScienceDirect Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging Xiaochao Fang, Nicolas Ollivier-Henry, Wu Gao, Christine Hu-Guo, Claude Colledani, Bernard Humbert, David Brasse, Yann Hu n Institut Pluridisciplinaire Hubert Curien (IPHC), UMR 7178 CNRS/ULP, 23 rue du Lœss, 67037 Strasbourg, France a r t i c l e i n f o a b s t r a c t Article history: Received 2 August 2010 Received in revised form 26 November 2010 Accepted 17 January 2011 Available online 26 January 2011 This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 mm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 mV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper. & 2011 Elsevier B.V. All rights reserved. Keywords: Positron emission tomography (PET) Front-end readout Delay-locked loop (DLL) Time-to-digital converter (TDC) Multi-channel plate (MCP) 1. Introduction Positron emission tomography (PET) is a noninvasive molecular imaging technique that measures the in vivo biodistribution of imaging agents labeled with positron-emitting radionuclides [1]. The physical principle is based on the detection of gamma radiations resulting from positrons emitted in the disintegration of radiotracer. A pair of 511 keV photons results from the annihilation of a positron and an electron. A line of response (LOR) is defined by these two photons (511 keV) emitted in opposite directions and detected in coincidence. The energy deposited by each photon inside the detector is converted into an electrical signal, which is amplified and digitized by readout electronics. The whole set of LORs is then used to reconstruct the 3D distribution of the radiotracer [1,2]. The quality of the image is limited both by the spatial resolution and the absolute detection efficiency of the system. The improvement of system resolution n Corresponding author. E-mail address: Yann.hu@ires.in2p3.fr (Y. Hu). 0168-9002/$ - see front matter & 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2011.01.082 pushes processing requirements on both novel detectors and the front-end data acquisition systems [3]. In the case where the system requires many hundreds or even thousands of readout channels, a mixed-signal application-specific integrated circuit (ASIC) [4] is needed to provide a compact platform for processing the many signals with charge integrators, pulse shapers, discriminators, TDC and so on for each detector element. In reality, the architecture and the specifications of the ASIC depends on the configuration of detector modules using photomultiplier tubes (PMTs), avalanche photodiodes (APDs) or silicon photomultiplier (SiPM) coupled to scintillating crystals such as bismuth germanate (BGO), lutetium oxyorthosilicate (LSO) and lutetium yttrium oxyorthosilicate (LYSO). Generally, PMTs are widely used in the PET imaging systems due to high linear gain and broad dynamic range. Several ASICs have been developed for PMTs with different scintillating crystals in Refs. [5–8]. A 64-channel mixed-signal front-end integrated circuit (IC) dedicated to read out a LSO/PMT for medical PET imaging was presented [5]. In this IC, each channel consisted of a low-noise CSA, a RC-CR pulse shaper and a winner-take-all multiplexer. Moreover, a custom mixed-signal CMOS integrated circuit was developed for high-performance PET front-end applications [6,7]. The chip, which included a 312.5 ps X. Fang et al. / Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112 TDC, was dedicated to the voltage pulses from four channel LSO/ PMTs. Fischer et al. [8,18] presented a full-custom ASIC optimized for LYSO/PMT, which integrates time-stamping, energy estimation and position finding for time-of-flight (TOF) PET. The coincidence timing resolution was 330 ps (FWHM). Meanwhile, a few novel ASICs were recently designed for APDs coupled with high-performance scintillating crystals in Refs. [9–14]. An ASIC to enable the implementation of LSO/APD arrays in PET was developed [9,10]. The chip can accommodate both positive and negative input signals, with a programmable conversion gain from 2.8 to 21 mV/fC. In Ref. [11], the analog signal processing electronics were fully integrated into monolithic chips dedicated to LSO/APD as well for a small-animal PET scanner. Each chip contained four independent differential receivers, shaping amplifiers, peak hold detectors and non-delay line constant-fraction discriminators (CFDs). Moreover, a 9-channel waveform sampling front-end ASIC for readout of GSO/ APD was proposed in Ref. [12]. The prototype chip consisted of a preamplifier, a variable gain amplifier and a fast ADC. Furthermore, an 8-channel front-end ASIC for high spatial resolution PET detectors with TOF capability based on LYSO/APD arrays [13] was designed. Energy resolution of 9.7% (FWHM) was obtained at 511 keV with a timing resolution below 970 ps. There are also some ASICs developed for SiPM-based-PET applications [15–20]. Herrero-Bosch et al. [15] proposed an integrated front-end based on a current preamplifier and a resistor network. An error of less than 15% of the multianode SiPM pitch has been reported. A 36-channel chip SPIROC for an ILC hadronic calorimeter technical prototype with SiPM readout was presented in Ref. [16]. Both the charge and the timing can be measured due to the integration of a TDC with a resolution of 100 ps and an ADC with a resolution of 0.6 mV per channel in the chip. This proposed chip can also be used in PET applications. A fullcustom 16-channel ASIC has been reported in Refs. [17,18] for LYSO/ SiPM. Both timing and energy can be measured by this chip. Its coincidence timing resolution is 20 ps (rms). Corsi et al. [19] has presented an 8-channel front-end ASIC for SiPM detectors. In this chip, each channel is composed by a current buffer, a discriminator, a CSA and a peak detector. Moreover, an 8 bit successive-approximation-register (SAR) ADC has also been integrated in the chip. This ASIC provides a timing resolution of 651.5 ps and an energy measurement error less than 3%. This paper focuses on the design and performance characteristics of a front-end ASIC dedicated to an innovative configuration using LYSO crystals read by multi-channel plate photo multipliers (MCPPMTs). The ASIC called IMOTEPAD is developed for a multi-modality imaging system including small-animal PET imaging [4]. The goal of the PET project is to obtain a detection efficiency greater than 15% keeping a spatial resolution of 1 mm3 [14]. Both energy signals and trigger from the photodetectors are read out by this front-end chip. For energy measurements, according to the arrangement of the detectors, the front-end electronics has to be designed for a large dynamic range (from few fC to 104 pC) and a low nonlinearity error. Meanwhile, a high-speed discriminator and a sub-nanosecond TDC are required as well for the measurement of time stamps. In Section 2, an overview of the PET system is presented. In Section 3, the design of the proposed front-end readout chip is described. However, only the implementation detail of the TDC will be discussed, since the design of the energy measurement has already been reported in Ref. [25]. In Section 4, the experimental results of the IMOTEPAD are shown and discussed. 107 photomultiplier tubes (PMTs). Normally, the spatial resolution is limited by the detection efficiency with these PET imaging systems. It means that we cannot obtain a high resolution with good detection efficiency due to the depth of interaction (DOI) error. In our configuration [20], shown in Fig. 1, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As shown in Fig. 1, the PET system consists of four modules arranged around the animal. Each module is composed of a matrix of 32  24 LYSO (Ce) crystals of 1.5 mm  1.5 mm  25 mm. Each pixel of matrix is read at both ends by a Photonis Corp. MultiChannel Plate (MCT, Planacon 85022-600)-PMT. Consequently, the PET imaging system is composed of 3072 crystals and 6144 electronic channels. These channels will be read out by 24 printed circuit boards (PCB). On each board, there are four 64-channel ASIC IMOTEPAD. Fig. 2 presents the arrangement of the detector modules and the readout electronics system. The proposed architecture of IMOTEPAD is shown in Fig. 3. The output charges of the PMT are collected and converted to voltage signal by the energy measurement. The analog memory allows us to Fig. 1. Arrangement of detector modules and LYSO crystals. 2. PET system overview In most PET systems dedicated to small-animal imaging [21,22], the geometry of the detector module is based on a block structure where the crystal elements are coupled to a reduced number of Fig. 2. Arrangement of the detector modules and the readout electronics system. 108 X. Fang et al. / Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112  A sub-nanosecond precision for time measurement with a high do the measurement continually. Then the measured energies are sent to output serially with a multiplexer controlled by the readout logic. For each detected event, the discriminator generates a time stamping signal indicating when a gamma ray is detected. This time mark signal is digitized by a TDC. The digitalized time information is also serialized and sent to the output. This multi-channel front-end readout ASIC is an essential element for the DAQ of the PET imaging system. The performances of the chip directly affect the quality of the reconstructed images. The characteristics of the chip will be carefully measured and discussed. In order to fulfill the requirement of the PET architecture, this 64-channel front-end readout chip has to take up several important challenges such as: performance TDC. 3. Circuit descriptions Fig. 4 represents one-channel schematic of the IMOTEPAD. The large bandwidth preamplifier with a gain of about 1 reduces considerably the input impedance but does not affect the signal pass-through. The gain-adjustment stage is used to adjust precisely the gain of amplification due to the gain dispersion of the photodetector’s anodes. The integration time of 1 ms is chosen to collect the maximum charges and at the same time avoid the pileup problem when the event frequency is 100 KHz. After being filtered and formed by the shaper, the maximum value of the signal, which corresponds to the energy is saved in the analog memory. The storage is realized by the sample-and-hold circuit, which includes two switches and capacitors. This operation allows a continuous readout without any dead time during the measurement. In Refs. [23,24], similar structures have been reported. However, in our structure, a current comparator is used to give precisely a time stamp for the arrival moment of an event.  Large dynamic range varying from few fC to 104 pC. It   corresponds to a variation of the input signal induced by the different positions of the scintillation along the axial extent of the crystal. Nonlinearity less than 3% and the signal-to-noise ratio (SNR) better than 40 dB. A very small input impedance in order to decrease the crosstalk between channels. Charge-Energy measurement AMP PM Energy measurement Discri TDC PM Energy measurement Discri Analog M U Memory X TDC Discri TDC PM Energy measurement M U X Time Stamp 16 bits DLL Readout Logic Bias DAC JTAG IMOTEPA IMOTEPD Fig. 3. Architecture of the IMOTEPAD. III. CIRCUIT DESCRIPTION Integrator vdda Vdd_hv 100k 100k -Ao Sample and Hold vref 10p A 3p Preamplifier A 1p 300k Shaper Gain Adjustment Enegery Output Buffer vdda Detector (LYSO+MCP) vtresh 2p Iref Current Comparator Hold Time 100k TDC Monostable Hit Fig. 4. One-channel schematic of the front-end ASIC. 109 X. Fang et al. / Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112 This moment is delayed by about 300 ns (corresponding to the shaping time; the delay value is programmable) by the monostable circuit to sample the peak value of the signal. At the same time, the time stamp is digitized by the TDC. A 10-channel prototype, composed by a preamplifier, an integrator, a shaper, a sample-and-hold circuit, a current comparator and a monostable circuit, has been designed in Ref. [25]. In this paper, only the design details of the TDC will be given. clk counterRE 0 1 1 counterFE 3 2 2 3 4 MSB of fine time Fig. 6. Method to avoid the metastable status of the counters. 3.1. TDC The architecture of the TDC is shown in Fig. 5. The main advantages of this architecture are wide range, high resolution and low static power consumption. The architecture can be easily extended to multiple channels such as 64 channels or 128 channels. Moreover, good performances on differential nonlinearity (DNL) and integral nonlinearity (INL) can be achieved by using low-jitter DLL techniques. In this architecture, the data readout circuits, which consist of the samplers, encoders and registers, are pure digital circuits thus they can be easily obtained by a digital top-down design. This TDC works with a reference clock of 50 MHz. The 9 bit counters extend the measurement range to 10 ms, which corresponds to the period of event. One period of the reference clock is divided into 32 intervals by the DLL with 32 delay cells. As a result, the value of every interval is equal to 625 ps, which corresponds to the bin size of the TDC. 32 delays correspond to 32 different stats of a hit during a period of the clock. These 32 stats are coded into 5 bit fine time by the encoder. Two counters are employed to avoid the metastable status. As shown in Fig. 6, the MSB of the fine time selects the result of a counter on stable status as the coarse time. During the first half period of the clock, the counter working on falling edge (counterFE) is selected because the counter working on rising edge (counterRE) has a metastable period. Otherwise the counterRE should be selected to avoid the metastable period of the counterFE. 3.2. DLL the DLL is employed as a timing generator, clkout and clock have a fixed latency of one clock period and the outputs of delay cells in VCDL are the multiphase delayed clocks (Q1, Q2,y, QN). However, the conventional DLL usually suffers from fail-to-lock or false-lock problems to more than one clock cycle [26]. In our design, an Initialization Controller is embedded in the DLL for solving these problems. As shown in Fig. 7, four signals, Up0, Down0, select and Charge are generated by this digital part. When the Reset signal is valid after power ON, the Up and Down are generated from the initialization controller. The capacitor is charged to positive power supply (vdd). The initial state of VCDL is set to generate the smallest delay. In this moment the delay difference between clock and clkout is maximized. Then we open the charge signal and begin to discharge Cfiltre in the loop filter, and thus decrease the delay difference. When the delay difference is smaller than the half period of the clock, the Initialization Controller will be released and the phase detector will be selected as a phase comparator. At that time, the DLL behaves as an analog chargepump DLL. The jitter performances of the DLL should be taken into account. In a charge-pump DLL, the jitter of the output clocks comes from input signal noise, circuit noise and leakage current. A jitter model has been given in Refs. [27,28]. The jitter of the output clock, the input clock, VCDL and controlled voltage presented by dOUT, dIN, dVCDL and dVC are described in Eqs. (1)–(5). qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð1Þ dOUT ¼ d2IN þ d2VCDL þ d2Vc 2pyIN Tclk dIN ¼ The proposed DLL is shown in Fig. 7. As usual, the DLL consists of a phase detector, a charge-pump, a loop filter and VCDL. When dVCDL ¼ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1KT þKT2 þ dclk 1 þ KT 2p yVCDL qffiffiffiffiffiffiffiffiffiffiffiffi Tclk 1K 2 ð2Þ ð3Þ T clock DLL Counter Counter KT ¼ hit Registers Registers Encoder 9 bits MUX 5 bits hold Registers 9 bits 32 bits Registers MSB 9 bits Registers Fine time (5 bits) Coarse time (9 bits) Fig. 5. Architecture of the TDC. 2p KVCDL DVc Tclk ð4Þ 9 bits 9 bits 32 bits dVC ¼ 2pKVCDL ICP Cfilter ð5Þ where Tclk is the period of the reference clock, yIN is the input phase error caused by the signal noise, dclk represents the time error caused by the noise and the slope variation of the clock, yVCDL is the VCDL output phase error, KVCDL is the gain of the VCDL in s/V, DVc is the voltage noise of the capacitor (Cfilter) in the loop filter and ICP represents the charge and discharge current in the charge-pump. The VCDL and loop filter exhibit significant contributions to total jitter performances. Generally, the worst jitter occurs at the last delay cell of the VCDL. The optimization of jitter performances depends on the value of KT in Eqs. (1)–(5). In order to reduce the dOUT, KVCDL and ICP should be minimized and the value of capacitor (Cfilter) should be maximized. According to Eqs. (1)–(5), in the design, the values chosen are equal to 90 pF, 10 mA and 580 ps/V (when DLL is locked) for Cfilter, ICP and KVCDL, respectively. 110 X. Fang et al. / Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112 Voltage Control Delay Line (VCDL) clock Q1 Qn-1 Q2 Phase Detector Up1 Down1 Initialisation Up0 Down0 MUX clkout Qn vdd Icp Vdd Icp Cfilter Charge Up Down select Charge Pump Loop filter Fig. 7. Architecture of the DLL. Fig. 9. Integral nonlinearity of channels according to injected charges ranging from 0.5 to 70 fC. Fig. 8. Microphotograph of the chip bonded on test board. 4. Experimental results The IMOTEPAD has been implemented in an AMS (Austriamicrosystems AG) CMOS 0.35 mm process with a 3.3 V power supply. Its size is 3.680 mm  8.257 mm. To avoid package parasitic capacitance and resistance, chips were unpackaged and wirebonded directly to the test board, which provided access to the inputs, bias control and outputs. Fig. 8 shows a microphotograph of the IC bonded on test board. The energies are sent serially to output by a full differential amplifier and digitized by a 14 bit high speed ADC on the test board. The time data has 16 bits per channel (including the error bit and the event bit). As a result we have to send 1024 bit data for 64 channels in less than 10 ms. A low-voltage differential signaling (LVDS) driver is employed to send these time data with a frequency as high as 125 MHz [29]. The LVDS PADs are indicated Fig. 10. Nonlinearity of the energy value versus the code. in Fig. 8. Thanks to the application of the serial transmission method, we saved the amount of PADs and also simplified the test. Linearity of the front-end readout chip, which is directly related to the energy resolution, is important to improve the rejection of scatter events in PET imaging systems. From Fig. 9, we can observe a typical curve of the INL, which shows an INL o2%. For all channels, INL is less than 3%. In addition, the chip operates under the variable gain stages, which are realized by the gain- 111 X. Fang et al. / Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112 adjustment circuit. The gain is controlled by a 6 bit DAC; the decimal values of the code from 0 to 63 correspond to the gain from 0 to 4. We measured the performances of nonlinearity for Fig. 13. RMS jitter of fine conversion. Fig. 11. Fine time measured according to the delay of an event varying from 0 to 20 ns compared with the reference clock. Table 1 Summary of the performances of the IMOTEPAD. Characteristics Test Dynamic range Crosstalk Input impedance Power consumption Few fC to 104 pC o 0.2% 180 O 16.8 mW/channel IMOTEPA CR-RC peaking time Nonlinearity RMS noise Gain 280 ns o 3% 300 mV 13.1 mV/pC IMOTEPD Jitter DNL (LSB) INL (LSB) 42 ps (rms) 7 0.17 7 0.31 different gain stages. Fig. 10 shows the nonlinearity of a channel while the input was fixed and the code was varied. For all channels, we have almost the same curve. It can be seen that lower nonlinearity is achieved at higher gain stages. Thanks to the preamplifier, the input impedance of the circuit is as small as 180 O and the crosstalk between channels is less than 0.2%. The peaking time measured is about 280 ns. The RMS noise of the analog part is 300 mV. The TDC was measured with a reference clock of 50 MHz. The bin size of 625 ps has been obtained. The performances were obtained by code density test from the collection of the 640,000 events (about 20,000 points for each digital code) by sampling signal at the condition of 27 1C and the power supply of 3.3 V. Fig. 11 shows the fine time measured according to the delay of an event varying from 0 to 20 ns compared with the reference clock. The DNL and INL performances are shown in Fig. 12. The maximum value of DNL and INL are 0.17 LSB and 0.31 LSB, respectively. The RMS jitter is represented in Fig. 13. Its maximum value is equal to 42 ps. The performances of the chip are summarized in Table 1. 5. Conclusion Fig. 12. Differential nonlinearity and integral nonlinearity of fine conversion. This paper presents the design and characteristics of a new front-end readout ASIC dedicated to PET imaging systems for biomedical research. This developed 64-channel chip provides 112 X. Fang et al. / Nuclear Instruments and Methods in Physics Research A 634 (2011) 106–112 trigger and also energy signals from the photodetectors. The triggers are sent to a multi-channel TDC for the measurement of time stamps. Meanwhile, the energy signals are digitalized by an external ADC. The main results of measurement are depicted and discussed. It is shown that the function of the chip is correct and the results well match the specifications. Low nonlinearity and high trigger efficiency are achieved. The TDC achieves a timing resolution of 625 ps. Moreover, the performance of crosstalk shows that the architecture of preamplifier is absolutely suitable for the MCP detectors. Acknowledgements The authors would like to thank Patrick Bard and Christian Fuchs from IPHC at Strasbourg for the technical support. References [1] Gray D. Hutchins, Michael A. Miller, Victor C. Soon, et al., ILAR Journal 49 (2008) 54. [2] N.C. Rouze, M. Schmand, S. Siegal, G.D. Hutchins, IEEE Trans. Nucl. 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